JPH02277263A - Resistance network - Google Patents

Resistance network

Info

Publication number
JPH02277263A
JPH02277263A JP9851789A JP9851789A JPH02277263A JP H02277263 A JPH02277263 A JP H02277263A JP 9851789 A JP9851789 A JP 9851789A JP 9851789 A JP9851789 A JP 9851789A JP H02277263 A JPH02277263 A JP H02277263A
Authority
JP
Japan
Prior art keywords
resistor
resistors
unit diffused
resistance
series
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9851789A
Other languages
Japanese (ja)
Inventor
Yasushi Igawa
井川 保志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Industries Corp
Original Assignee
Toyoda Automatic Loom Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyoda Automatic Loom Works Ltd filed Critical Toyoda Automatic Loom Works Ltd
Priority to JP9851789A priority Critical patent/JPH02277263A/en
Publication of JPH02277263A publication Critical patent/JPH02277263A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a resistance-value ratio whose accuracy is high and whose temperature tracking characteristic is excellent by a method wherein a plurality of resistances formed by connecting a plurality of unit diffusion resistances of an identical shape in series or in parallel are provided via a plurality of conductive members which are formed in an identical process. CONSTITUTION:A plurality of unit diffusion resistances 2, 2', of an identical shape, of a second conductivity type are formed side by side at equal intervals inside a semiconductor substrate of a first conductivity type; a semiconductor process to form an insulating film and to form contact holes 3, 3', 5, 5' is executed. After that, conducting members 4, 4' are formed; a resistance formed by connecting the plurality of unit diffusion resistances 2, 2' in series or in parallel via the members is formed at the same time. Thereby, temperature coefficients of a plurality of resistances become nearly uniform; a temperature tracking characteristic of a resistance-value ratio between the individual resistances becomes good.

Description

【発明の詳細な説明】 〔概   要〕 本発明は、半導体基板内に熱拡散又はイオン注入等の工
程により複数の単位拡散抵抗を等間隔で同時に並設して
形成し、さらにそれらの複数の単位拡散抵抗を第1の導
電性部材及び第2の導電性部材を介して直列又は並列に
接続することにより、それぞれ抵抗値精度の高い第1の
抵抗器、第2の抵抗器を形成したものであり、上記単位
拡散抵抗が同一のフォトリソグライエ工程により工程で
近接して形成されることから、各単位拡散抵抗の抵抗値
を抵抗値偏差を少なくかつ高精度に設定できると共に各
単位拡散抵抗の温度係数を非常に均一なものとなし得る
ので上記第1の抵抗器と上記第2の抵抗器の抵抗値比は
高精度でかつ非常に温度トラッキング特性に優れたもの
となる。また同一ウェハ上に多数の抵抗ネットワークの
チップを形成できるので量産性に優れており、高精度で
かつ温度トラッキング特性に優れた抵抗値比を有する抵
抗ネットワークを低コストで製造することが可能となる
[Detailed Description of the Invention] [Summary] The present invention involves forming a plurality of unit diffused resistors in parallel at equal intervals in a semiconductor substrate by a process such as thermal diffusion or ion implantation. By connecting unit diffused resistors in series or in parallel via a first conductive member and a second conductive member, a first resistor and a second resistor each having high resistance value accuracy are formed. Since the unit diffused resistors are formed in close proximity in the same photolithography process, the resistance value of each unit diffused resistor can be set with high accuracy with little resistance value deviation, and each unit diffused resistor can be set with high accuracy. Since the temperature coefficient of can be made very uniform, the resistance value ratio of the first resistor and the second resistor can be highly accurate and have excellent temperature tracking characteristics. In addition, since multiple resistor network chips can be formed on the same wafer, mass production is excellent, making it possible to manufacture resistor networks with high precision and resistance value ratios with excellent temperature tracking characteristics at low cost. .

〔産業上の利用分野〕[Industrial application field]

本発明はアナログ回路で広く用いられる抵抗ネットワー
クに係り、特に高精度でかつ温度トランキング特性に優
れた抵抗値比を得ることが可能な抵抗ネットワークに関
する。
The present invention relates to a resistor network widely used in analog circuits, and particularly to a resistor network that is highly accurate and can obtain a resistance value ratio with excellent temperature trunking characteristics.

〔従来の技術〕[Conventional technology]

反転増幅回路、非反転増幅回路、及び差動増幅回路、さ
らにはA/Dコンハ゛−タ(アナログ/デジタル・コン
バータ)などの前段におく利得切り替えアンプ等のよう
な高い利得精度を必要とする02771回路、さらには
A/Dコンバータ、D/Aコンバータ(デジタル/アナ
ログ・コンバータ)などに適用される正負基準電圧回路
等のような各抵抗素子間の相対精度が重要視されるアナ
ログ回路においては、調整時間や信頼性の点で大幅な改
善ができることから抵抗ネットワークが広く利用されて
いる。
02771 that requires high gain accuracy, such as an inverting amplifier circuit, a non-inverting amplifier circuit, a differential amplifier circuit, and a gain switching amplifier placed before an A/D converter (analog/digital converter). In analog circuits where relative accuracy between each resistance element is important, such as positive and negative reference voltage circuits applied to circuits, A/D converters, D/A converters (digital/analog converters), etc. Resistor networks are widely used because they offer significant improvements in adjustment time and reliability.

この抵抗ネ・ノドワークは、複数の抵抗器を1つのパッ
ケージに収納したいわゆるチップ抵抗であり、従来厚膜
素子または薄膜素子を用いて得られていた。
This resistor node work is a so-called chip resistor in which a plurality of resistors are housed in one package, and has conventionally been obtained using thick film elements or thin film elements.

厚膜抵抗は、印刷技術を利用してペースト状の材料をイ
ンク抵抗として回路パターンを作った後、約600〜7
00°Cで焼成して作成する。
Thick film resistors are made by using printing technology to create circuit patterns using paste-like materials as ink resistors.
Created by firing at 00°C.

一方、薄膜抵抗はアルミナ基板等の絶縁性基板上にNi
−Cr、Ta2N等の金属膜を真空蒸着法またはスパッ
タ法等により形成して作成するものである。
On the other hand, thin film resistors are made of Ni on an insulating substrate such as an alumina substrate.
- It is created by forming a metal film such as Cr or Ta2N by a vacuum evaporation method or a sputtering method.

上記2種類の抵抗ネットワークのうち、上記薄膜抵抗素
子を用いたものは、一般に厚膜抵抗素子を用いたものよ
りも素子密度が高く、ノイズや高周波特性にも優れてお
り、さらに、温度係数が小さく、抵抗値偏差も小さいこ
とから、上記厚膜抵抗よりも高精度の抵抗器を作成する
ことができる。
Of the two types of resistance networks mentioned above, those using the thin film resistance elements generally have higher element density than those using thick film resistance elements, have better noise and high frequency characteristics, and have a lower temperature coefficient. Since it is small and has a small resistance value deviation, it is possible to create a resistor with higher precision than the above-mentioned thick film resistor.

しかも、レーザ・トリミングや陽極酸化法によるトリミ
ングにより、抵抗値精度の向上、TCP(温度係数)を
低下させることが可能であるという利点も有している。
Furthermore, trimming by laser trimming or anodic oxidation has the advantage that it is possible to improve resistance value accuracy and lower TCP (temperature coefficient).

特にTaz N抵抗素子を用いた抵抗ネットワークは陽
極酸化法によりきわめて高精度(±0.1%以下)のト
リミングが可能なうえに、スパッタリング時のN2の量
の制御により、TCRを変化させることができるので温
度係数が零のCR振回路の製造などに利用されている。
In particular, the resistance network using Taz N resistance elements can be trimmed with extremely high precision (±0.1% or less) by anodizing, and the TCR can be changed by controlling the amount of N2 during sputtering. Because of this, it is used in the manufacture of CR oscillator circuits with a zero temperature coefficient.

〔発明が解決しようとする課題] しかしながら、従来の薄膜抵抗素子を用いた抵抗ネット
ワークは、スパッタリングや、フォトリソグラフィ法に
よるバターニング工程など、製造工程数が多いことから
量産化に限界があり、そのため製造コストが高くなると
いう欠点があった。
[Problem to be solved by the invention] However, there is a limit to mass production of resistive networks using conventional thin film resistive elements because of the large number of manufacturing steps such as sputtering and patterning processes using photolithography. The disadvantage was that the manufacturing cost was high.

また、リソグラフィ・エツチング技術におけるパターン
幅(線幅)の制御精度及び位置合わせ精度の技術的制約
により、薄膜抵抗素子の線幅の微細化にも限界があり、
そのためチップサイズの小型化にも限界があるという欠
点もあった。さらに、Ni−Cr、Ta2Nの面積抵抗
値は低いことから薄膜抵抗素子の場合高抵抗化に限界が
あり(約10OKΩ程度まで)、そのため100にΩ以
上の高抵抗には抵抗値精度及び温度係数が薄膜抵抗より
も劣りしかも素子密度が低いことから小型化に難点があ
る厚膜抵抗を用いざるを得ないという問題があった。
Furthermore, due to technical constraints on pattern width (line width) control accuracy and alignment accuracy in lithography and etching technology, there are limits to the miniaturization of line widths in thin film resistive elements.
Therefore, there was also a drawback that there was a limit to miniaturization of the chip size. Furthermore, since the sheet resistance values of Ni-Cr and Ta2N are low, there is a limit to increasing the resistance in the case of thin film resistive elements (up to about 10 OKΩ). There is a problem in that a thick film resistor must be used, which is inferior to a thin film resistor and has a low element density, making it difficult to miniaturize.

本発明の課題は、高精度でかつ温度トラッキング特性に
優れた抵抗値比が得られ、さらに製造工程が容易で量産
化による低コスト化が可能な抵抗ネットワークを提供す
ることを目的とする。
An object of the present invention is to provide a resistor network that is highly accurate and provides a resistance value ratio with excellent temperature tracking characteristics, and that also has an easy manufacturing process and can be mass-produced to reduce costs.

〔課題を解決するための手段〕[Means to solve the problem]

前記課題を解決するため、本発明の抵抗ネットワークは
、複数個の抵抗器を同一基板上に形成して成る抵抗ネッ
トワークにおいて、 第1の導電型の半導体基板と、 該半導体基板内に等間隔で並設された同一工程で形成さ
れる前記第1の導電型とは逆の第2の導電型を有する複
数の同一形状の単位拡散抵抗と、該複数の単位拡散抵抗
の一部を第1の導電性部。
In order to solve the above-mentioned problems, the resistance network of the present invention includes a semiconductor substrate of a first conductivity type, and a resistor network formed of a plurality of resistors formed on the same substrate, and a resistor network formed of a plurality of resistors formed on the same substrate. A plurality of unit diffused resistors having the same shape and having a second conductivity type opposite to the first conductivity type are formed in parallel in the same process, and a part of the plurality of unit diffused resistors is conductive part.

材を介して直列又は並列に接続して成る抵抗器を複数個
有することを特徴とする。
It is characterized by having a plurality of resistors connected in series or in parallel through materials.

前記複数の各抵抗器は、例えば前記複数の単位拡散抵抗
をそれぞれ任意の列おきに前記導電性部材を介して直列
接続又は並列接続して成る。
Each of the plurality of resistors is formed by, for example, connecting the plurality of unit diffused resistors in series or in parallel at arbitrary intervals through the conductive member.

〔作   用〕[For production]

本発明の手段の作用は次の通りである。 The operation of the means of the invention is as follows.

第1の導電型の半導体基板内に、熱拡散又はイオン注入
等により上記第1の導電型とは逆の第2の導電型の複数
の同一形状の単位拡散抵抗を等間隔で並設して形成する
。そして、絶縁膜の形成やコンタクトホール形成等の周
知の半導体プロセス工程を行った後、スパッタ法、真空
蒸着法等により例えばAl、Aj!−3i等から成る導
電性部材を形成し、その導電性部材を介し前記複数の単
位拡散抵抗を直列又は並列に接続して成る抵抗器を同時
に形成する。
In a semiconductor substrate of a first conductivity type, a plurality of unit diffused resistors of the same shape and of a second conductivity type opposite to the first conductivity type are arranged in parallel at equal intervals by thermal diffusion or ion implantation. Form. After performing well-known semiconductor process steps such as forming an insulating film and forming contact holes, for example, Al, Aj! A conductive member made of -3i or the like is formed, and a resistor is simultaneously formed by connecting the plurality of unit diffused resistors in series or in parallel via the conductive member.

このように、抵抗器を構成する複数の単位拡散抵抗は同
一工程で形成され、さらに上記各抵抗器を構成する各単
位拡散抵抗間を電気的に接続する導電性部材も全ての抵
抗器において同一工程で形成される。
In this way, the plurality of unit diffused resistors constituting the resistor are formed in the same process, and the conductive members that electrically connect the unit diffused resistors constituting each resistor are also the same in all resistors. Formed during the process.

したがって、複数の抵抗器の温度係数はほぼ均一となり
、各抵抗器間の抵抗値比の温度トラッキング特性は非常
に良好なものとなる。
Therefore, the temperature coefficients of the plurality of resistors become almost uniform, and the temperature tracking characteristic of the resistance value ratio between the resistors becomes very good.

また、単位拡散抵抗は半導体プロセス工程により形成さ
れるため、各単位拡散抵抗の抵抗値を非常に高精度に形
成でき、各単位拡散抵抗の抵抗値偏差を非常に小さなも
のとすることができる。したがって、複数の抵抗器間の
抵抗値比が非常に高精度でかつ温度トラッキング特性が
非常に優れた抵抗ネットワークを同一ウェハ上に多数作
成することが可能となる。
Further, since the unit diffused resistors are formed by a semiconductor process, the resistance value of each unit diffused resistor can be formed with very high precision, and the resistance value deviation of each unit diffused resistor can be made very small. Therefore, it is possible to create a large number of resistance networks on the same wafer, in which the resistance value ratio between the plurality of resistors is very accurate and the temperature tracking characteristics are very excellent.

〔実  施  例〕〔Example〕

以下、図面を参照しながら本発明の実施例について説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

第1図は、本発明に係る一実施例を示す概略平面図であ
る。
FIG. 1 is a schematic plan view showing one embodiment of the present invention.

同図において、単位拡散抵抗2.2°は、所定の抵抗値
を有するp型の拡散抵抗であり、熱拡散又はイオン注入
等によりn型の半導体基板内に不純物を添加・拡散する
ことにより形成される。上記単位拡散抵抗2.2゛は、
所定長dの等間隔で交互に複数個並設して配列されてい
る。
In the figure, the unit diffused resistor 2.2° is a p-type diffused resistor having a predetermined resistance value, and is formed by adding and diffusing impurities into an n-type semiconductor substrate by thermal diffusion or ion implantation. be done. The above unit diffused resistance 2.2゛ is
A plurality of them are alternately arranged in parallel at equal intervals of a predetermined length d.

また、上記単位拡散抵抗2は1個おきに配線用コンタク
トホール3を介して、A1、Aj!−3i等から成る導
電性部材4により接続されている。
Further, every other unit diffused resistor 2 is connected to A1, Aj! through a contact hole 3 for wiring. They are connected by a conductive member 4 made of -3i or the like.

すなわち、任意の個数nの単位拡散抵抗2がコンタクト
ホール3及び導電性部材4を介して直列接続されている
That is, an arbitrary number n of unit diffused resistors 2 are connected in series via contact holes 3 and conductive members 4.

一方、上記単位拡散抵抗2.2間に配設されている任意
の個数nの単位拡散抵抗2′はコシタクトホール3° 
 3′及び各単位拡散抵抗2“の両端に設けられた/l
、A1−3i等から成る導電性部材4゛を介して並列接
続されている。
On the other hand, an arbitrary number n of unit diffused resistors 2' arranged between the unit diffused resistors 2 and 2 have a koshi tact hole of 3°.
3' and /l provided at both ends of each unit diffused resistor 2''
, A1-3i, etc. are connected in parallel via a conductive member 4'.

さらに、上記直列接続されている単位拡散抵抗2.2、
・・・の中で両端に配設された単位拡散抵抗2  (2
−1) 、2 (2−n)は、電極用コンタクトホール
5.5を介してA1、A1−3i等から成る外部接続用
の電極6.6に接続されている。
Furthermore, the unit diffused resistor 2.2 connected in series,
Unit diffused resistors 2 (2
-1) and 2 (2-n) are connected to external connection electrodes 6.6 made of A1, A1-3i, etc. through electrode contact holes 5.5.

また、上記並列接続されている単位拡散抵抗2”2゛ 
 ・・・の図中向かって左側端部の単位拡散抵抗2’ 
 (2−n)の両端は、電極用コンタクトホール5゛ 
5゛を介して、外部接続用の電極6′6′に接続されて
いる。
In addition, the above unit diffused resistors 2"2" connected in parallel
The unit diffused resistor 2' at the left end in the figure...
Both ends of (2-n) have electrode contact holes 5゜.
5' to an electrode 6'6' for external connection.

上記構成において、例えば単位拡散抵抗2及び単位拡散
抵抗2′の抵抗値をX〔Ω〕とし、単位拡散抵抗2.2
、・・・及び単位拡散抵抗2゛2′  ・・・をどちら
でもn個配設した場合、直列接続されたn個の単位拡散
抵抗2  (2−1)、2(2−2)、・・・2 (2
−n)(便宜上、直列抵抗器R,と表現する)の総抵抗
値はnx(Ω〕となり、また並列接続されたn個の単位
拡散抵抗2° (2°−1)、2’  (2′−2)・
・・2゛(2’−n)(便宜上、並列抵抗器R2と表現
する)の総抵抗値はX/n(Ω〕となる。
In the above configuration, for example, let the resistance value of the unit diffused resistor 2 and the unit diffused resistor 2' be X [Ω], and the unit diffused resistor 2.2
, ... and unit diffused resistors 2'2'... are arranged, n unit diffused resistors 2 (2-1), 2 (2-2), ... connected in series ...2 (2
-n) (expressed as series resistor R for convenience) is nx (Ω), and n unit diffused resistors 2° (2°-1), 2' (2 '-2)・
The total resistance value of 2'(2'-n) (expressed as parallel resistor R2 for convenience) is X/n (Ω).

したがって、直列抵抗器R1と並列抵抗器R2の抵抗値
比R+/Rzは、 となる。
Therefore, the resistance value ratio R+/Rz of the series resistor R1 and the parallel resistor R2 is as follows.

このことにより、直列接続する単位拡散抵抗2及び並列
接続する単位拡散抵抗2”の数nを、任意の個数に設定
することにより、任意の抵抗値比n2を有するペア抵抗
器を得ることが可能となる。
As a result, by setting the number n of unit diffused resistors 2 connected in series and unit diffused resistors 2 connected in parallel to an arbitrary number, it is possible to obtain a pair of resistors having an arbitrary resistance value ratio n2. becomes.

しかも、単位抵抗器となる単位拡散抵抗2.2゛を半導
体基板上に同一工程で形成するため、各単位拡散の抵抗
値もほぼ均一なものとなり、また温度係数もほぼ均一な
ものとなる。
Moreover, since the unit diffused resistors 2.2'' serving as unit resistors are formed in the same process on the semiconductor substrate, the resistance value of each unit diffusion becomes substantially uniform, and the temperature coefficient also becomes substantially uniform.

したがって、高精度の抵抗値比を有するペア抵抗チップ
を得ることが可能となる。
Therefore, it is possible to obtain a pair of resistor chips having a highly accurate resistance value ratio.

さらに、本実施例においては、直列接続される単位拡散
抵抗2と並列接続される単位拡散抵抗2゛とを交互に配
設しているため、リソグラフィ工程等において各単位拡
散抵抗の配設位置が異なることに起因して発生する各単
位拡散抵抗2.2′の線幅のバラツキによる抵抗値及び
温度係数のバラツキが直列抵抗器R1と並列抵抗器R2
において相殺されるようになっており、非常に高精度の
抵抗値比と非常に優れた温度トラッキング特性を有する
ペア抵抗チップが得られる。
Furthermore, in this embodiment, since the unit diffused resistors 2 connected in series and the unit diffused resistors 2'' connected in parallel are arranged alternately, the arrangement position of each unit diffused resistor is changed in the lithography process etc. Variations in resistance value and temperature coefficient due to variations in line width of each unit diffused resistor 2.2' caused by differences between series resistor R1 and parallel resistor R2
This results in a paired resistor chip with a very precise resistance value ratio and very good temperature tracking characteristics.

また、単位拡散抵抗2.2゛は半導体プロセスにより形
成されるため、単位拡散抵抗2.2′の微細化も通常の
半導体プロセスにより容易に可能であり、非常に小さな
ペア抵抗チップを作成することができる。また、同一ウ
ェハ上に多数のペア抵抗チップを作製できるので、量産
効果による低価格化が可能となる。
Furthermore, since the unit diffused resistor 2.2' is formed by a semiconductor process, it is easy to miniaturize the unit diffused resistor 2.2' by a normal semiconductor process, and it is possible to create a very small paired resistor chip. I can do it. Furthermore, since a large number of paired resistor chips can be manufactured on the same wafer, it is possible to reduce the cost by mass production.

尚、上記実施例では半導体基板としてn型Si基板を用
い、そのn型Si基板内にp型の単位拡散抵抗を形成す
るようにしているが、本発明は上記実施例に限定される
ものではなく、n型Si基板にn型の拡nt抵抗を形成
するようにして抵抗ネットワークを形成するようにして
もよく、また半導体基板も、Si基板に限定されること
なく、ゲルマニウム(Ge)等の他の半導体基板を用い
るようにすることも可能である。また、第1の抵抗器及
び第2の抵抗器はどちらも単位拡散抵抗を直列接続又は
並列接続することにより形成するようにしてもよい。
In the above embodiment, an n-type Si substrate is used as the semiconductor substrate, and a p-type unit diffused resistor is formed in the n-type Si substrate, but the present invention is not limited to the above embodiment. Instead, a resistor network may be formed by forming an n-type extended NT resistor on an n-type Si substrate, and the semiconductor substrate is not limited to a Si substrate, but may be made of germanium (Ge) or the like. It is also possible to use other semiconductor substrates. Further, both the first resistor and the second resistor may be formed by connecting unit diffused resistors in series or in parallel.

されに、本発明は上記実施例のようなペア抵抗器に限定
されるものではなく、複数の単位拡散抵抗を任意の列お
きに直列又は並列に接続して成る3個以上の複数の抵抗
器を有するブリッジ回路やフィルタ等に利用可能な抵抗
ネットワークにも容易に適用できるものである。
Furthermore, the present invention is not limited to a pair of resistors as in the above embodiments, but also includes a plurality of three or more resistors formed by connecting a plurality of unit diffused resistors in series or parallel in every other column. It can also be easily applied to resistor networks that can be used in bridge circuits, filters, etc.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、半導体基板内に等間隔で並設された同
一工程で形成される複数の同一形状の単位拡散抵抗と、
さらにそれらの単位拡散抵抗を同一工程で形成される複
数の導電性部材を介して直列又は並列に接続して成る複
数個の抵抗器を有するので、各抵抗器を同一工程で形成
することが可能となり、高精度でかつ温度トラッキング
特性の非常に優れた抵抗値比を有するペア抵抗並びに抵
抗値の温度依存性が非常に均一な複数の抵抗器を有する
抵抗ネットワークを得ることが可能となる。
According to the present invention, a plurality of unit diffused resistors of the same shape formed in the same process and arranged in parallel at equal intervals in a semiconductor substrate,
Furthermore, since it has a plurality of resistors formed by connecting these unit diffused resistors in series or parallel via a plurality of conductive members formed in the same process, each resistor can be formed in the same process. As a result, it is possible to obtain a resistor network having a pair of resistors with high accuracy and an extremely excellent temperature tracking characteristic and a resistance value ratio, and a plurality of resistors with extremely uniform temperature dependence of the resistance value.

また、半導体プロセスにより、上記抵抗ネットワークチ
ップを同一ウェハ上に多数作製できるので、非常に高い
スループットで大量の抵抗ネットワークチップを生産す
ることができ、量産効果により製造コストを著しく低減
することが可能となる。
In addition, since a large number of the above-mentioned resistor network chips can be manufactured on the same wafer using a semiconductor process, it is possible to produce a large number of resistor network chips with extremely high throughput, and the mass production effect can significantly reduce manufacturing costs. Become.

また、請求項2記載のように複数の単位拡散抵抗を任意
の列おきに導電性部材を介して直列又は並列に接続して
複数の抵抗器を形成するようにすれば、各抵抗器の抵抗
値がさらに高精度で、しがち各抵抗器の抵抗値の温度依
存性が非常に均一で温度トラッキング特性がより優れた
抵抗ネットワークを得ることが可能となる。
Furthermore, if a plurality of unit diffused resistors are connected in series or parallel every other column via a conductive member to form a plurality of resistors as described in claim 2, the resistance of each resistor is It is possible to obtain a resistor network whose values are more accurate, the temperature dependence of the resistance value of each resistor is very uniform, and whose temperature tracking properties are better.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係る抵抗ネットワークの一実施例を説
明する概略平面図である。 2.2° ・・・単位拡散抵抗、 3.3゛ ・・・配線用コンタクトホール4.4” ・
・・導電性部材、 5.5゛ ・・・電極用コンタクトホール、6・・・電
極。 特許出願人  株式会社豊田自動織機製作所I 図
FIG. 1 is a schematic plan view illustrating an embodiment of a resistor network according to the present invention. 2.2°...Unit diffused resistance, 3.3゛...Wiring contact hole 4.4" ・
...Conductive member, 5.5゛...Contact hole for electrode, 6...Electrode. Patent applicant: Toyota Industries Corporation I

Claims (1)

【特許請求の範囲】 1)複数個の抵抗器を同一基板上に形成して成る抵抗ネ
ットワークにおいて、 第1の導電型の半導体基板と、 該半導体基板内に等間隔で並設された同一工程で形成さ
れる前記第1の導電型とは逆の第2の導電型を有する複
数の同一形状の単位拡散抵抗と、該複数の単位拡散抵抗
の一部を導電性部材を介して直列又は並列に接続して成
る抵抗器を複数個有することを特徴とする抵抗ネットワ
ーク。 2)前記複数の各抵抗器は、前記複数の単位拡散抵抗を
それぞれ任意の列おきに前記導電性部材を介して直列接
続又は並列接続して成ることを特徴とする請求項1記載
の抵抗ネットワーク。
[Claims] 1) In a resistance network formed by forming a plurality of resistors on the same substrate, a semiconductor substrate of a first conductivity type, and the same process line arranged in parallel at equal intervals within the semiconductor substrate. A plurality of unit diffused resistors having the same shape and having a second conductivity type opposite to the first conductivity type formed by the above, and a part of the plurality of unit diffused resistors are connected in series or in parallel via a conductive member. A resistance network characterized by having a plurality of resistors connected to. 2) The resistor network according to claim 1, wherein each of the plurality of resistors is formed by connecting the plurality of unit diffused resistors in series or parallel via the conductive member every other column. .
JP9851789A 1989-04-18 1989-04-18 Resistance network Pending JPH02277263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9851789A JPH02277263A (en) 1989-04-18 1989-04-18 Resistance network

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9851789A JPH02277263A (en) 1989-04-18 1989-04-18 Resistance network

Publications (1)

Publication Number Publication Date
JPH02277263A true JPH02277263A (en) 1990-11-13

Family

ID=14221845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9851789A Pending JPH02277263A (en) 1989-04-18 1989-04-18 Resistance network

Country Status (1)

Country Link
JP (1) JPH02277263A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07151818A (en) * 1993-11-29 1995-06-16 Nec Corp Semiconductor integrated circuit device
JP2006210664A (en) * 2005-01-28 2006-08-10 Toppan Printing Co Ltd Printed wiring board and its manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07151818A (en) * 1993-11-29 1995-06-16 Nec Corp Semiconductor integrated circuit device
JP2006210664A (en) * 2005-01-28 2006-08-10 Toppan Printing Co Ltd Printed wiring board and its manufacturing method
JP4720194B2 (en) * 2005-01-28 2011-07-13 凸版印刷株式会社 Method for manufacturing printed wiring board

Similar Documents

Publication Publication Date Title
US5206623A (en) Electrical resistors and methods of making same
JPH01199404A (en) Trimming resistance circuit network
JP3058097B2 (en) Thermistor chip and manufacturing method thereof
US3680013A (en) Film attenuator
JPH0320041B2 (en)
JPH02277263A (en) Resistance network
JPH09129825A (en) Method of forming thick film resistance
JP4073673B2 (en) Resistor manufacturing method
JPH09205004A (en) Chip resistor and its manufacturing method
JP2847102B2 (en) Chip type thermistor and method of manufacturing the same
JP3525673B2 (en) Resistor and manufacturing method thereof
JP2860799B2 (en) Manufacturing method of temperature sensitive resistor
EP0398364B1 (en) Thick-film element having flattened resistor layer
JPH03257986A (en) Electronic circuit device
JPS61229302A (en) Parallel type resistor unit
JPH0132363Y2 (en)
JPH01155601A (en) Manufacture of thin film resistance element
JP3288241B2 (en) Resistive material and resistive material thin film
JP2567550Y2 (en) Temperature measuring matching resistor
JPS63283102A (en) Thermistor
JPS63169058A (en) Thin film integrated circuit
JPS6149455A (en) Integrated circuit device
JPS62169301A (en) Temperature coefficient regulation of thick film resistance element
JPS5931202B2 (en) AC/DC conversion element for true RMS value measurement
JPH11162705A (en) Low-resistance chip resistor