JPH02272768A - Solid state image sensor - Google Patents
Solid state image sensorInfo
- Publication number
- JPH02272768A JPH02272768A JP1093163A JP9316389A JPH02272768A JP H02272768 A JPH02272768 A JP H02272768A JP 1093163 A JP1093163 A JP 1093163A JP 9316389 A JP9316389 A JP 9316389A JP H02272768 A JPH02272768 A JP H02272768A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layers
- wiring
- layer
- light shielding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000007787 solid Substances 0.000 title 1
- 229910018125 Al-Si Inorganic materials 0.000 claims abstract 7
- 229910018520 Al—Si Inorganic materials 0.000 claims abstract 7
- 238000003384 imaging method Methods 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims 1
- 230000035945 sensitivity Effects 0.000 abstract description 7
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は各画素の感度のバラツキを低減した固体撮像装
置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a solid-state imaging device in which variations in sensitivity of each pixel are reduced.
(従来の技術)
近年の固体撮像装置は、撮像性能が急速に進歩して来て
おり、ますます高性能化の要望が大きくなっている。(Prior Art) In recent years, the imaging performance of solid-state imaging devices has been rapidly improving, and there is a growing demand for higher performance.
第2図(a)は、従来の固体撮像素子の単位セルの模式
断面側図を示す。これは、光検出部の受光域(N)1、
伝達ゲート部のエンハンスメント領域(P”)2.埋込
チャネル(N”)3、伝達ゲート4を含み紙面に対し、
垂直方向へ電荷を運ぶ垂直転送レジスタ部からなる組が
、それらの間にチャネルストッパ5からなる絶縁分離領
域(P+)を介して構成される。そして、N型半導体基
板12上に選択的に形成されたPウェル6及び、上記伝
達ゲート4上に絶縁膜7を介して受光域1の面積を決定
する遮光膜8を形成している。FIG. 2(a) shows a schematic cross-sectional side view of a unit cell of a conventional solid-state image sensor. This is the light receiving area (N)1 of the photodetector,
Enhancement region (P”) of the transmission gate portion 2. Including the buried channel (N”) 3 and the transmission gate 4.
A set of vertical transfer register sections that carry charges in the vertical direction is formed with an insulating isolation region (P+) consisting of a channel stopper 5 interposed therebetween. A P-well 6 selectively formed on the N-type semiconductor substrate 12 and a light-shielding film 8 that determines the area of the light-receiving region 1 are formed on the transmission gate 4 via an insulating film 7.
また、第2図(b)は、同図(a)の周辺部MOSトラ
ンジスタの模式断面側図を示す。9はゲート電極、10
は配線膜、11はN型拡散層で、その他は(a)図と同
じである。Further, FIG. 2(b) shows a schematic cross-sectional side view of the peripheral MOS transistor shown in FIG. 2(a). 9 is a gate electrode, 10
11 is a wiring film, 11 is an N-type diffusion layer, and the other parts are the same as in FIG.
第2図(a)の遮光膜8と第2図(b)の配線膜10と
は製作の際、同時に形成し、遮光膜8と配線膜10はA
g材料を用いるが、第2図(b)の場合、純Adを用い
ると薄いN型拡散層11へAQの突き抜けが生じるため
、従来はAI+にSiを含有(1,0%)させたAd−
3i(1,0%)を用い、AlがN型拡散層へ突き抜け
るのを回避していた。The light shielding film 8 in FIG. 2(a) and the wiring film 10 in FIG. 2(b) are formed at the same time during manufacturing, and the light shielding film 8 and the wiring film 10 are
However, in the case of FIG. 2(b), if pure Ad is used, AQ will penetrate into the thin N-type diffusion layer 11, so conventionally, Ad containing Si (1.0%) in AI+ has been used. −
3i (1.0%) was used to prevent Al from penetrating into the N-type diffusion layer.
(発明が解決しようとする課題)
しかし、その反面、AllにSiを含有したため、製作
時、遮光膜8及び配線膜10にヒロック8h。(Problems to be Solved by the Invention) However, on the other hand, since Si is contained in the Al, hillocks 8h occur in the light shielding film 8 and the wiring film 10 during manufacturing.
10h(llill・ock )が発生しやすくなった
。これは、A+2−Si膜を絶縁膜7やN型拡散層11
上に蒸着し熱処理を行う過程において、再結晶により発
生するものと考えられる。10h (llill・ock) has become more likely to occur. This is done by using the A+2-Si film as the insulating film 7 and the N-type diffusion layer 11.
It is thought that this occurs due to recrystallization during the process of vapor deposition and heat treatment.
第2図(a)のヒロック8hは、図示のとおり受光域1
に突出しその一部分を遮光するため撮像画面では各画素
の感度のバラツキに影響を与える。また、第2図(b)
のヒロックtohは1図示のとおり配線膜10に薄い所
と厚い所が生ずるため抵抗値の変化(高くなる)が生じ
バラツクこととなる。Hillock 8h in Figure 2(a) is light receiving area 1 as shown in the figure.
Because it protrudes from the outside and partially blocks light, it affects the variation in sensitivity of each pixel on the imaging screen. Also, Figure 2(b)
As shown in FIG. 1, the hillock toh causes the wiring film 10 to have thinner areas and thicker areas, resulting in a change in resistance value (increase) and variation.
本発明は、このような遮光膜及び配線膜でのヒロック発
生を抑え、各画素の感度のバラツキがなく、良好な配線
コンタクトをうろことを目的とする。It is an object of the present invention to suppress the occurrence of hillocks in the light shielding film and wiring film, to eliminate variations in the sensitivity of each pixel, and to ensure good wiring contact.
(課題を解決するための手段)
本発明は上記目的を達成するため、遮光膜及び配線膜の
構造を二層構造とし、その膜材料はAl1−3i膜でな
り、上層及び下層のSi含有率を変えるようにしたこと
を特徴とする。(Means for Solving the Problems) In order to achieve the above object, the present invention has a two-layer structure for the light-shielding film and the wiring film, and the film material is an Al1-3i film, and the Si content of the upper and lower layers is It is characterized by changing the
(作 用)
本発明は、上層のAlt−Si膜のSiは0〜0.5%
。(Function) In the present invention, the upper Alt-Si film has a Si content of 0 to 0.5%.
.
下層(7)Al−8L膜(7) S iは0.8〜1.
6%、の範囲に夫々含有させることにより、上層におい
てSiを従来より少なくしヒロック発生を抑止し、下層
においてSiを従来より僅かに増減させてコンタクトの
向上をはかったものである。Lower layer (7) Al-8L film (7) S i is 0.8 to 1.
By containing each in the range of 6%, the upper layer contains less Si than before to suppress the occurrence of hillocks, and the lower layer contains slightly more or less Si than before to improve contact.
(実施例)
第1図は本発明の一実施例の模式断面図を示し、(a)
は単位セル、(b)は周辺部のMoSトランジスタであ
る。両図(a)、 (b)において、遮光膜8′及び配
線膜10’は夫々、二層のA I −S L膜8a、
8b。(Example) FIG. 1 shows a schematic sectional view of an example of the present invention, (a)
is a unit cell, and (b) is a MoS transistor in the peripheral area. In both figures (a) and (b), the light shielding film 8' and the wiring film 10' are a two-layer AI-SL film 8a,
8b.
及び10a、 10bで構成し、上層8a、 10aの
Si含有率をO〜0.5%、下層(7) 8b、 10
b(7) Si含有率を0.8〜1.6%、の各範囲で
製作されている。and 10a, 10b, the Si content of the upper layer 8a, 10a is O~0.5%, and the lower layer (7) 8b, 10
b(7) They are manufactured with Si content ranging from 0.8% to 1.6%.
このように構成することにより、上層8a、 10aは
従来に比べSi含有率が1.0%から最大でもその1/
2の0.5%に低減された結果、A+2−8L膜を絶縁
膜7(a図)やN型拡散層11(b図)に蒸着し、加熱
処理する過程でヒロック8h、 10hの発生を抑え、
(a)図の場合、受光域1の各画素の感度のバラツキが
少なくなる。また、下層8b、10bは従来に比べSi
含有率が1.0%を僅かに減増0.2〜0.6%してい
るのみであるから(b)図の場合、薄いN型拡散層11
を突き抜けることなく、良好なコンタクトが得られる。With this configuration, the upper layers 8a and 10a have a Si content of 1.0% to at most 1/1% compared to the conventional one.
As a result, the occurrence of hillocks 8h and 10h occurred during the process of depositing the A+2-8L film on the insulating film 7 (figure a) and the N-type diffusion layer 11 (figure b) and heat-treating it. suppress,
In the case of (a), the variation in sensitivity of each pixel in the light-receiving area 1 is reduced. In addition, the lower layers 8b and 10b are made of Si compared to the conventional one.
Since the content rate is only slightly decreased or increased by 0.2 to 0.6% from 1.0%, in the case of figure (b), the thin N-type diffusion layer 11
Good contact can be obtained without penetrating the surface.
なお、標準的なSi含有率は上層8a、 10aに0.
5%、下層sb、 tabに1.0%とすることが、材
料の混成、及びヒロックを抑え、画素の感度のバラツキ
をなくしかつ良好な配線コンタクトをつる上で最適であ
った。Note that the standard Si content is 0.
5% and 1.0% for the lower layer sb and tab was optimal for suppressing material mixture and hillocks, eliminating variations in pixel sensitivity, and establishing good wiring contacts.
(発明の効果)
以」二説明したように本発明は、製作時に同時に形成さ
れる+4位セルの遮光膜及び周辺部MOSトランジスタ
の配線膜を従来の一層から二層構造とし、そのAf!−
3j膜のSi含有率を上層を少なく、下層はそれより多
くし、上層でのヒロックの発生を抑止し、下層でのコン
タクトを良好ならしめた。(Effects of the Invention) As explained above, in the present invention, the light shielding film of the +4 cell and the wiring film of the peripheral MOS transistor, which are formed simultaneously during manufacturing, are changed from the conventional one-layer structure to a two-layer structure, and the Af! −
The Si content of the 3j film was made lower in the upper layer and higher in the lower layer to suppress the occurrence of hillocks in the upper layer and to improve contact in the lower layer.
この結果、jll−位セルにおける各画素の感度のバラ
ツキがなくなり品質の向上が得られる。As a result, variations in the sensitivity of each pixel in the jll-cell are eliminated, resulting in improved quality.
第1図は本発明の一実施例の模式断面図、第2図は従来
の固体撮像素子の模式断面側図を示す。
1 ・・・受光域、 2・・・エンハンスメント、3・
・・埋込チャネル、4 ・・・伝達ゲート、5 ・・・
チャネルストッパ、 6 ・・・ Pウェル、 7・・
・絶縁層、 8,8′ ・・・遮光膜、8a、 10a
−上層、 8b、 10b ・・・下層。
9 ・・・ゲート電極、10.10′ ・・・配線膜、
11・・・N型拡散層、12・・・N型半導体基板。
特許出闇人 松下電子工業株式会社
第
図
第
図
N型平早捧蟇棟FIG. 1 is a schematic sectional view of an embodiment of the present invention, and FIG. 2 is a schematic sectional side view of a conventional solid-state image sensor. 1... Light receiving area, 2... Enhancement, 3...
...Embedded channel, 4...Transmission gate, 5...
Channel stopper, 6...P well, 7...
・Insulating layer, 8, 8'... Light shielding film, 8a, 10a
- Upper layer, 8b, 10b...lower layer. 9...Gate electrode, 10.10'...Wiring film,
11...N-type diffusion layer, 12...N-type semiconductor substrate. Patent developer Matsushita Electronics Co., Ltd.
Claims (1)
からなる単位セルを複数個有する固体撮像装置において
、遮光用のAl−Si膜と配線用のAl−Si膜を二層
の膜で形成したことを特徴とする固体撮像装置。In a solid-state imaging device having a plurality of unit cells each consisting of a photoelectric conversion element section, a transmission gate section, and a vertical transfer register section, an Al-Si film for light shielding and an Al-Si film for wiring are formed as two-layered films. A solid-state imaging device featuring:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1093163A JPH02272768A (en) | 1989-04-14 | 1989-04-14 | Solid state image sensor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1093163A JPH02272768A (en) | 1989-04-14 | 1989-04-14 | Solid state image sensor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02272768A true JPH02272768A (en) | 1990-11-07 |
Family
ID=14074900
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1093163A Pending JPH02272768A (en) | 1989-04-14 | 1989-04-14 | Solid state image sensor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02272768A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04196167A (en) * | 1990-11-26 | 1992-07-15 | Nec Corp | Solid state image sensing element |
JPH04225565A (en) * | 1990-12-27 | 1992-08-14 | Matsushita Electron Corp | Solid state image sensor |
-
1989
- 1989-04-14 JP JP1093163A patent/JPH02272768A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04196167A (en) * | 1990-11-26 | 1992-07-15 | Nec Corp | Solid state image sensing element |
JPH04225565A (en) * | 1990-12-27 | 1992-08-14 | Matsushita Electron Corp | Solid state image sensor |
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