JPH02272750A - Formation of multilayer wiring and continuous treatment device - Google Patents

Formation of multilayer wiring and continuous treatment device

Info

Publication number
JPH02272750A
JPH02272750A JP9300189A JP9300189A JPH02272750A JP H02272750 A JPH02272750 A JP H02272750A JP 9300189 A JP9300189 A JP 9300189A JP 9300189 A JP9300189 A JP 9300189A JP H02272750 A JPH02272750 A JP H02272750A
Authority
JP
Japan
Prior art keywords
substrate
conductive material
multilayer wiring
contact hole
ultraviolet rays
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9300189A
Other languages
Japanese (ja)
Other versions
JP2832991B2 (en
Inventor
Yuji Komatsu
裕司 小松
Yasushi Morita
靖 森田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP9300189A priority Critical patent/JP2832991B2/en
Publication of JPH02272750A publication Critical patent/JPH02272750A/en
Application granted granted Critical
Publication of JP2832991B2 publication Critical patent/JP2832991B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To reduce a contact resistance value and to enable formation of a multilayer wiring having good ohmic characteristics by irradiating ultraviolet rays to a bottom of a contact hole which is made in an interlayer insulating film on a semiconductor substrate and by filling it up with a conductive material continuously. CONSTITUTION:When a contact hole 23 is made in an interlayer insulating film 21 on a semiconductor substrate 2, a natural oxidation film 22 is formed slightly on a surface of the substrate 2 of a bottom thereof. The substrate 2 is installed in an ultraviolet ray irradiating device, and ultraviolet rays 24 are irradiated to a bottom of the contact hole 23 in reducing atmosphere. The film 22 is reduced and removed by irradiation of ultraviolet rays 24. The substrate 2 is transferred to a conductive material deposit device without being exposed to atmosphere and a conductive material 25 is filled continuously by selective vapor deposit method to form a multilayer wiring. Accordingly, it is possible to reduce a contact resistance value and to form a multilayer wiring of good ohmic characteristics, thereby improving and stabilizing device characteristics of a semiconductor device.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造工程における多層配線の形
成方法および連続処理装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for forming multilayer wiring in the manufacturing process of semiconductor devices and a continuous processing apparatus.

〔発明のイ既要] 本発明は、半導体装置の製造工程における多層配線の形
成方法および連続処理装置に関し、更に詳しくは、還元
性雰囲気中において接続孔底部に紫外線照射を施し、次
いで連続的にこの接続内部に導電性材料を埋め込む多層
配線形成方法、およびこの多層配線形成方法を可能とす
るための連続処理装置に関する。
[Summary of the Invention] The present invention relates to a method and continuous processing apparatus for forming multilayer wiring in the manufacturing process of semiconductor devices, and more specifically, the present invention relates to a method for forming multilayer wiring in the manufacturing process of a semiconductor device and a continuous processing apparatus. The present invention relates to a method of forming a multilayer wiring in which a conductive material is embedded inside the connection, and a continuous processing apparatus for making this method of forming a multilayer wiring possible.

〔従来の技術〕[Conventional technology]

LSI等半導体装置の高集積度化、高速度化に伴い、多
層配線の形成技術の重要性が高まっている。とりわけ接
続孔は、そのアスペクト比すなわち深さと直径の比が例
えば1以上と大きくなってきており、この接続孔への導
電性材料の信頼性ある埋め込み技術の重要性が増してい
る。
2. Description of the Related Art As semiconductor devices such as LSIs become more highly integrated and operate at higher speeds, the importance of multilayer wiring formation technology is increasing. In particular, the aspect ratio, that is, the ratio of depth to diameter, of connection holes is increasing, for example, to 1 or more, and the importance of reliable embedding techniques for conductive materials into these connection holes is increasing.

従来、半導体等の基体上の層間絶縁膜に開口した接続孔
内部に導電性材料を埋め込む方法としては、選択CVD
、ブランケットCVDさらにスパッタリングによる方法
等が用いられている。また埋め込みに用いる導電性材料
としては、アルミニラム(AI)やその合金、タングス
テン(W)等の高融点金属やそのシリサイドさらにはポ
リシリコン(p−3t)等が用いられている。
Conventionally, selective CVD has been used as a method for embedding a conductive material inside a contact hole opened in an interlayer insulating film on a substrate such as a semiconductor.
, blanket CVD, sputtering, and the like are used. Further, as the conductive material used for embedding, aluminum (AI), its alloy, high melting point metal such as tungsten (W), its silicide, polysilicon (p-3t), etc. are used.

これらの導電性材料をSi等の半導体基体上の層間絶縁
膜に開口した接続孔内部に埋め込むに際して、接続孔底
部に露出した基体表面の効果的な清浄化が極めて重要で
ある。この理由は主にSiが非常に酸化され易い物質で
あるため、基体表面の自然酸化膜の除去が難しく、−旦
除去しても純水等で洗浄したり、あるいは次の工程に入
る迄の間に基体を大気に露出すると直ぐに新しい自然酸
化膜が形成されることによる。自然酸化膜の除去が不完
全のまま接続内部に導電性材料を埋め込むと、コンタク
ト抵抗値が大きくなったり、オーミンクなコンタクトが
得られず、デバイス特性に悪影響をおよぼすことがある
。さらに選択CVDによる埋め込みにおいては、自己整
合的な選択成長が不完全であったり、場合によっては全
く選択成長が行われない場合すらある。
When embedding these conductive materials into connection holes opened in an interlayer insulating film on a semiconductor substrate such as Si, it is extremely important to effectively clean the surface of the substrate exposed at the bottom of the connection hole. The main reason for this is that Si is a substance that is very easily oxidized, so it is difficult to remove the natural oxide film on the surface of the substrate. This is because a new natural oxide film is formed as soon as the substrate is exposed to the atmosphere during this period. If a conductive material is buried inside the connection while the native oxide film is incompletely removed, the contact resistance value may increase or an ohmink contact may not be obtained, which may adversely affect device characteristics. Furthermore, in embedding by selective CVD, self-aligned selective growth may be incomplete, or in some cases, selective growth may not occur at all.

そこで従来より、導電性材料の堆積室内部で基体に対し
てアルゴン(Ar)等によるプラズマクリーニングを行
ったり、高温高真空ベーキングを施したりして自然酸化
膜を除去し、この後に連続的に導電性材料を埋め込む方
法が行われてきた。また選択CVDによる方法において
は、反応性ガス雰囲気中で200〜11000nの波長
の光を基体に照射し、密着性の良い中間生成物を形成し
て上記問題点を解決しようという従来技術が知られてい
る(特開昭筒61−274345号公報参照)。
Conventionally, the natural oxide film is removed by performing plasma cleaning with argon (Ar) or the like on the substrate inside a conductive material deposition chamber, or by performing high-temperature, high-vacuum baking, and then continuously conductive Methods of embedding synthetic materials have been used. Furthermore, in the selective CVD method, a conventional technique is known in which the substrate is irradiated with light with a wavelength of 200 to 11,000 nm in a reactive gas atmosphere to form an intermediate product with good adhesion to solve the above problems. (Refer to Japanese Patent Application Laid-Open No. 61-274345).

(発明が解決しようとする課題〕 前記した従来例による多層配線形成法においては、プラ
ズマによる基体への損傷や炉内金属からの汚染、あるい
は例えば800″C以上の高温さ−キングを必要とする
など、実用上は問題があった。
(Problems to be Solved by the Invention) In the conventional multilayer wiring forming method described above, damage to the substrate due to plasma, contamination from metal in the furnace, or high temperature of 800"C or higher is required. There were problems in practical use.

また密着性の良い中間生成物が形成されても、自然酸化
膜の除去という観点からは、必ずしも満足な結果が得ら
れるとは言い難い一面があった。
Further, even if an intermediate product with good adhesion is formed, it is difficult to say that a satisfactory result is necessarily obtained from the viewpoint of removing a natural oxide film.

そこで本発明の課題は、半導体等の基体上の層間絶縁膜
に開口した接続孔内部に導電性材料を埋め込んで多層配
線を形成するに際して、接続孔底部に露出した基体表面
の自然酸化膜を効果的に除去し、ここに連続的に導電性
材料を埋め込むことにより、低くしかもオーミンクなコ
ンタクト抵抗を持つ多層配線を形成する方法と装置を提
供する事である。併せて、前記導電性材料の埋め込みを
選択CVDにより行う場合においては、良好な選択成長
が行われるような多層配線を形成する方法と装置を提供
する事である。
Therefore, an object of the present invention is to effectively reduce the natural oxide film on the surface of the substrate exposed at the bottom of the connection hole when forming a multilayer wiring by burying a conductive material inside the connection hole opened in an interlayer insulating film on a substrate such as a semiconductor. It is an object of the present invention to provide a method and apparatus for forming a multilayer wiring having low and ohmic contact resistance by removing the conductive material and continuously embedding a conductive material therein. Another object of the present invention is to provide a method and apparatus for forming a multilayer wiring that allows good selective growth when the conductive material is buried by selective CVD.

[課題を解決するための手段] 前述した課題を達成するため、本発明における多層配線
形成方法は、半導体等の基体上の層間絶縁膜に開口した
接続孔内部に導電性材料を埋め込むに際して、まず還元
性雰囲気中において接続孔底部に紫外線照射を施し、次
いで連続的にこの接続孔内部に導電性材料を埋め込むこ
とを特徴とするものである。ここで用いた連続的という
語は、基体を大気に露出させることなくという意味であ
る。また還元性雰囲気とは、水素(11□)または重水
素(D2)ガスのことを言い、紫外線照射とは400 
nm以下の波長の光の照射を意味し、単色光あるいは連
続スペクトル光の別を問わない。光源は特に限定するも
のではな(、低圧水銀ランプ、重水素ランプ、ArF等
のエキシマレーザ等、基体上の自然酸化膜を還元する作
用を持ち、本発明の目的を達成しうる範囲内の光源を任
意に選定することが可能である。接続孔内部に導電性材
料を埋め込む導電性材料堆積方法は、これも特に限定を
設けるものではなく、選択CVD、ブランケットCVD
さらにスパッタリングによる方法等を目的により任意に
用いることが可能である。
[Means for Solving the Problems] In order to achieve the above-mentioned problems, the multilayer interconnection forming method of the present invention first includes the steps of filling a conductive material into a contact hole opened in an interlayer insulation film on a substrate such as a semiconductor. The method is characterized in that the bottom of the connection hole is irradiated with ultraviolet rays in a reducing atmosphere, and then a conductive material is continuously embedded inside the connection hole. The term continuous, as used herein, means without exposing the substrate to the atmosphere. Also, reducing atmosphere refers to hydrogen (11□) or deuterium (D2) gas, and ultraviolet irradiation refers to 400
It means the irradiation of light with a wavelength of nm or less, regardless of whether it is monochromatic light or continuous spectrum light. The light source is not particularly limited (e.g., a low-pressure mercury lamp, a deuterium lamp, an excimer laser such as ArF, etc.) that has the effect of reducing the natural oxide film on the substrate and that can achieve the purpose of the present invention. The conductive material deposition method for embedding the conductive material inside the contact hole is not particularly limited, and may be selective CVD or blanket CVD.
Furthermore, it is possible to arbitrarily use a method such as sputtering depending on the purpose.

また本発明における連続処理装置は、上記多層配線形成
方法を可能とする、紫外線照射装置と導電性材料堆積装
置とを具備したことを特徴とする装置である。ここで紫
外線照射装置とは、前記光源により基体を照射する機能
を持ち、かつ前記還元性雰囲気を使用しうる防爆型のチ
ャンバを有するものである。また導電性材料堆積装置と
は、特に限定するものではなく、選択CVD、プランケ
ットCVDさらにスパッタリング等本発明の目的を達成
しうる装置であればいずれも使用可能である。紫外線照
射装置のチャンバと、導電性材料堆積装置のチャンバと
を別体に設ける場合には、基体が大気に露出することな
く再装置間を移動しうる例えばゲートバルブにより両装
置が接続されるように構成する。勿論−つのチャンバで
両装置の機能を兼ねるように構成することも可能である
Further, the continuous processing apparatus according to the present invention is an apparatus characterized in that it is equipped with an ultraviolet irradiation device and a conductive material deposition device, which enable the above-described multilayer wiring formation method. Here, the ultraviolet irradiation device has an explosion-proof chamber that has the function of irradiating the substrate with the light source and can use the reducing atmosphere. The conductive material deposition apparatus is not particularly limited, and any apparatus that can achieve the object of the present invention, such as selective CVD, Plunkett CVD, and sputtering, can be used. When the chamber of the ultraviolet irradiation device and the chamber of the conductive material deposition device are provided separately, the two devices may be connected by, for example, a gate valve that allows the substrate to be moved between the devices without being exposed to the atmosphere. Configure. Of course, it is also possible to configure the apparatus so that two chambers serve the functions of both apparatuses.

〔作用〕[Effect]

接続孔底部に露出したシリコン等の半導体基体表面に生
成した自然酸化膜は、還元性雰囲気中で紫外線照射を施
すことにより、例えば次式のごとく還元され除去される
ので、選択CVDにおいては選択性が向上し、確実な選
択成長が可能となる。
A natural oxide film formed on the surface of a semiconductor substrate such as silicon exposed at the bottom of a contact hole is reduced and removed by irradiation with ultraviolet rays in a reducing atmosphere as shown in the following equation, so selective CVD is not effective in selective CVD. will be improved, and reliable selective growth will be possible.

SiO□+28z→ Si  +2HzO3iO□+H
t→ SiO+ H2O 5tO+ )12→ St  + HzO同時に接続孔
底部に露出したシリコン等の半導体基体最表面のみが昇
温され、ドーパントの活性化が効果的に進行するので、
自然酸化膜除去の効果とあわせて、コンタクト抵抗値が
小さく、かつオーミックなコンタクトを持つ多層配線が
可能となる。
SiO□+28z→ Si +2HzO3iO□+H
t→ SiO+ H2O 5tO+ ) 12→ St + HzO At the same time, only the outermost surface of the semiconductor substrate such as silicon exposed at the bottom of the contact hole is heated, and the activation of the dopant proceeds effectively.
In addition to the effect of removing the native oxide film, it becomes possible to create multilayer interconnections with low contact resistance and ohmic contacts.

本発明による多層配線形成装置は、例えばゲートバルブ
により紫外線照射装置のチャンバと、導電性材料堆積装
置のチャンバとが接続されるように構成されており、あ
るいは両装置が一体に構成されており、半導体等の基体
が大気に露出することなく、換言すれば接続孔底部に現
れている基体表面に自然酸化膜を形成することなく導電
性材料を堆積することを可能とする。
The multilayer wiring forming apparatus according to the present invention is configured such that the chamber of the ultraviolet irradiation device and the chamber of the conductive material deposition device are connected, for example, by a gate valve, or the both devices are configured integrally, It is possible to deposit a conductive material without exposing a substrate such as a semiconductor to the atmosphere, in other words, without forming a natural oxide film on the surface of the substrate appearing at the bottom of a connection hole.

〔実施例〕〔Example〕

以下、本発明の一実施例について図面を参照しながら説
明する。
An embodiment of the present invention will be described below with reference to the drawings.

災立皿土 第1図は本発明の第1の実施例による連続処理装置の概
略断面図である。同図において1は紫外線照射装置であ
り、Si等の半導体基体2は紫外線照射装置1のチャン
バ内の第1のサセプタ3上に載置されている。ArFエ
キシマレーザ4からの193 runの紫外線は、たと
えば合成石英製の紫外線照射窓5を介して基体2を照射
するように配置されている。11□ガスが還元性ガス導
入孔6より導入され、図示せざる真空ポンプにより第1
の排気孔7より排気され、紫外線照射装置1のチャンバ
内を減圧された一定圧力の還元性雰囲気に保つ。
FIG. 1 is a schematic sectional view of a continuous processing apparatus according to a first embodiment of the present invention. In the figure, 1 is an ultraviolet irradiation device, and a semiconductor substrate 2 made of Si or the like is placed on a first susceptor 3 in a chamber of the ultraviolet irradiation device 1. 193 runs of ultraviolet rays from the ArF excimer laser 4 are arranged so as to irradiate the substrate 2 through an ultraviolet irradiation window 5 made of synthetic quartz, for example. 11□ Gas is introduced from the reducing gas introduction hole 6, and the first
The inside of the chamber of the ultraviolet irradiation device 1 is maintained at a reduced pressure and a reducing atmosphere at a constant pressure.

11は導電性材料堆積装置であり、本実施例においては
選択CVDを行うための装置である。基体2は図示せざ
る移送手段により、例えばゲートバルブ10を介して再
装置間を大気に露出することなく移送することが可能と
なるように構成されている。紫外線照射装置1より移送
された基体2は第2のサセプタ12上に載置され、反応
ガス導入孔13より導入される反応ガスは、これも図示
せざる真空ポンプにより第2の排気孔14より排気され
、導電性材料堆積装置11のチャンバ内を減圧された一
定圧力の反応ガス雰囲気に保つ。
Reference numeral 11 denotes a conductive material deposition apparatus, which in this embodiment is an apparatus for performing selective CVD. The base body 2 is configured to be able to be transferred between apparatuses by a transfer means (not shown), for example, via a gate valve 10 without being exposed to the atmosphere. The substrate 2 transferred from the ultraviolet irradiation device 1 is placed on the second susceptor 12, and the reaction gas introduced from the reaction gas introduction hole 13 is also discharged from the second exhaust hole 14 by a vacuum pump (not shown). The chamber of the conductive material deposition apparatus 11 is evacuated and maintained at a reduced pressure and a constant pressure reaction gas atmosphere.

基体2は、第1のサセプタ3および第2のサセプタ12
内のヒータ等の加熱手段により、必要に応じて任意の温
度に昇温することが可能となっている。
The base body 2 includes a first susceptor 3 and a second susceptor 12
Using heating means such as a heater inside, it is possible to raise the temperature to an arbitrary temperature as necessary.

以上のように構成された連続処理装置において、本実施
例ではタングステン(W)の選択CVDにより接続孔を
埋め込む多層配線形成方法について説明をおこなう。
In the continuous processing apparatus configured as described above, in this embodiment, a method for forming a multilayer wiring in which connection holes are filled by selective CVD of tungsten (W) will be explained.

第3図(a)〜(c)は本発明の実施例による多層配線
形成方法を示す工程図である。同図(a)において、ド
ーパントとしてボロン(B)を注入したpSt半導体で
ある基体2上の、5iOt等の絶縁膜21には、接続孔
23が開口している。通常、この基体2をフッ化水素(
HF)水等によるウェットエツチングで前処理した後純
水洗浄を施したり、あるいは基体2を大気中に露出した
りすると、接続孔23底部に現れている基体2表面には
、わずかながら自然酸化膜22が成長する。そこでこの
基体2を紫外線照射装置1の第10サセプタ3上に設置
し、H2ガスを還元性ガス導入孔6より導入し、第1の
排気孔7よりこれを減圧排気し、紫外線照射装置1のチ
ャンバ内を例えば10Torrに減圧された還元性雰囲
気に保つ。次にArFのエキシマレーザ4による193
nmの紫外線24を、紫外線照射窓5を介して基体2全
面にステップ的に第3図(b)に示すように照射する。
FIGS. 3(a) to 3(c) are process diagrams showing a method for forming multilayer wiring according to an embodiment of the present invention. In the figure (a), a connection hole 23 is opened in an insulating film 21 made of 5iOt or the like on a base 2 which is a pSt semiconductor into which boron (B) is implanted as a dopant. Usually, this substrate 2 is hydrogen fluoride (
HF) If the substrate 2 is pretreated with wet etching using water or the like and then cleaned with pure water, or if the substrate 2 is exposed to the atmosphere, a slight natural oxide film will form on the surface of the substrate 2 appearing at the bottom of the connection hole 23. 22 grows. Therefore, this base body 2 is installed on the tenth susceptor 3 of the ultraviolet irradiation device 1, H2 gas is introduced through the reducing gas introduction hole 6, and the gas is depressurized and exhausted through the first exhaust hole 7. The inside of the chamber is maintained in a reducing atmosphere with a reduced pressure of, for example, 10 Torr. Next, 193 by ArF excimer laser 4
The entire surface of the substrate 2 is irradiated with ultraviolet rays 24 of nm wavelength through the ultraviolet irradiation window 5 in a stepwise manner as shown in FIG. 3(b).

この時の照射条件はパルスエネルギー50mJ/pul
se、繰り返し周波数10Hz、パルス幅10n3とし
た。
The irradiation conditions at this time were pulse energy of 50 mJ/pul.
se, repetition frequency 10Hz, and pulse width 10n3.

この紫外線照射により、自然酸化膜22は還元除去され
ると共に、基体2最表面のみ温度が上昇しドーパントの
活性化が行われる。このときのドーパントの活性化率は
、表面のキャリヤ濃度が10g。
By this ultraviolet irradiation, the natural oxide film 22 is reduced and removed, and the temperature of only the outermost surface of the substrate 2 is increased to activate the dopant. The activation rate of the dopant at this time is that the carrier concentration on the surface is 10 g.

013以上が達成され、この値は900°C程度の電気
炉アニールで得られる値よりも大きく 、p” −Si
に対する−の障壁高さφ。=0.67eVを充分にクリ
アするものであった。
013 or more, which is larger than the value obtained by electric furnace annealing at about 900°C,
− barrier height φ for. = 0.67 eV.

次に紫外線照射を終えた基体2を、大気に露出させるこ
となくゲートバルブ10を経由して導電性材料堆積装置
11のチャンバ内に移送し、第2のサセプタ12上に載
置する。反応ガス導入孔13より、6フツ化タングステ
ン(WF6)を10scc+a、シラン(SHE)を5
iees、11□を1000iCC,、lの混合ガスを
導入し、第2の排気孔14より減圧排気し、導電性材料
堆積装置11のチャンバ内を0,2Torrに保つ。次
に基体2はサセプタ12内のヒータにより例えば260
°Cに加熱する。以上により第3図(c)に示すように
、接続孔23内には−よりなる導電性材料25が選択成
長して埋め込まれた。この導電性材料25の埋め込みに
より、コンタクト抵抗値が小さく、オーミック性に優れ
た多層配線を形成することが可能であった。
Next, the substrate 2 that has been irradiated with ultraviolet rays is transferred into the chamber of the conductive material deposition apparatus 11 via the gate valve 10 without being exposed to the atmosphere, and placed on the second susceptor 12. From the reaction gas introduction hole 13, 10scc+a of tungsten hexafluoride (WF6) and 5scc of silane (SHE) were added.
A mixed gas of 1000 iCC, 1 is introduced into the chamber of 11□, and the pressure is evacuated from the second exhaust hole 14 to maintain the inside of the chamber of the conductive material deposition apparatus 11 at 0.2 Torr. Next, the base body 2 is
Heat to °C. As shown in FIG. 3(c), the electrically conductive material 25 made of - is selectively grown and embedded in the connection hole 23 as described above. By embedding the conductive material 25, it was possible to form a multilayer interconnection with low contact resistance and excellent ohmic properties.

ス11汁l 第2図は本発明の第2の実施例による連続処理装置の概
略断面図である。同図では実施例1と同じ機能を持つ部
分には、第1図で用いたものと同じ名称と番号を付しで
ある。本実施例においては紫外線照射装置1と導電性材
料堆積装置11とが、同一のチャンバを共有する場合に
ついて述べる。
Figure 2 is a schematic sectional view of a continuous processing apparatus according to a second embodiment of the present invention. In the figure, parts having the same functions as those in the first embodiment are given the same names and numbers as those used in FIG. In this embodiment, a case will be described in which the ultraviolet irradiation device 1 and the conductive material deposition device 11 share the same chamber.

15は重水素ランプであり、400nm以下の波長の連
続スペクトル紫外光を、例えば合成石英製の紫外線照射
窓5を介して、第3のサセプタ9上の基体2を照射する
ように配置されている。基体2は、例えば第3のサセプ
タ9に内蔵されたヒータにより任意の温度に昇温できる
ように構成されている。
15 is a deuterium lamp, which is arranged to irradiate the substrate 2 on the third susceptor 9 with continuous spectrum ultraviolet light having a wavelength of 400 nm or less, for example, through an ultraviolet irradiation window 5 made of synthetic quartz. . The base body 2 is configured to be able to be heated to an arbitrary temperature by, for example, a heater built into the third susceptor 9.

チャンバ内の圧力は、図示せざる真空ポンプにより第3
の排気孔8を介して減圧された一定の値に保たれる。
The pressure inside the chamber is controlled by a third vacuum pump (not shown).
The pressure is maintained at a constant value by reducing the pressure through the exhaust hole 8.

以上のように構成された連続処理装置において、本実施
例ではポリシリコン(p−Si)の選択CVDにより接
続孔を埋め込む多層配線形成方法について同じく第3図
を用いて説明をおこなう。
In the continuous processing apparatus configured as described above, in this embodiment, a method for forming a multilayer wiring in which connection holes are filled by selective CVD of polysilicon (p-Si) will be explained using FIG. 3 as well.

同図(a)において、Si等の半導体である基体2上の
SiO□等の絶縁膜21には、接続孔23が開口してい
る。接続孔23底部に現れている基体2表面には、わず
かながら自然酸化膜22が残されている。この基体2を
チャンバ内の第3のサセプタ9上に設置し、例えば60
0°Cに昇温すると共に、重水素(D2)ガスを還元性
ガス導入孔6より導入し、第3の排気孔8より減圧排気
し、チャンバ内を例えば50Torrに減圧された還元
性雰囲気に保つ。次に重水素ランプ15の紫外線24を
紫外線照射窓5を介して基体2全面に一様に第3図(b
)に示すように照射する。重水素ランプ15の出力は例
えば150Wとした。この照射により、チャンバ内の重
水素は励起され、接続孔23底部に現れている基体2表
面の自然酸化膜22が次式のように還元除去される。
In FIG. 2A, a connection hole 23 is opened in an insulating film 21 made of SiO□ or the like on a substrate 2 made of a semiconductor such as Si. A small amount of the natural oxide film 22 remains on the surface of the base 2 appearing at the bottom of the connection hole 23. This substrate 2 is placed on a third susceptor 9 in the chamber, and
While raising the temperature to 0°C, deuterium (D2) gas is introduced through the reducing gas introduction hole 6, and the pressure is evacuated through the third exhaust hole 8, so that the inside of the chamber is reduced to a reducing atmosphere of, for example, 50 Torr. keep. Next, the ultraviolet rays 24 of the deuterium lamp 15 are uniformly applied to the entire surface of the base 2 through the ultraviolet irradiation window 5 as shown in FIG.
). The output of the deuterium lamp 15 was, for example, 150W. By this irradiation, deuterium in the chamber is excited, and the natural oxide film 22 on the surface of the base 2 appearing at the bottom of the connection hole 23 is reduced and removed as shown in the following equation.

5i02+20.→ Si  +2DzO3ing +
 02→ SiO+ D、03iO+ Dz→ Si 
 + DzO次に紫外線照射を終えた基体2を、同じチ
ャンバ内のサセプタ9上に載置して600°Cに保持し
たまま、反応性ガス導入孔13から例えばジクロルシラ
ン(SiH2Ch) 1005ccraと塩化水素(H
CI) 10 、CIおよびH210000、C,、の
混合ガスを導入し、第3の排気孔より図示せざる真空ポ
ンプにより減圧排気してチャンバ内圧力を100 To
rrに保つ。以上により接続孔23内部には第3図(c
)のようにp−Siによる導電性材料25が自己整合的
に選択成長し、埋め込みが行われた。この後、目的に応
じて2フツ化ボロンイオン(BF2 ” )またはリン
イオン(P”)等のN型またはP型の不純物イオンを注
入し、さらに活性化熱処理を加えることにより、コンタ
クト抵抗値が小さく、オーミック性に優れた多層配線を
形成することが可能となるのである。
5i02+20. → Si +2DzO3ing +
02→ SiO+ D, 03iO+ Dz→ Si
+DzO Next, the substrate 2 that has been irradiated with ultraviolet rays is placed on the susceptor 9 in the same chamber, and while maintained at 600°C, for example, 1005 ccra of dichlorosilane (SiH2Ch) and hydrogen chloride ( H
A mixed gas of CI) 10, CI and H210000, C, is introduced and evacuated from the third exhaust hole using a vacuum pump (not shown) to reduce the chamber internal pressure to 100 To
Keep it at rr. As a result of the above, the inside of the connection hole 23 is
), a conductive material 25 made of p-Si was selectively grown in a self-aligned manner and embedded. After this, depending on the purpose, N-type or P-type impurity ions such as boron difluoride ions (BF2'') or phosphorus ions (P'') are implanted, and an activation heat treatment is applied to reduce the contact resistance. , it becomes possible to form multilayer wiring with excellent ohmic properties.

以上本発明の実施例について詳細な説明を加えたが、本
発明の趣旨とするところは半導体等の基体上の層間絶縁
膜に開口した接続孔内部に導電性材料を埋め込むに際し
て、まず還元性雰囲気中において接続孔底部に紫外線照
射を施し、次いで連続的にこの接続内部に導電性材料を
埋め込むことを特徴とするものである。従って、紫外線
照射のための光源は前記したものの他に、KrF (2
48nm)、XeC1(308ni)等のガス媒体を用
いるエキシマレーザ、低圧水銀ランプ、キセノンアーク
ランプ等、400nm以下の波長の光を照射し、本発明
の効果を発揮しうるちのを任意に使用することができる
Although a detailed explanation has been given above of the embodiments of the present invention, the gist of the present invention is that when embedding a conductive material into a connection hole opened in an interlayer insulating film on a substrate such as a semiconductor, first a reducing atmosphere is applied. The method is characterized in that the bottom of the connection hole is irradiated with ultraviolet rays, and then a conductive material is continuously embedded inside the connection. Therefore, in addition to the above-mentioned light sources, KrF (2
48nm), an excimer laser using a gas medium such as XeC1 (308ni), a low-pressure mercury lamp, a xenon arc lamp, etc., which irradiates light with a wavelength of 400nm or less, and which exhibits the effects of the present invention, may be used as desired. I can do it.

また導電性材料堆積装置としては、前記した選択CVD
装置によるものが自己整合的な選択性を向上でき、最も
効果的である。しかし本発明はこの装置に限定されるも
のではなく、ブランケットCVDを施すための装置、ス
パッタリング装置、さらには蒸着装置等が用いることが
できる。これら非選択的な堆積装置を用いる場合には、
言うまでもなくエッチバックを併用して接続孔近辺の配
線パターンを残すこととなる。
In addition, as a conductive material deposition apparatus, the above-mentioned selective CVD
The method using a device can improve self-aligned selectivity and is the most effective. However, the present invention is not limited to this apparatus, and a blanket CVD apparatus, a sputtering apparatus, a vapor deposition apparatus, and the like can be used. When using these non-selective deposition devices,
Needless to say, etchback is also used to leave the wiring pattern near the connection hole.

前記2つの実施例においては、基体2の昇温方法として
サセプタに内蔵したヒータを用いたが、これも特に限定
されるものでなく、ハロゲンランプや高周波加熱等が使
用できる。
In the two embodiments described above, a heater built into the susceptor was used to raise the temperature of the substrate 2, but this is not particularly limited either, and a halogen lamp, high frequency heating, etc. can be used.

また、接続孔内に埋め込む導電性材料については、Wや
p−3iの他、Mo等の高融点金属やアルミニウム(A
I)、A1合金、銅(Cu)等が目的に応じて使用する
ことが可能であり、これらの材料すべてについて、低く
しかもオーミックなコンタクト抵抗を持つ多層配線を形
成することが可能である。
In addition to W and p-3i, the conductive materials to be buried in the connection holes include high-melting point metals such as Mo and aluminum (A
I), A1 alloy, copper (Cu), etc. can be used depending on the purpose, and it is possible to form a multilayer wiring having low and ohmic contact resistance using all of these materials.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように、本発明における多層配線形成方法
は、半導体等の基体上の眉間絶縁膜に開口した接続孔内
部に導電性材料を埋め込むに際して、まず還元性雰囲気
中において接続孔底部に紫外線照射を施し、次いで連続
的にこの接続孔内部に導電性材料を埋め込むことにより
、コンタクト抵抗値が小さ(、かつオーミンクなコンタ
クトを持つ多層配線が可能となり、半導体装置のデバイ
ス特性が向上しかつ安定する。また本発明における連続
処理装置によれば、紫外線照射と導電性材料堆積とを連
続して施すことができるので、前記特徴を持つ多層配線
が確実にかつ再現性よ〈実施できる。とりわけ、導電性
材料堆積装置として選択CVD装置を用いれば、自己整
合的な選択性を向上することができ、−層効果的である
。以上、接続孔への導電性材料の埋め込みにおいて、従
来の方法と装置では未解決であった信頼性に優れた多層
配線が可能となり、半導体装置製造工程におよぼす寄与
は大きい。
As described in detail above, in the method for forming multilayer wiring according to the present invention, when embedding a conductive material inside a contact hole opened in a glabellar insulating film on a substrate such as a semiconductor, first, the bottom of the contact hole is exposed to ultraviolet light in a reducing atmosphere. By applying irradiation and then continuously embedding a conductive material inside the contact hole, it is possible to create multilayer interconnections with low contact resistance (and ohmic contacts), which improves and stabilizes the device characteristics of semiconductor devices. Furthermore, according to the continuous processing apparatus of the present invention, since ultraviolet irradiation and conductive material deposition can be performed continuously, multilayer wiring having the above characteristics can be produced reliably and reproducibly.In particular, If a selective CVD device is used as a conductive material deposition device, the self-aligned selectivity can be improved and the layer effect will be improved. Multi-layer wiring with excellent reliability, which has not yet been achieved in devices, has become possible, and this will greatly contribute to the semiconductor device manufacturing process.

図(a)〜(c)は本発明の実施例による多層配線形成
方法を示す工程図である。
Figures (a) to (c) are process diagrams showing a method for forming multilayer wiring according to an embodiment of the present invention.

1−−−−−−・−・・−紫外線照射装置2・−−−−
−−−−−−・−・・基体4−−−−−−−−−−−−
−−−一エキシマレーザ5−・−・−・−・紫外線照射
窓 10   ・・−ゲートバルブ 11−・−・・−・−・・−導電性材料堆積装置15−
・−・−−−−−−−・・−重水素ランプ21−・−・
−・−層間絶縁膜 22・−・−−一−−−−−・−自然酸化膜23・・−
−一一−−−−−−−−−接続孔24・−・−・−一一
−−−−紫外線 25・・−・−・・・−・−導電性材料
1---------・--・-Ultraviolet irradiation device 2・----
---------・--・Substrate 4-----------
--- Eximer laser 5 --- Ultraviolet irradiation window 10 -- Gate valve 11 --- Conductive material deposition device 15 --
・−・−−−−−−−・・−Deuterium lamp 21−・−・
−・−Interlayer insulating film 22・−・−−1−−−−−・−Natural oxide film 23・・−
−11−−−−−−−−Connection hole 24・−・−・−11−−−−Ultraviolet light 25・−・−−・−・−Conductive material

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例による連続処理装置の概
略断面図、第2図は本発明の第2の実施例による連続処
理装置の概略断面図、そして第3本発明の第1の実施に
よる 第1図 本発明の第2の実施イiすによる 連続処理秩厘の概恥面図 匈≠q /+11 ml ↓↓↓↓↓↓↓↓;↓↓↓↓ト24 柴タト線本発明の
実施例による 叉眉配線形へ方法と示す工程図
FIG. 1 is a schematic cross-sectional view of a continuous processing apparatus according to a first embodiment of the present invention, FIG. 2 is a schematic cross-sectional view of a continuous processing apparatus according to a second embodiment of the present invention, and third FIG. Fig. 1 by carrying out the second embodiment of the present invention Approximate view of the shameful face of Chichirin by continuous processing according to the second embodiment of the present invention A process diagram illustrating a method for forming a forked wire according to an embodiment of the present invention.

Claims (1)

【特許請求の範囲】 1、基体上の接続孔底部に、還元性雰囲気中で紫外線照
射を施し、次いで連続的に導電性材料を前記接続孔内部
に埋め込むことを特徴とする多層配線形成方法。 2、紫外線照射装置と、導電性材料堆積装置とを具備し
たことを特徴とする、請求項1記載の多層配線形成方法
を施すための連続処理装置。
[Scope of Claims] 1. A method for forming multilayer wiring, which comprises: irradiating the bottom of a contact hole on a substrate with ultraviolet rays in a reducing atmosphere, and then continuously filling the inside of the contact hole with a conductive material. 2. A continuous processing apparatus for carrying out the multilayer interconnection forming method according to claim 1, comprising an ultraviolet irradiation device and a conductive material deposition device.
JP9300189A 1989-04-14 1989-04-14 Multilayer wiring forming method and continuous processing apparatus Expired - Fee Related JP2832991B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9300189A JP2832991B2 (en) 1989-04-14 1989-04-14 Multilayer wiring forming method and continuous processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9300189A JP2832991B2 (en) 1989-04-14 1989-04-14 Multilayer wiring forming method and continuous processing apparatus

Publications (2)

Publication Number Publication Date
JPH02272750A true JPH02272750A (en) 1990-11-07
JP2832991B2 JP2832991B2 (en) 1998-12-09

Family

ID=14070132

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9300189A Expired - Fee Related JP2832991B2 (en) 1989-04-14 1989-04-14 Multilayer wiring forming method and continuous processing apparatus

Country Status (1)

Country Link
JP (1) JP2832991B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03263319A (en) * 1990-03-13 1991-11-22 Tokyo Electron Ltd Film forming method
US5930608A (en) * 1992-02-21 1999-07-27 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor in which the channel region of the transistor consists of two portions of differing crystallinity
US6323069B1 (en) 1992-03-25 2001-11-27 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor using light irradiation to form impurity regions
US6331717B1 (en) 1993-08-12 2001-12-18 Semiconductor Energy Laboratory Co. Ltd. Insulated gate semiconductor device and process for fabricating the same
US6458200B1 (en) * 1990-06-01 2002-10-01 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating thin-film transistor
US6500703B1 (en) 1993-08-12 2002-12-31 Semicondcutor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and process for fabricating the same
JP2008057048A (en) * 2007-11-02 2008-03-13 Ulvac Japan Ltd Method for forming barrier film
JP2011216597A (en) * 2010-03-31 2011-10-27 Fujitsu Semiconductor Ltd Method for manufacturing semiconductor device and film forming apparatus

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03263319A (en) * 1990-03-13 1991-11-22 Tokyo Electron Ltd Film forming method
US6458200B1 (en) * 1990-06-01 2002-10-01 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating thin-film transistor
US7018874B2 (en) 1990-06-01 2006-03-28 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating thin-film transistor
US6740547B2 (en) 1990-06-01 2004-05-25 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating thin-film transistor
US6717180B2 (en) 1991-02-22 2004-04-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US6352883B1 (en) 1991-02-22 2002-03-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US5930608A (en) * 1992-02-21 1999-07-27 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor in which the channel region of the transistor consists of two portions of differing crystallinity
US6569724B2 (en) 1992-03-25 2003-05-27 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor and method for forming the same
US6323069B1 (en) 1992-03-25 2001-11-27 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor using light irradiation to form impurity regions
US6887746B2 (en) 1992-03-25 2005-05-03 Semiconductor Energy Lab Insulated gate field effect transistor and method for forming the same
US6437366B1 (en) 1993-08-12 2002-08-20 Semiconductor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and process for fabricating the same
US6500703B1 (en) 1993-08-12 2002-12-31 Semicondcutor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and process for fabricating the same
US6331717B1 (en) 1993-08-12 2001-12-18 Semiconductor Energy Laboratory Co. Ltd. Insulated gate semiconductor device and process for fabricating the same
JP2008057048A (en) * 2007-11-02 2008-03-13 Ulvac Japan Ltd Method for forming barrier film
JP2011216597A (en) * 2010-03-31 2011-10-27 Fujitsu Semiconductor Ltd Method for manufacturing semiconductor device and film forming apparatus

Also Published As

Publication number Publication date
JP2832991B2 (en) 1998-12-09

Similar Documents

Publication Publication Date Title
KR100236500B1 (en) Apparatus and method for forming low contact resistivity barrier layer and conductive via
US7452810B2 (en) Method of forming a barrier layer of a semiconductor device
US4517225A (en) Method for manufacturing an electrical interconnection by selective tungsten deposition
JP3528665B2 (en) Method for manufacturing semiconductor device
JP3937892B2 (en) Thin film forming method and semiconductor device manufacturing method
US20090039475A1 (en) Apparatus and Method for Manufacturing Semiconductor
US5876796A (en) Process for selectively depositing a refractory metal silicide on silicon, and silicon wafer metallized using this process
JPH09148268A (en) Method for manufacturing semiconductor device
JPH0666289B2 (en) Nitride plasma self-aligned tungsten system for VLSI interconnection
JP3606095B2 (en) Manufacturing method of semiconductor device
JPH0697111A (en) Formation of barrier metal
JPS61203636A (en) Formation of heatproof metal silicide layer
JP2742590B2 (en) Method for manufacturing semiconductor device
JPH11150084A (en) Semiconductor device and forming method of amorphous silicon titanium nitride on substrate
JPH02272750A (en) Formation of multilayer wiring and continuous treatment device
JPS61140175A (en) Manufacture of semiconductor device
EP0460918B1 (en) Semiconductor device having improved insulated gate type transistor
JP2000150653A (en) Manufacture of semiconductor device
JP2726438B2 (en) Thin film forming equipment
US4612257A (en) Electrical interconnection for semiconductor integrated circuits
US20060048706A1 (en) Apparatus for manufacturing semiconductor device and method for manufacturing semiconductor device by using the same
JP3571160B2 (en) Method for forming oxide film on semiconductor surface and method for manufacturing semiconductor device
JP4255203B2 (en) Manufacturing method of semiconductor device
JPH06120355A (en) Manufacture of semiconductor device
JPH11317452A (en) Semiconductor device and manufacture thereof

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees