JPH02271412A - Charging circuit also used for measuring number of individual instructions - Google Patents
Charging circuit also used for measuring number of individual instructionsInfo
- Publication number
- JPH02271412A JPH02271412A JP1093470A JP9347089A JPH02271412A JP H02271412 A JPH02271412 A JP H02271412A JP 1093470 A JP1093470 A JP 1093470A JP 9347089 A JP9347089 A JP 9347089A JP H02271412 A JPH02271412 A JP H02271412A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- output
- register
- measured
- instructions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005259 measurement Methods 0.000 claims description 12
- 230000004044 response Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
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- Debugging And Monitoring (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電子計算機システムに関し、特に個別命令数測
定を兼ねた課金回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic computer system, and particularly to a billing circuit that also measures the number of individual instructions.
電子計算機システムにおける課金方式の一手段として、
各命令コードに対して重み付けされた値を課金情報とし
て累積加算するものがある。この種の課金回路を用いて
個別命令数を測定する場合、被測定命令に対応する課金
情報(重み値)のみ1とし、他は0となるように重み値
を格納したメモリを初期設定することにより測定してい
た。As a method of charging in electronic computer systems,
Some methods cumulatively add weighted values for each instruction code as billing information. When measuring the number of individual instructions using this type of billing circuit, the memory that stores the weight values should be initially set so that only the billing information (weight value) corresponding to the instruction being measured is set to 1, and the others are set to 0. It was measured by
従来の課金回路を用いて命令数を測定する場合には、被
測定命令を変更するたびにメモリの内容を再設定しなけ
ればならず、続けていくつもの命令の実行回数を測定す
る場合には効率が悪くなるという欠点がある。When measuring the number of instructions using a conventional accounting circuit, the contents of the memory must be reset every time the instruction to be measured is changed, and when measuring the number of executions of several instructions in succession, The disadvantage is that it is less efficient.
本発明の個別命令数測定を兼ねた課金回路は、命令コー
ドに対応して重み付けされた値を課金情報として累積加
算する課金回路において、命令コードを保持する命令レ
ジスタと、前記命令コードをデコードするメモリ手段と
、命令数測定を指示する命令数測定フラグと、被測定命
令コードを保持する被測定命令レジスタと、前記命令コ
ードと前記被測定命令コードとを比較する比較器と、前
記命令数測定フラグと前記比較器との出力に応じて選択
信号を作成する選択信号作成回路と、前記選択信号作成
回路の出力に応答して前記メモリ手段の出力とあらかじ
め定められた値とを選択するセレクタと、前記セレクタ
の出力を累積するカウンタとを備えて構成される。The billing circuit that also measures the number of individual instructions of the present invention cumulatively adds a weighted value corresponding to the instruction code as billing information. a memory means, an instruction count measurement flag for instructing instruction count measurement, a measured instruction register for holding a measured instruction code, a comparator for comparing the instruction code with the measured instruction code, and the instruction count measurement. a selection signal creation circuit that creates a selection signal in response to a flag and the output of the comparator; and a selector that selects the output of the memory means and a predetermined value in response to the output of the selection signal creation circuit. , and a counter that accumulates the outputs of the selector.
以下本発明について図面を参照して詳細に説明する。 The present invention will be described in detail below with reference to the drawings.
第1図は本発明の一実施例の構成を示すブロック図であ
って、課金回路において本発明に関連する部分のみを示
したものである。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and shows only the portions of the billing circuit that are related to the present invention.
第1図において10が被測定命令レジスタ(CIR)、
20が命令レジスタ(IR)、30が被測定命令レジス
タ(CIR)10と命令レジスタ(IR>20を比較器
、40が命令数測定フラグ(CF)、50が(IR)を
デコードするメモリ手段、60が比較器30の出力と命
令数測定フラグ(CF)40の出力に応じてメモリ手段
50とあらかじめ定められた値とを選択するセレクタ、
80がセレクタ70の出力を累積するカウンタ、81が
加算器(WIC)、82がレジスタ(WIC)81の出
力を保持するレジスタ(WICR)82がレジスタ(W
ICR)82の出力を制御する制御回路である。In FIG. 1, 10 is a measured instruction register (CIR);
20 is an instruction register (IR), 30 is a comparator between the instruction register under measurement (CIR) 10 and the instruction register (IR>20), 40 is an instruction count measurement flag (CF), 50 is a memory means for decoding (IR), 60 is a selector that selects the memory means 50 and a predetermined value according to the output of the comparator 30 and the output of the instruction count measurement flag (CF) 40;
80 is a counter that accumulates the output of the selector 70, 81 is an adder (WIC), 82 is a register (WIC), and a register (WICR) that holds the output of 81 is a register (WIC).
This is a control circuit that controls the output of ICR) 82.
次にこの課金回路の動作について説明する。Next, the operation of this billing circuit will be explained.
今、命令レジスタ(IR)20に命令コードがセットさ
れるとその命令コードをアドレスとしてメモリ手段50
を読み出し、その出力を加算器(WIC>81によって
レジスタ(WICR)82の出力と累積加算されて再び
レジスタ(WICR)82にセーブされる。メモリ手段
50には命令レジスタ(IR)20に対応して重み付け
された値があらかじめ格納されており、この値を課金情
報として累積加算することができる。Now, when an instruction code is set in the instruction register (IR) 20, the memory means 50 uses the instruction code as an address.
The output is cumulatively added to the output of the register (WICR) 82 by an adder (WIC>81) and saved in the register (WICR) 82 again. A weighted value is stored in advance, and this value can be cumulatively added as billing information.
本発明では、命令数測定フラグ(CF)40で命令数測
定の指示がある場合、被測定命令レジスタ(CIR)1
0と命令レジスタ(IR)20の出力とを比較器30に
よって比較し、一致している場合は選択信号作成回路6
0の出力を調整してセレクタ70の出力が“1”を出力
するようにする。不一致の場合はセレクタ70の出力が
ii Onになるよう選択信号作成回路60の出力を調
整する。その後、セレクタ70の出力を加算器(WIC
)81へ入力し、レジスタ(WICR)82の出力と加
算して再びレジスタ(WICR)82にセーブする。こ
の動作により、レジスタ(WICR)82には被測定命
令レジスタ(CIR)10の指定する命令コードの命令
の実行回数が累積される。すなわち、レジスタ(WIC
R)82の出力を読み出すことによって命令の実行回数
が測定できる。In the present invention, when there is an instruction to measure the number of instructions using the instruction count measurement flag (CF) 40, the measured instruction register (CIR) 1
0 and the output of the instruction register (IR) 20 are compared by the comparator 30, and if they match, the selection signal generation circuit 6
The output of 0 is adjusted so that the output of selector 70 is ``1''. If they do not match, the output of the selection signal generation circuit 60 is adjusted so that the output of the selector 70 becomes ii On. After that, the output of the selector 70 is added to the adder (WIC).
) 81, added to the output of register (WICR) 82, and saved in register (WICR) 82 again. As a result of this operation, the number of executions of the instruction of the instruction code specified by the instruction under test register (CIR) 10 is accumulated in the register (WICR) 82. That is, the register (WIC
By reading the output of R) 82, the number of instruction executions can be measured.
以上説明したように本発明は、命令数測定を指示するフ
ラグを設け、被測定命令コードと命令コードとを比較し
、それらの出力でカウンタの入力を制御することにより
、メモリの内容を再設定することなく個別命令数を測定
できるという効果がある。また、被測定命令コードをソ
フトウェアにより設定できるようにすれば、ソフトウェ
アの制御によりダイナミックに測定すべき命令が変更で
きるため、命令数の測定を効率よく実行できるという効
果がある。As explained above, the present invention provides a flag that instructs the measurement of the number of instructions, compares the instruction code to be measured with the instruction code, and controls the input of the counter using the output, thereby resetting the contents of the memory. This has the effect of being able to measure the number of individual instructions without having to do so. Furthermore, if the instruction code to be measured can be set by software, the instructions to be measured can be dynamically changed under software control, which has the effect of efficiently executing the measurement of the number of instructions.
第1図は本発明の一実施例の構成を示すブロック図であ
る。
10・・・被測定命令レジスタ(CIR)、20.、。
命令レジスタ(IR)、30・・・比較器、40・・・
命令数測定フラグ(CF)、50・・・メモリ手段、6
0・・・選択信号作成回路、70・・・セレクタ、80
・・・カウンタ、81・・・加算器(WIC)、82・
・・しジスタ(WICR)FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. 10... Instruction under test register (CIR), 20. ,. Instruction register (IR), 30... Comparator, 40...
Instruction count measurement flag (CF), 50...Memory means, 6
0... Selection signal generation circuit, 70... Selector, 80
...Counter, 81...Adder (WIC), 82.
...Shijista (WICR)
Claims (1)
して累積加算する課金回路において、命令コードを保持
する命令レジスタと、前記命令コードをデコードするメ
モリ手段と、命令数測定を指示する命令数測定フラグと
、被測定命令コードを保持する被測定命令レジスタと、
前記命令コードと前記被測定命令コードとを比較する比
較器と、前記命令数測定フラグと前記比較器との出力に
応じて選択信号を作成する選択信号作成回路と、前記選
択信号作成回路の出力に応答して前記メモリ手段の出力
とあらかじめ定められた値とを選択するセレクタと、前
記セレクタの出力を累積するカウンタとを備えて成るこ
とを特徴とする個別命令数測定を兼ねた課金回路。A billing circuit that cumulatively adds weighted values corresponding to instruction codes as billing information includes an instruction register that holds the instruction code, a memory means that decodes the instruction code, and an instruction count measurement flag that instructs to measure the number of instructions. and a measured instruction register that holds a measured instruction code.
a comparator that compares the instruction code and the instruction code under test; a selection signal creation circuit that creates a selection signal according to the instruction count measurement flag and the output of the comparator; and an output of the selection signal creation circuit. 1. A billing circuit that also measures the number of individual instructions, characterized in that it comprises a selector that selects the output of the memory means and a predetermined value in response to the above, and a counter that accumulates the output of the selector.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1093470A JPH02271412A (en) | 1989-04-12 | 1989-04-12 | Charging circuit also used for measuring number of individual instructions |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1093470A JPH02271412A (en) | 1989-04-12 | 1989-04-12 | Charging circuit also used for measuring number of individual instructions |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02271412A true JPH02271412A (en) | 1990-11-06 |
Family
ID=14083226
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1093470A Pending JPH02271412A (en) | 1989-04-12 | 1989-04-12 | Charging circuit also used for measuring number of individual instructions |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02271412A (en) |
-
1989
- 1989-04-12 JP JP1093470A patent/JPH02271412A/en active Pending
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