JPH05119166A - Microcomputer timer - Google Patents

Abstract

PURPOSE:To sequentially change the timer values of a timer incorporated in a microcomputer without using a CPU. CONSTITUTION:A microcomputer timer comprises a counter/decoder 2 with (n) reload registers 3(0) to 3(n-1) connected to one timer 1 for incrementing within a range of 0 to (n-1) with an overflow signal of the timer 1 and selecting one of the reload registers by decoding the counter value, a ROM file comprising (n) words X (m) for setting the timer value and a memory address instructing means 5 for outputting a ROM address pointer for instructing a ROM file address. Therefore a regular layout method is possible, wherein it is advantageous especially in a layout when numerous timer values are to be set. In addition the CPU load is light even if the timer values are to be sequentially changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timer, and particularly when it is incorporated in a microcomputer, the hardware configuration can be reduced, and when the timer value set in the timer is changed one after another, The present invention relates to a microcomputer timer that can reduce the load.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional microcomputer timer. 1 is a timer, 6 is a compare register, 7 is a timer 1 and a compare register 6
Is a match detection circuit that outputs a match detection signal when these input signals match.

Next, the operation will be described. The count value of the timer 1 is changing every moment by the input of a count source (not shown). Predetermined timer values detected by comparison with the timer 1 are successively written in the compare register 6 by the CPU 8. The coincidence detection circuit 7 detects the coincidence between the count value of the timer 1 and the timer value of the compare register 6 which changes depending on the input of the count source, and outputs a coincidence detection signal.

[0004]

Since the conventional timer is configured as described above, when the timer value of the compare register 6 is set, the compare register 6 provided in the hardware has a settable number of comparison times. It depends on the number of. Further, when the timer value of the compare register is changed one after another, there is a problem that the load on the CPU is large and the hardware configuration becomes enormous.

The present invention has been made to solve the above problems, and an object thereof is to obtain a computer timer which has a small load on the CPU and can be highly integrated.

[0006]

A microcomputer timer according to the present invention includes a memory (ROM file 4) such as a ROM file including a plurality of memory areas for storing timer values, and a memory address instruction for instructing the memory. When the means 5 and a plurality of reload registers 3 (0) to 3 (n-1) respectively holding the timer value and the timer value held in a predetermined reload register are set, the timer values up to this timer value are set. A timer 1 that starts timing and outputs an overflow signal when the timing ends, and a register selection means (counter that sequentially counts up by counting up each time the overflow signal is received and decodes the counted number to select the reload register). / Decoder 2).

[0007]

According to the present invention, since the timer value of the reload register can be collectively transferred to the n reload registers by the memory configured by n words × m, as many comparison time functions as can be set can be set. It is possible to secure. Further, since the reload register timer value of the reload register designated by the memory address designating means can be transferred from the memory to the reload register all at once, the CPU is involved only when rewriting the address of the memory area indicated by the memory address designating means. , CP
The load on U can be reduced.

[0008]

1 is a block diagram of a microcomputer timer according to an embodiment of the present invention. In FIG. 1, reference numeral 1 is a timer, 2 is a counter / decoder as a register selecting means for incrementing and decoding an overflow signal of the timer 1, and 3 is a reloader of n (0 to n-1) for outputting a timer value to the timer 1. Registers 4 are ROMs that store the timer values of n reload registers 3 and that are collectively transferred by n words × m.
Files 5 are memory address designating means for outputting a ROM address pointer for designating an address (0 to m-1) of an n-word ROM file in which data to be collectively transferred to the reload register 3 is stored.

The memory address designating means 5 sets the ROM address pointers 0 to m-1 to RO according to the instruction of the CPU.
Send to M file 4 and specify memory area. ROM
The file 4 is stored in the memory area designated by the memory address designating means 5 in the reload registers 3 (0) to 3 (n-1).
The timer value for n words to be transferred to is stored. The reload registers 3 (0) to (n-1) send the timer value from the reload register designated by the counter / decoder 2 to the timer. The timer 1 counts up to the sent timer value, and when the count is finished, the counter / counter
The overflow signal is output to the decoder 2. The counter / decoder 2 increments for each overflow signal, sequentially decodes the current count value, outputs it to one of the reload registers, and selects the reload register.

Next, the operation will be described. Due to the overflow signal from the timer 1 connected to the n reload registers 3, the counter / decoder 2 has 0-n-
Increment in the range of 1 (0 → 1 → 2 → ... → n-2 →
n-1 → 0 → 1 → ...) and count. Then, the count value at this time is decoded, and one of the n reload registers 3 (0) to 3 (n-1) is sequentially designated (for example, the reload register 3 (1)). The timer value is transferred from the designated reload register 3 (1) to timer 1. Further, the timer value is the k-th (0≤k≤m- of the ROM file 4 designated by the ROM address pointer from the memory address designating means.
The data is collectively transferred from the memory area of the ROM file 4 configured by n words × m stored in the memory area 1) to the reload registers 3 (0) to 3 (n-1).

[0011]

As described above, according to the present invention, the timer value of the reload register is set to CP by the batch transfer from the memory.
Since it is configured to rewrite without going through U, the C
Since it does not go through the PU, the load on the CPU is lightened. Furthermore, it is possible to adopt a regular layout method, especially when there are many timer values to set.
This is advantageous in terms of layout and has the effect of achieving high integration.

[Brief description of drawings]

FIG. 1 is a block diagram of a microcomputer timer according to an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional microcomputer timer.

[Explanation of symbols]

 1 Timer 2 Counter / Decoder 3 Reload Register 4 ROM File 5 Memory Address Instructing Means 6 Compare Register 7 Match Detection Circuit

Claims (1)

[Claims] 1. A memory such as a ROM file including a plurality of memory areas for storing a timer value, a memory address designating means for designating the memory, a plurality of reload registers for respectively holding the timer values, and a predetermined reload. When the timer value held in the register is set,
A timer that starts counting up to this timer value and outputs an overflow signal when the timing ends, and a register that counts up each time the overflow signal is received and decodes the counted value to sequentially select the reload register. A timer for a microcomputer, comprising a selecting means.