JPH02268009A - Analog circuit with dc offset compensation circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for setting directly an offset compensation period through time division of a specific time of an input signal and to simplify the circuit constitution by using an offset circuit including an integration circuit to compensate an offset in an analog circuit. CONSTITUTION:When an analog input signal is fed to an input terminal 1 and no offset compensation is applied to the input signal, then an output including an offset is obtained. An A/D converter circuit 4 converts the signal into a digital signal of 1 or 0 level depending on the signal is positive or negative. The output of the circuit 4 is fetched into a latch circuit 5 at a period of a clock phi1 and its output throws a switch 63 of a changeover circuit 6 to the position of a positive power supply voltage 61 or a negative power supply voltage 62 depending on the digital value. The output of the circuit 6 is fetched and integrated in an integration device 7 in the timing of the clock phi1 and the output voltage is sampled by a sample and hold circuit 8 in the clock phi2 and the result is inputted to an operational amplifier 25.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an analog circuit having a circuit for compensating for DC offset, and in particular, it eliminates the need to provide a special period for generating a DC offset compensation signal. Regarding the circuit configuration.

[Prior Art] Conventional DC offset compensation involves dividing the signal input period and the DC offset compensation signal generation period by time division, and applying a ground voltage (AC ground) to the input terminal of the analog circuit during the DC offset compensation signal generation period. This is done by sampling the DC offset voltage that occurs at the output terminal when the signal is applied, and subtracting this sampled voltage from the input signal during the signal input period.

[Problems to be Solved by the Invention] The conventional DC offset compensation circuit described above is configured to input the ground voltage within a certain period of the input signal and sample the output voltage of the analog circuit during that period. Therefore, it is necessary to switch the input signal to the ground voltage for a certain period of time, which requires a complicated control system such as time division processing. In particular, when a plurality of circuits are involved, as in the case of a communication system, the control system becomes even more complex because it is necessary to synchronize the switching between those circuits.

[Means for Solving the Problems] The analog circuit according to the present invention has a first input terminal to which an analog input signal is input, and a second input terminal that functions differentially with respect to the first input terminal.
It has an input terminal and an output terminal, and a DC offset compensation circuit is connected between the output terminal and the second input terminal. a converter that outputs a positive and negative binary value according to the output, an integrator that integrates the output of this converter,
It consists of a sample-and-hold circuit that samples the output of this integrator at a frequency and number of cycles lower than the frequency of the analog input signal and holds it.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. As shown in the figure, the analog signal input to the input terminal 1 is taken out from the output terminal 3 via the amplifier circuit 2 composed of switches 21, 22, capacitors 23, 24, and operational amplifier 25. The output terminal 3 receives the output of the amplifier circuit 2 and outputs either ``'1'' or '' depending on the positive or negative of the output.
An A/D conversion circuit 4 that outputs ``o'' is connected, and an output 9 of this A/D conversion circuit 4 is latched by a latch circuit 5. An output 10 of the latch circuit 5 is taken into a switching circuit 6. , switches the contacts of the switch 63 to the positive power supply voltage 61 or negative power supply voltage 62 side according to the value of the output 10.The positive and negative outputs of the switching circuit 6 are composed of switches 71, 72, capacitors 82, 83, and operational amplifier 75. The output 11 of the integrator 7 is input to the non-inverting input terminal of the operational amplifier 25 via the sample-and-hold circuit 8 consisting of a switch 81 and capacitors 82 and 83.Switches 21 and 22 .71.72 and the latch circuit 5 are driven by a clock φ1 having a higher frequency than the analog input signal, and the switch 81 is driven by a clock φ2 having a lower frequency than the analog input signal.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to FIG. 2. Assume now that the analog input signal shown in FIG. 2(c) is applied to input terminal 1. If offset compensation is not performed on this input signal, an output containing an offset as shown in FIG. 2(d) will be obtained. This signal is converted into "1" or "0" by the A/D conversion circuit 4 depending on the positive or negative voltage, as shown in FIG. 2(e).
′ is converted into a digital signal. The output of the A/D conversion circuit 4 is taken into the latch circuit 5 at the cycle of the clock φl shown in FIG. 2(a), and the output of the latch circuit shown in FIG. The switch 63 of the switching circuit 6 is switched to the positive power supply voltage 61 or the negative power supply voltage 62.The output of the switching circuit 6 is taken into the integrator 7 at the timing of clock φl and integrated, and the output is shown in FIG. 2(g). The voltage is sampled by the sample-and-hold circuit 8 at the timing of clock φ2 and input to the non-inverting input terminal of the operational amplifier 25. As a result, this voltage is subtracted from the analog input signal, and the output waveform of the output terminal 3 is The result is shown in Fig. 2 (h).By repeating such a process, the DC offset voltage of the amplifier circuit 2 can be automatically compensated.Here, the loop gain of the compensation circuit and the amplifier circuit 2 can be automatically compensated. If is made sufficiently large, the DC offset can be made substantially negligible.

Furthermore, in this embodiment, the reason why the sample-and-hold circuit driven by the clock φ2 is provided between the integrator 7 and the amplifier circuits 2 and 4 is to keep the amount subtracted from the input signal constant for a certain period of time. This is because a stable output signal can be obtained.

FIG. 3 is a circuit diagram showing another embodiment of the present invention. In the figure, parts similar to those in the embodiment of FIG. 1 are given the same symbols. This embodiment is different from the previous embodiments in that the amplifier circuit 2 includes an operational amplifier 25 and a resistor 26.
．． 27. In the previous embodiment, the amplifier circuit 2 was configured to handle discrete analog signals using switches and capacitors, but the present invention can also handle continuous waveforms in the same way as in this embodiment. , this embodiment can also produce the same effects as described in the previous embodiment.

In the above embodiments, the analog circuit is an amplifier circuit, but the present invention is not limited to this, and can be applied to analog circuits such as filter circuits using operational amplifiers. It's Chino.

[Effects of the Invention] As explained above, the present invention compensates for offsets in analog circuits using an offset compensation circuit including an integrating circuit. Time division eliminates the need to set a DC offset compensation signal generation period, and the DC offset can be compensated with a simple circuit.

1...Input terminal, 2...Amplification circuit, 3...
・Output terminal, 4... A/D conversion circuit, 5...
・Latch circuit, 6...Switching circuit, 7...Integrator, 8...Sample and hold circuit, 9.
...Conversion circuit output, 10...Latch circuit output,
11... Integrator output, 21.22.63.7
1.72.81...Switch, 23.24.7
3.74.82.83...Capacitor, 61...Positive power supply voltage, 62...Negative power supply voltage, 26.27.
··resistance.

Claims (1)

[Claims] In an analog circuit having a first input terminal into which an analog input signal is input, and a second input terminal and an output terminal that function differentially, the output terminal and the second input terminal function differentially. An analog circuit having a DC offset compensation circuit, characterized in that a DC offset compensation circuit including an integrating circuit is connected between the terminal and the terminal.