KR950026125A

KR950026125A - Analog digital inverter

Info

Publication number: KR950026125A
Application number: KR1019940002659A
Authority: KR
Inventors: 박승우
Original assignee: 문정환; 금성일렉트론 주식회사
Priority date: 1994-02-15
Filing date: 1994-02-15
Publication date: 1995-09-18
Also published as: KR960003449B1

Abstract

본 발명은 아날로그 디지탈 변환장치에 관한 것으로, 입력 아날로그 신호의 표본값을 유지하는 심플링 홀더와, 기준전압을 형성하는 저항렬과, 각각의 비반전압단자(+)가 상기 저항렬의 각 노드와 연결되며, 각가의 반전압 입력단(-)는 상기 샘플링홀더와 연결되어 비교결과를 출력하는 비교기와, 상기 비교기로부터 신호를 인가받아 저장하여 클럭에 따라 출력하는 래치와, 상기 래치의 출력을 BCH 데이터로 변환시는 엔코더와, 상기 엔코더로부터 신호를 전송받아 필터링하는 디지털 필터와, 상기 디지털 필터로부터 출력되는 신호의 최대값과 최소값을 검출하는 검출기와, 상기 검출기에서 검출된 값에 따라 정해진 디지털 값을 출력하는 디코더와, 디코더로부터 출력되는 디지털 값을 아날로그로 변환시켜 상기 저항렬의 기준전압을 조절하는 디지털 아날로그 변환기와, 상기 각 부에 필요한 클럭을 공급하고 제어하는 클럭 제어기를 포함하여 구성되며, 아날로그 디지털 변환과 자동이득 조절을 동시에 할 수 있고, 아날로그 입력신호를 그대로 받아 대역변화없이 그 신호대역 내에서 직접 아날로그 디지털 변환 및 자동이득 조절을 수행하으로써 집적화가 용이하며, 시스템의 구성이 간단한 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog digital converter, comprising a simple holder for holding a sample value of an input analog signal, a resistor column forming a reference voltage, and each non-voltage terminal (+) being connected to each node of the resistor row. Each half voltage input terminal (-) is connected to the sampling holder and outputs a comparison result, a latch receiving a signal from the comparator, storing and outputting the signal according to a clock, and outputting the latch of the BCH data. Outputs an encoder, a digital filter for receiving and filtering a signal from the encoder, a detector for detecting maximum and minimum values of the signal output from the digital filter, and a digital value determined according to the detected value at the detector. And a digital converter for converting the digital value output from the decoder into an analog to adjust the reference voltage of the resistor string. It includes a analog converter and a clock controller for supplying and controlling the clock required for each unit, and can simultaneously perform analog-to-digital conversion and automatic gain adjustment, and receive analog input signals as they are without changing the band. Analog-to-digital conversion and automatic gain control are performed directly in the system for easy integration, and the system configuration is simple.

Description

Analog to digital inverter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 의한 아날로그 디지털 변환장치의 회로도.3 is a circuit diagram of an analog-to-digital converter according to the present invention.

제4도는 제3도의 아날로그 디지털 변환 특성도.4 is an analog-digital conversion characteristic diagram of FIG.

Claims

A sampling holder 1 for holding a sample value of an input analog signal, a resistor string 2 forming a reference voltage, and each non-inverting input terminal (+) are connected to each node of the resistor string 2; Each of the inverting input terminals (-) is connected to the sampling holder (1) and compares the input signal and outputs a comparison result, and receives a signal from the comparator (3) and stores it according to a clock. A latch 4 to output, an encoder 5 for converting the output of the latch 4 into BCH data, a digital filter 9 for receiving and filtering a signal from the encoder 5, and the digital filter ( A detector 10 for detecting a maximum value and a minimum value of a signal output from 9), and a decoder 11 for outputting a digital value determined according to the value detected by the detector 10 and a digital output from the decoder 11. Convert the value to analog to adjust the reference voltage of the resistor row 2 Digital-to-analog converter (6, 7) and, an analog-to-digital converter, characterized in that configured by a clock controller 8 for supplying and controlling the clock required for the respective parts to.

※ Note: The disclosure is based on the initial application.