JPH02266714A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To prevent harmful switching noise from generation by providing a current limitation circuit to moderate the change of the current value of an operating signal when the state of a high impedance setting circuit is changed. CONSTITUTION:In the high impedance setting circuit consisting of transistors 13 and 14, a CMOS transmission gate 19, and current sources 6 and 16, the transmission gate 19 is turned off when the operating signal Hz is switched to an H level, and the transistors 13 and 14 are turned on, and current supply from the current sources 6 and 16 are started, and transistors 3 and 4 are switched to turn off gradually. At such a case, it is possible to adjust a time to change the high impedance setting circuit to high impedance by adjusting the current sources 6 and 16 and capacity of a mirror capacitor 2 appropriately, and to moderate the falling speed of a waveform outputted from an output terminal 5. Thereby, the generation of noise due to the steep change of the waveform can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an output buffer circuit composed of a CMOS inverter that drives transmission lines and pass lines on a PC board, in particular.

(Prior Art) Conventionally, an output buffer circuit has generally been constructed of a CMOS inverter, and as shown in FIG. There is.

In this output buffer circuit, the input signal applied to the input end is output from the output end 5, but the waveform of the output signal obtained is not necessarily an ideal waveform, and in reality there is overshoot during switching. Noise is generated due to distortion and reflection in transmission lines. Therefore, when this output buffer circuit is used for pulse transmission, it becomes a source of electromagnetic wave noise, which interferes with AM and FM reception during transmission in a vehicle, for example.

Furthermore, even when used to drive a pass line within a unit, if there is a leakage path from the unit, it will similarly cause noise in radio reception.

Therefore, various methods for suppressing the switching noise generated in the output stage have been proposed as logic circuits become faster.

As an example, Japanese Patent Application Laid-Open No. 152125/1983 describes a method of connecting a capacitor 2 of a suitable capacity between the input and output of a CMOS inverter to blunt the output waveform, as shown in FIG.

Furthermore, as shown in FIG. 7, a method for accurately controlling the output waveform by providing current sources 6 and 16 in the inverter 1 has already been filed by the present applicant in Japanese Patent Application No. 63-272462.

Let us consider a case where two-way communication is performed using these output buffer circuits as shown in FIG.

In the illustrated example, in order to transmit and receive data, the following two requirements must be met.

First, in order to ensure contact between the connectors 9 and 19, a pull-down resistor 10, 20 or a pull-up resistor must be provided on the outside of the connectors, respectively, and a current must flow to the ground side.

Secondly, the output of the output buffer circuit 7 must be placed in a high impedance state at any time so as not to affect other transmissions.

In order to make the output buffer circuit 7 high impedance, which is the second requirement, as shown in FIG.
．． This can be easily realized by providing 24.

(Problem to be Solved by the Invention) However, in the illustrated example described above, when unit A and unit B communicate, there is no problem if they are synchronized with each other, but a problem occurs if they are asynchronous. For example, unit B
has priority over unit A, and if unit A changes to a high impedance state at an arbitrary time point to while outputting an H level signal as shown in Figure 10, the output waveform from unit A will change. Because of the resistor 10, the voltage falls rapidly as shown in the figure, which may cause switching noise.

This problem of noise generation is also the same when driving the second pass line of the PC board.

In this way, a C with a conventional high impedance setting circuit
Output buffer circuits made of MOS inverters generate switching noise when set to high impedance, so if these output buffer circuits are installed in a vehicle, they may cause problems such as interfering with AM or FM radio reception. be.

(Object of the Invention) This invention was made to solve the above problem, and its purpose is to connect a capacitor between the input and output of a CMOS inverter, and to connect the above CMOS inverter as a high impedance setting circuit. To provide a highly reliable output buffer circuit which prevents generation of harmful switching noise when setting a high impedance in an output buffer circuit formed by connecting MOS transistors to the power supply side and ground side of a.

(Means for Solving the Problems) In order to achieve the above object, the present invention connects a capacitor between the input and output of a CMOS inverter, and also puts the CMOS inverter in an active state when an operating signal is input. In an output buffer circuit having a high impedance setting circuit made up of a pair of MOS transistors that puts the high impedance state into a high impedance state when no human power is applied, the current limiting circuit slows down the change in the current value of the operating signal when the state of the high impedance setting circuit changes. It is characterized by having the following.

(Function) In this invention, when an operating signal is input to the high impedance and setting circuit, the CMOS inverter becomes active, and the input signal waveform is distorted by the capacitor connected between the input and output of the CMOS inverter. When no operating signal is input to the high impedance setting circuit, the CMOS inverter enters a high impedance state, and the input and output of the CMOS inverter are electrically isolated and the input signal is not output.

Here, when the operating signal is changed to invert the operating state of the high impedance setting circuit, the current value of the operating signal input to the high impedance setting circuit is gradually increased or decreased by the current limiting circuit, and as a result, The inversion operation of the operating state of the high impedance setting circuit is also slowed down, and a sudden change in the waveform of the signal output from the output buffer circuit is avoided.

(Example) Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of an output buffer circuit according to the present invention.

In this embodiment, as shown in the figure, inverters 1°11,
P-channel transistor 3. 13. N channel・
Transistor 4.14. A well-known output buffer circuit consisting of a Miller capacitor 2 and the like is provided with a 6MO3 transmission gate 19 and a pair of current sources 6.16.

P-channel transistor 13 above. N-channel transistor 14. A high impedance setting circuit consisting of a CMO8 transmission gate 19 and current sources 6 and 16 is
Controlled by an operating signal Hz.

Next, the operation of this output buffer circuit will be explained with reference to the signal waveform diagram of FIG.

While the operating signal Hz applied to the high impedance setting circuit is at L level, the transmission gate 19 is ON and the transistors 13 and 14 are OFF, so the input signal applied to the input terminal is waveformed by the mirror φ capacitor 2. The signal is output to the output terminal 5 after being distorted.

Here, when the operation signal Hz is switched to H level,
The transmission gate 19 is turned off, electrically insulating the input terminal and the output terminal 5, and further transistor 13.1
4 is turned on, and current supply from the pair of current sources 6 and 16 is started. As the current is supplied from the current sources 6 and 16,
By gradually increasing or decreasing the voltage applied to the gate of transistor 3.4, transistors 3, 4 are also gradually switched off. Here, the speed of switching from ON to OFF is determined by the magnitude of the current supplied from the current sources 6 and 16, the capacitance of the Miller capacitor 2, and other gate capacitances. In other words, by appropriately adjusting the capacitance of the current sources 6 and 16 and the mirror capacitor 2, the time for the high impedance setting circuit to change to high impedance can be adjusted, and the waveform output from the output terminal 5 at the time of change can be adjusted. It becomes possible to slow down the speed at which the voltage falls from the H level to the L level.

As a result, it becomes possible to prevent the generation of noise caused by sudden waveform changes that conventionally occur when high impedance is set.

FIG. 2 is a circuit diagram showing a second embodiment of the invention.

This embodiment has an inverter 1.11 as shown in the figure.
, P-channel transistors 3, 23, N-channel transistors 4, 24, Miller capacitor 2, etc., are connected to an inverter 21.31, a current source 26.36, and a current source 46.56. This is what I did. The high impedance setting circuit composed of the above-mentioned P-channel transistor 23, N-channel transistor 24, current source 26.36, and current source 46.56 is controlled by the operating signal Hz.

In this embodiment, as in the first embodiment, while the operating signal Hz given to the high impedance setting circuit is at L level, transistors 23 and 24 are turned on and transistor 3 is turned on.
, 4 becomes active, so
The input signal applied to the input terminal is outputted to the output terminal 5 after its waveform is blunted by the Miller capacitor 2.

When the operating signal H2 is switched to H level to create a high impedance state, the output of the inverter 21 gradually rises to the H level at a speed corresponding to the current value supplied from the current source 26. The voltage applied to the gate gradually increases, and the transistor 3 is gradually turned off. Similarly, the output of the inverter 31 gradually decreases to the L level at a speed corresponding to the current value supplied from the current source 56, so that the voltage applied to the gate of the transistor 24 gradually decreases, and the voltage of the transistor 4 gradually decreases. Switched to OFF. The speed of switching from ON to OFF is determined by the magnitude of the current supplied from current source 26.56 and the gate capacitance of transistors 23 and 24.

In other words, the current value of the current source 26.56 and the transistor 23
．． By appropriately adjusting the gate capacitance of 24, the time for the high impedance setting circuit to change to high impedance is adjusted, and if the waveform output from the output terminal 5 at the time of the change is at H level, It becomes possible to slow down the speed at which the signal falls from the L level to the L level.

As a result, it becomes possible to prevent the generation of noise caused by sudden waveform changes that conventionally occur when high impedance is set.

Similarly, when the operating signal Hz is changed from the H level to the L level, the outputs of the inverters 21.31 are gradually switched at a speed corresponding to the current value supplied from the current sources 36.46. When the transistors 3 and 4 are gradually turned on and the waveform input to the input terminal is at H level, it is possible to prevent the waveform from rising suddenly when output from the output terminal 5 is started.

In this embodiment, when it is not necessary to smooth out a sudden change in the waveform when canceling the high impedance, the current source 36.36 connected to the inverter 21.31 is used.
It is also possible to omit 46.

FIG. 4 is a circuit diagram showing a third embodiment of the invention.

As shown in the figure, this embodiment has a CMO3 transmission gate 19 inserted at the input end of the Miller capacitor 2 in the second embodiment as part of a high impedance setting circuit, and is used to set and release high impedance. The actual operation and effects are the same as in the second embodiment, so detailed explanations will be omitted.

In these embodiments, in a high impedance setting circuit of an output buffer circuit consisting of a CMOS inverter, the operating speed of the MOS transistor constituting the setting circuit is set to a low current value of the current source to set or cancel the high impedance. By making it possible to set the output waveform at any slope, it is possible to eliminate the noise that conventionally occurs when setting or canceling high impedance. As a result, even if a pull-down resistor or pull-up resistor is connected when installing an output buffer circuit consisting of a CMOS inverter in a vehicle, it will not interfere with receiving the same AM or FM radio.

(Effects) As described above, the present invention provides a current limiter that slows down the change in the current value of an operating signal when switching between activation and release of the high impedance setting circuit in an output buffer circuit consisting of a CMOS inverter equipped with a high impedance setting circuit. With this circuit, when the operating signal is changed and the operating state of the high impedance setting circuit is about to be reversed, the current value of the operating signal input to the high impedance setting circuit is gradually increased by the current limiting circuit. Or, by decreasing it, the operation of inverting the state of the high impedance setting circuit also becomes slow, and rapid waveform deformation of the signal output from the output buffer circuit is avoided.

As a result, the electromagnetic noise that previously occurred is eliminated,
Even when this type of output buffer circuit is used in a vehicle or the like, the effect of achieving good radio reception can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the output buffer circuit according to the present invention, FIG. 2 is a circuit diagram also showing the second embodiment, FIG. 3 is a signal waveform diagram showing the operation, and FIG. 4 is a circuit diagram showing the second embodiment. The circuit diagram of the third embodiment, Figure 5.6.7 is a circuit diagram showing a conventional output buffer circuit, Figure 8 is a circuit diagram showing an example of use of the conventional output buffer circuit, and Figure 9 is a circuit diagram showing a conventional output buffer circuit. FIG. 10, a circuit diagram showing a buffer circuit, is a waveform diagram of a signal output from a conventional output buffer circuit. 1.11, 21.31... Inverter 2... Miller capacitor 3.13.23... P-channel transistor 4.1
4.24...N-channel transistor 5...Output terminal 6, 16.26. 36.46. 56...Current source 19...CMO8 transmission gate D...Input terminal

Claims (1)

[Claims] 1. A high impedance setting circuit consisting of a pair of MOS transistors that connects a capacitor between the input and output of the CMOS inverter, and puts the CMOS inverter into an active state when an operating signal is input, and puts it into a high impedance state when no operating signal is input. An output buffer circuit comprising: a current limiting circuit that slows down the change in current value of the operating signal when the state of the high impedance setting circuit changes.