JP2003110418A - Output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output circuit which selectively outputs a plurality of output signals different in amplitude at a desired operating speed without deterioration of the reliability. SOLUTION: The output circuit comprises a first and second output buffer circuits 13, 14 for outputting output signals S1 , S2 different in amplitude, and an output switching circuit 20 which selects either of the first or second buffer circuits 13, 14 to output the signal S1 , S2 from the selected buffer circuit 13, 14 to an external output terminal 3. Besides, the circuit 20 cuts off a signal path between output ends 31, 32 of the first and second buffer circuits 13, 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit, and more specifically, it is provided between an internal circuit and an external output terminal.
The present invention relates to an output circuit used as an interface when outputting an output signal of an internal circuit to an external output terminal.

[0002]

2. Description of the Related Art Generally, semiconductor integrated circuits (hereinafter referred to as LSI
Is required to output a signal having a logical amplitude suitable for an externally connected circuit. Therefore, the LSI is provided with an interface output circuit for converting an output signal from the internal circuit into a predetermined logical amplitude.

In recent years, as a bus standard for realizing high-speed data transfer between a main memory and a graphics accelerator, a frequency 66 has been adopted.
MHz / logic amplitude 3.3V operation mode and frequency 133
There is an operation mode of MHz / logical amplitude of 1.5V. Therefore, in order to adapt to both of these two operation modes, conventionally, there is an output circuit that outputs two output signals having different logic amplitudes to one external output terminal. An example thereof is shown in FIG.

The conventional output circuit of FIG. 4 has a logic amplitude of 3.3.
A first output buffer circuit 113 that generates and outputs a V output signal, a second output buffer circuit 114 that generates and outputs an output signal with a logical amplitude of 1.5 V, and an inverter 112 for mode control signal inversion. I have it.

The first output buffer circuit 113 is a NAND
A pre-driver 104 having a gate 121 and a NOR gate 122, and two level shift circuits 115 and 116.
And p-channel field effect transistor 106 for driver
And n-channel field effect transistor 107 for driver
Composed of and. The transistors 106 and 107 are
It functions as an output transistor of the first output buffer circuit 113.

NAND gate 12 of pre-driver 104
Of the two input terminals 1, one is connected to the internal input terminal 101 that functions as an input terminal of the output circuit, and the other is connected to the mode control terminal 102 of the output circuit. The output terminal of the NAND gate 121 is connected to the gate of the transistor 106 via the level shift circuit 115.

NOR gate 122 of pre-driver 104
One of the two input terminals is connected to the internal input terminal 101, and the other is connected to the mode control terminal 102 via the inverter 112. The output terminal of the NOR gate 122 is connected to the gate of the transistor 107 via the level shift circuit 116.

The source and drain of the transistor 106 are connected to the first power supply line of the power supply voltage V _DD1 (= 3.3 V) and the drain of the transistor 107, respectively.
The mutually connected drains of the transistors 106 and 107 form the output terminal 131 of the first output buffer circuit 113, and are connected to the external output terminal 103 of the output circuit. The source of the transistor 107 is grounded.

The second output buffer circuit 114 is a NAND
It is composed of a pre-driver 105 having a gate 123 and a NOR gate 124, a driver p-channel field effect transistor 108, and a driver n-channel field effect transistor 109. The transistors 108 and 109 function as output transistors of the second output buffer circuit 114.

NAND gate 12 of pre-driver 105
One of the two input terminals 3 is the internal input terminal 101
, And the other is connected to the mode control terminal 102 via the inverter 112. NAND gate 121
The output terminal of is connected to the gate of the transistor 108.

NOR gate 124 of pre-driver 105
One of the two input terminals is connected to the internal input terminal 101, and the other is connected to the mode control terminal 102. The output terminal of the NOR gate 124 is the transistor 1
09 gate.

The source and drain of the transistor 108 are connected to the second power supply line of the power supply voltage V _DD2 (= 1.5 V) and the drain of the transistor 109, respectively.
The mutually connected drains of the transistors 108 and 109 form the output terminal 132 of the second output buffer circuit 114 and are connected to the external output terminal 103. The source of the transistor 109 is grounded.

An internal input terminal 101 is supplied with an output signal (logic amplitude 2.5V) of an internal circuit (not shown) as an input signal S _IN to the output circuit. Thereby, N
AND gates 121 and 123 and NOR gates 122 and 1
The input signal S _IN is input to 24.

The mode control terminal 102 has a frequency of 66M.
A mode control signal S _MC (logic amplitude 2.5 V) indicating which of the operation modes, Hz / logic amplitude 3.3 V and frequency 133 MHz / logic amplitude 1.5 V, is supplied from the internal circuit. As a result, the NAND gate 121 and the NO
The mode control signal S _MC is input to the R gate 124 and NO
An inverted signal of the mode control signal S _MC is input to the R gate 122 and the NAND gate 123.

From the external output terminal 103, an external output signal S _OUT having a different logic amplitude is output according to the operation mode indicated by the mode control signal S _MC .

The operation of the conventional output circuit of FIG. 4 will be described as follows.

In the operation mode of frequency 66 MHz / logic amplitude 3.3 V, the mode control signal S _MC of logic high level (hereinafter referred to as H level) is supplied to the mode control terminal 102. As a result, the first output buffer circuit 113 operates and the external output signal S _OUT having a logical amplitude of 3.3 V is output from the external output terminal 103.

That is, in the pre-driver 104 of the first output buffer circuit 113, an H level signal is input to the NAND gate 121 and a logical low level (hereinafter referred to as L level) signal is input to the NOR gate 122. Therefore, each of the NAND gate 121 and the NOR gate 122 outputs an inverted signal of the input signal S _IN to the level shift circuits 115 and 116. Each of the level shift circuits 115 and 116 level-adjusts the output signals of the NAND gate 121 and the NOR gate 122 to output an output signal of logic amplitude 3.3V to the transistors 106 and 107.
Output to the gate of. And the transistors 106, 1
07 inverts the output signals of the level shift circuits 115 and 116, generates an output signal S ₁ having a logical amplitude of 3.3 V according to the power supply voltage V _DD1 , and outputs the output signal S ₁ from the output terminal 131. This output signal S ₁ has the logical amplitude of the input signal S _IN of 2.5V.
To 3.3V.

On the other hand, in the pre-driver 105 of the second output buffer circuit 114, an L level signal is input to the NAND gate 123 and an H level signal is input to the NOR gate 124. Therefore, the NAND gate 123
Outputs a signal fixed at the H level to the gate of the transistor 108, and the NOR gate 124 outputs a signal fixed at the L level to the gate of the transistor 109. As a result, the transistors 108 and 109 are both turned off, and the output of the second output buffer circuit 114 is stopped.

In this way, the output signal S ₁ (logic amplitude 3.3 V) of the first output buffer circuit is output to the external output terminal 103 and taken out as the external output signal S _OUT .

In the operation mode of frequency 133 MHz / logical amplitude 1.5 V, the mode control terminal 102 is supplied with the mode control signal S _MC of L level. Thereby, contrary to the operation mode of frequency 66 MHz / logic amplitude 3.3 V, the second output buffer circuit 114 operates to output the external output signal S _OUT having the logic amplitude of 1.5 V to the external output terminal 103.
Is output from.

That is, in the pre-driver 105 of the second output buffer circuit 114, an H level signal is input to the NAND gate 123 and an L level signal is input to the NOR gate 124. Therefore, NAND gate 1
23 and NOR gate 124 each have an input signal S _IN
The inverted signal of is output to the gates of the transistors 108 and 109. The transistors 108 and 109 have NA
The output signals of the ND gate 123 and the NOR gate 124 are inverted to generate an output signal S ₂ having a logical amplitude of 1.5 V according to the power supply voltage V _DD2 and output from the output terminal 132.
This output signal S ₂ has a logic amplitude of the input signal S _IN of 2.5.
This corresponds to the one adjusted from V to 1.5V.

On the other hand, in the pre-driver 104 of the first output buffer circuit 113, an L level signal is input to the NAND gate 121 and an H level signal is input to the NOR gate 122. Therefore, the NAND gate 121
Is a level shift circuit 115 for a signal fixed at H level.
Output to the gate of the transistor 106 via
The gate 122 outputs a signal fixed at the L level to the gate of the transistor 107 via the level shift circuit 116. As a result, both the transistors 106 and 107 are turned off, and the output of the first output buffer circuit 113 is stopped.

In this way, the output signal S ₂ (logic amplitude 1.5 V) of the second output buffer circuit is output to the external output terminal 103 and taken out as the external output signal S _OUT .

[0025]

The conventional output circuit of FIG. 4 has the following problems.

The output terminal 13 of the output signals S ₁ of logic amplitude 3.3V is generated at the first output buffer circuit 113, the output signal S ₁ is the second output buffer circuit 114
2 is applied. As a result, the second output buffer circuit 11
The maximum voltage of 3.3 V is applied between the drain and the gate of the transistors 108 and 109 of No. 4 and between the drain and the source. Therefore, in order to prevent the withstand voltage failure, it is necessary to use the transistors 108 and 109 of the second output buffer circuit 114 that have the same withstand voltage of 3.3 V as the transistors 106 and 107 of the first output buffer circuit 113. is there.

Generally, when the withstand voltage performance of a transistor is increased, the operating speed of the transistor tends to decrease.
That is, the operating speed of a transistor having a withstand voltage of 3.3V is significantly lower than that of a transistor having a withstand voltage of 1.5V. Therefore, in the conventional output circuit of FIG. 4, there is a problem that the operation speed of the second output buffer circuit 114 that generates the output signal S ₂ having the logical amplitude of 1.5 V is reduced, and high speed operation cannot be realized.

If transistors having a withstand voltage of 1.5 V are used as the transistors 108 and 109 of the second output buffer circuit 114, high speed operation of the second output buffer circuit 114 is ensured. However, in that case, there is a problem that the withstand voltage defect of the second output buffer circuit 114 increases, and the reliability decreases.

Therefore, an object of the present invention is to provide an output circuit capable of selectively outputting a plurality of output signals having different amplitudes and capable of high-speed operation while preventing withstand voltage failure.

Another object of the present invention is to provide an output circuit capable of selectively outputting a plurality of output signals having different amplitudes at a desired operation speed while preventing a decrease in reliability.

Other objects of the invention not specified here will be apparent from the following description.

[0032]

(1) An output circuit of the present invention is provided between an internal circuit and an external output terminal, and serves as an interface for outputting an output signal of the internal circuit to the external output terminal. In the output circuit used,
A plurality of output buffer circuits that receive an output signal of the internal circuit and output each of a plurality of output signals having different amplitudes, and select one of the plurality of output buffer circuits, and select the selected output. An output switching circuit for outputting the output signal of the buffer circuit to the external output terminal, wherein the output switching circuit goes from the output terminal of the selected output buffer circuit to the output terminal of the unselected output buffer circuit. The feature is that the signal path is blocked.

(2) In the output circuit of the present invention, the output switching circuit selects any one of the plurality of output buffer circuits which outputs each of the plurality of output signals having different amplitudes, and the selection thereof. The output signal of the selected output buffer circuit is output to the external output terminal, and the signal path from the output terminal of the selected output buffer circuit to the output terminal of the unselected output buffer circuit is cut off.

Therefore, a plurality of output signals having different amplitudes can be selectively taken out from the external output terminal.
Moreover, the output signal of the output buffer circuit output to the external output terminal is not applied to the output terminal of the output buffer circuit that does not output it. This means that each of the output buffer circuits can be designed with a withstand voltage performance according to the amplitude of its output signal.

Therefore, it is possible to solve the problems such as the decrease in the operation speed and the increase in the withstand voltage failure, which are caused in the above-described conventional output circuit. That is, a plurality of output signals having different amplitudes can be selectively output, and high-speed operation can be performed while preventing defective withstand voltage. Therefore, it is possible to selectively output a plurality of output signals having different amplitudes at a desired operation speed while preventing a decrease in reliability.

(3) In a preferred example of the output circuit of the present invention, each of the plurality of output buffer circuits includes an output transistor having a withstand voltage performance according to the amplitude of its output signal. In this case, in each of the plurality of output buffer circuits, there is an advantage that the maximum operating speed can be obtained while preventing the withstand voltage failure.

In another preferred example of the output circuit of the present invention,
Each of the plurality of output buffer circuits is configured to turn off the output transistor when not selected by the signal switching circuit. In this case, there is an advantage that an unnecessary current path can be prevented from being formed via the output transistor of the output buffer circuit which is not selected.

In still another preferred example of the output circuit of the present invention, the signal switching circuit includes a plurality of switch elements provided between each of the output terminals of the plurality of output buffer circuits and the external output terminal. Composed of.

In still another preferred example of the output circuit of the present invention, each of the plurality of switch elements is a field effect transistor.

In still another preferred example of the output circuit of the present invention, each of the plurality of switch elements comprises a transfer gate composed of a pair of complementary field effect transistors.

[0041]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

(First Embodiment) FIG. 1 is a circuit diagram showing a configuration of an output circuit according to a first embodiment of the present invention.

The output circuit of FIG. 1 is a first output buffer circuit 13 for generating and outputting an output signal having a logical amplitude of 3.3V.
A second output buffer circuit 14 for generating and outputting an output signal having a logical amplitude of 1.5 V, an output switching circuit 20, an inverter 12 for inverting the mode control signal, and a level shift circuit 19.

The first output buffer circuit 13 includes a pre-driver 4 having two inverters 21 and 22, two level shift circuits 15 and 16, a driver p-channel field effect transistor 6, and a driver n-channel field effect. And a transistor 7. Each of the transistors 6 and 7 has a withstand voltage performance of 3.3V,
It functions as an output transistor of the first output buffer circuit 13.

Each of the input terminals of the inverters 21 and 22 of the pre-driver 4 is connected to the internal input terminal 1 which functions as the input terminal of the output circuit. Inverter 21
The output terminal of is connected to the gate of the transistor 6 via the level shift circuit 15. The output terminal of the inverter 22 is connected to the gate of the transistor 7 via the level shift circuit 16.

The source and drain of the transistor 6 are connected to the first power supply line of the power supply voltage V _DD1 (= 3.3 V) and the drain of the transistor 7, respectively. The drains of the transistors 6 and 7 connected to each other form the output terminal 31 of the first output buffer circuit 13. The source of the transistor 7 is grounded.

The second output buffer circuit 14 includes a pre-driver 5 having two inverters 23 and 24, two level shift circuits 17 and 18, a driver p-channel field effect transistor 8 and a driver n-channel field effect. And a transistor 9. Each of the transistors 8 and 9 has a withstand voltage performance of 1.5 V,
It functions as an output transistor of the second output buffer circuit 14.

Each of the input terminals of the inverters 23 and 24 of the pre-driver 5 is connected to the internal input terminal 1.
The output terminal of the inverter 23 is connected to the gate of the transistor 8 via the level shift circuit 17. The output terminal of the inverter 24 is connected to the gate of the transistor 9 via the level shift circuit 18.

The source and the drain of the transistor 8 are connected to the second power supply line of the power supply voltage V _DD2 (= 1.5 V) and the drain of the transistor 9, respectively. The mutually connected drains of the transistors 8 and 9 form the output terminal 32 of the second output buffer circuit 14. The source of the transistor 9 is grounded.

The output switching circuit 20 is composed of two n-channel field effect transistors 10 and 11 which respectively function as switching elements. Each of these transistors 10 and 11 has a withstand voltage performance of 3.3V, and the threshold voltage _Vth of each of the transistors 10 and 11 is set to "0V".

The drain and source of the transistor 10 are
The output terminal 31 of the first output buffer circuit 13 and the external output terminal 3 are respectively connected. The gate of the transistor 10 is connected to the mode control terminal 2 via the level shift circuit 19.

The drain and source of the transistor 11 are
The output terminal 32 of the second output buffer circuit 14 and the external output terminal 3 are respectively connected. The gate of the transistor 11 is connected to the mode control terminal 2 via the inverter 12.

An output signal (logic amplitude 2.5 V) of an internal circuit (not shown) is supplied to the internal input terminal 1 as an input signal S _IN to the output circuit. As a result, the input signal S _IN is input to the inverters 21, 22, 23, 24.

The mode control terminal 2 has a frequency of 66 MHz.
A mode control signal S _MC (logic amplitude 2.5V) indicating which one of the operation modes of / logic amplitude 3.3V and frequency 133MHz / logic amplitude 1.5V is supplied from the internal circuit. Thereby, the mode control signal S _MC to the gate of the transistor 10 of the output switching circuit 20 is inputted, the inverted signal of the gate to the mode control signal S _MC of the transistor 11 of the output switching circuit 20 is input.

From the external output terminal 3, the mode control signal S
_An external output signal S _OUT having a different logical amplitude is output according to the operation mode indicated by _MC .

Next, the operation of the output circuit of the first embodiment shown in FIG. 1 will be described.

The first output buffer circuit 13 receives the input signal S
_An output signal S ₁ generated by adjusting the logical amplitude of _IN from 2.5 V to 3.3 V is generated and output from the output terminal 31.

That is, when the input signal S _IN is input to each of the inverters 21 and 22 in the pre-driver 4 of the first output buffer circuit 13, each of the inverters 21 and 22 outputs the inverted signal of the input signal S _IN as a level. Shift circuit 1
Output to 5 and 16. The level shift circuits 15 and 16 level-adjust the output signals of the inverters 21 and 22, respectively, and output the output signals having a logical amplitude of 3.3 V to the transistors 6 and 7.
Output to the gate of. The transistors 6 and 7 are
The output signals of the level shift circuits 15 and 16 are inverted to generate an output signal S ₁ having a logical amplitude of 3.3 V according to the power supply voltage V _DD1 and output from the output terminal 31.

The second output buffer circuit 14 receives the input signal S
_An output signal S ₂ obtained by adjusting the logical amplitude of _IN from 2.5 V to 1.5 V is generated and output from the output terminal 32.

That is, in the pre-driver 5 of the second output buffer circuit 14, when the input signal S _IN is input to each of the inverters 23 and 24, each of the inverters 23 and 24 sets the level of the inverted signal of the input signal S _IN. Shift circuit 1
Output to 7 and 18. Each of the level shift circuits 17 and 18 level-adjusts the output signals of the inverters 23 and 24, and outputs the output signals having a logical amplitude of 1.5 V to the transistors 8 and 9.
Output to the gate of. And the transistors 8 and 9 are
The output signals of the level shift circuits 17 and 18 are inverted to generate an output signal S ₂ having a logical amplitude of 1.5 V according to the power supply voltage V _DD2 and output from the output terminal 32.

The output switching circuit 20 uses the mode control signal S _MC.
Select one of the first and second output buffer circuits 13 and 14 according to the operation mode indicated by, and output signals S ₁ and S _{2 of the} selected first or second output buffer circuit 13 and 14 are selected. Is output to the external output terminal 3.

That is, in the operation mode of frequency 66 MHz / logic amplitude 3.3 V, the mode control signal S _MC of logic high level (hereinafter referred to as H level) is supplied to the mode control terminal 2. As a result, H of logical amplitude 2.5V
The level signal is the level shift circuit 19 and the inverter 12
Entered in.

The level shift circuit 19 adjusts the level of the mode control signal S _MC and outputs an H level signal having a logical amplitude of 3.3 V to the gate of the transistor 10 of the output switching circuit 20. Therefore, the transistor 10 is turned on, and the signal path from the output terminal 31 of the first output buffer circuit 13 to the external output terminal 3 is turned on. As a result, the output signal S _{1 of} the first output buffer circuit 13 (logic amplitude 3.3 V) is output to the external output terminal 3.

On the other hand, the inverter 12 inverts the mode control signal S _MC and outputs a signal of logic low level (hereinafter referred to as L level) to the gate of the transistor 11 of the output switching circuit 20. Therefore, the transistor 11 is turned off, and the signal path from the output terminal 32 of the second output buffer circuit 14 to the external output terminal 3 is turned off.
Therefore, the output signal S _{2 of} the second output buffer circuit 14 is
(Logical amplitude 1.5 V) is not output to the external output terminal 3. Further, the output terminal 31 of the first output buffer circuit 13
The signal path from the output terminal to the output terminal 32 of the second output buffer circuit 14 is also cut off.

In this way, the output signal S ₁ (logic amplitude 3.3 V) of the first output buffer circuit 13 is taken out from the external output terminal 3 as the external output signal S _OUT .

In the operation mode having a frequency of 133 MHz / logical amplitude of 1.5 V, the mode control signal S _MC of L level is supplied to the mode control terminal 2. As a result, the L level signal is input to the level shift circuit 19 and the inverter 12.

The inverter 12 inverts the mode control signal S _MC and outputs an H level signal having a logical amplitude of 2.5 V to the gate of the transistor 11 of the output switching circuit 20. Therefore, the transistor 11 is turned on, and the signal path from the output terminal 32 of the second output buffer circuit 14 to the external output terminal 3 is turned on. As a result, the output signal S _{2 of} the second output buffer circuit 14 (logical amplitude 1.5 V) is output to the external output terminal 3.

On the other hand, the level shift circuit 19 outputs an L level signal to the gate of the transistor 10 of the output switching circuit 20. Therefore, the transistor 10 is turned off, and the signal path from the output terminal 31 of the first output buffer circuit 13 to the external output terminal 3 is turned off. Therefore, the output signal S ₁ (logic amplitude 3.3V) of the first output buffer circuit 13 is not output to the external output terminal 3. Further, the signal path from the output terminal 32 of the second output buffer circuit 13 to the output terminal 31 of the first output buffer circuit 13 is also cut off.

In this way, the output signal S _{2 of} the second output buffer circuit 14 (logical amplitude 1.5 V) is taken out from the external output terminal 3 as the external output signal S _OUT .

As described above, in the output circuit of the first embodiment shown in FIG. 1, the output switching circuit 20 makes the mode control signal S
One of the first and second output buffer circuits 13 and 14 is selected according to the operation mode indicated by _MC, and the output signals S ₁ and S of the selected first or second output buffer circuit 13 and 14 are selected. ₂ is output to the external output terminal 3. Further, the output switching circuit 20 shuts off the signal path between the output terminal 31 of the first output buffer circuit 13 and the output terminal 32 of the second output buffer circuit 14.

Therefore, as the external output signal S _OUT , two output signals S ₁ and S ₂ having different amplitudes can be selectively taken out from the external output terminal 3. Moreover, even if the output signal S ₁ having a large logical amplitude is output from the first output buffer circuit 13 to the external output terminal 3, the output signal S ₁ is not
It is not applied to the output terminal 32 of the output buffer circuit 14. Therefore, withstand voltage failure in the output transistors 8 and 9 having low withstand voltage performance is prevented.

As the output transistors 8 and 9 of the second output buffer circuit 14, transistors having low withstand voltage performance are used. This substantially means that high-speed transistors are used as the output transistors 8 and 9. Therefore, the second output buffer circuit 14 can operate at high speed.

Therefore, two output signals having different amplitudes can be selectively output, and high speed operation can be performed while preventing a withstand voltage failure. Therefore, it is possible to selectively output two output signals having different amplitudes at a desired operation speed while preventing a decrease in reliability.

When a signal is transmitted between the source and drain of the n-channel field effect transistor, the maximum transmittable amplitude is reduced by the threshold voltage. However, the threshold voltage of the transistors 10 and 11 of the output switching circuit 20 is "0.
V ”, the output signals S ₁ and S _{2 of} the first or second output buffer circuits 13 and 14 are transmitted to the external output terminal 3 as they are, with almost no decrease in logic amplitude in the transistors 10 and 11. It

(Second Embodiment) FIG. 2 is a circuit diagram showing a configuration of an output circuit according to a second embodiment of the present invention.

The output circuit of FIG. 2 is different from the output circuit of the first embodiment of FIG. 1 except that predrivers 4A and 5A having NAND gates and NOR gates are provided in place of the predrivers 4 and 5. It has the same structure as. Therefore, in FIG. 2, the same components as those of the output circuit of the first embodiment are designated by the same reference numerals as those in FIG. 1, and the description thereof will be omitted.

In the output circuit of the first embodiment of FIG. 1 described above, when the threshold voltage V _{th of} the n-channel field effect transistors 10 and 11 functioning as switch elements changes (that is, shifts) in the negative direction, the transistor 1
It is conceivable that the transistors 10 and 11 are not sufficiently turned off even though the L level signal is applied to the gates of 0 and 11. In that case, an unnecessary current path from the external output terminal 3 to the ground may be formed.

For example, when the H level mode control signal S _MC is supplied to the mode control terminal 2, the input signal S _IN becomes L
The output terminal 32 of the second output buffer circuit 13 when the level is set
Becomes the L level, the transistor 11 having a negative threshold voltage V _th is turned on. At this time, the inverter 24 of the pre-driver 5 outputs the H-level output signal, so that the transistor 8 of the second output buffer circuit 13 is turned on. Therefore, a current path from the external output terminal 3 to the ground via the transistors 11 and 9 is formed. As a result, the desired output impedance cannot be obtained at the external output terminal 3.

Even when the H-level mode control signal S _MC is supplied to the mode control terminal 2, the external output terminal 3 passes through the transistors 10 and 7 from the external output terminal 3 when the input signal S _IN is at the L level in the same manner as described above. A current path to the ground is formed.

Therefore, in the output circuit of FIG. 2, when the output switching circuit 20 does not select the first output buffer circuit 13A, the transistors 6 and 7 are turned off, and when the second output buffer circuit 14A is not selected. The transistors 8 and 9 are configured to be turned off.

That is, in the output circuit of FIG. 2, the pre-driver 4A of the first output buffer circuit 13A has the NAND gate 41 and the NOR gate 42.

Of the two input terminals of the NAND gate 41 of the predriver 4A, one is connected to the internal input terminal 1 and the other is connected to the mode control terminal 2. NAN
The output terminal of the D gate 41 is connected to the input terminal of the level shift circuit 15.

Of the two input terminals of the NOR gate 42 of the predriver 4A, one is connected to the internal input terminal 1 and the other is connected to the mode control terminal 2 via the inverter 12. The output terminal of the NOR gate 42 is connected to the input terminal of the level shift circuit 16.

The pre-driver 5A of the second output buffer circuit 14A includes the NAND gate 43 and the NOR gate 4
4 and.

Of the two input terminals of the NAND gate 43 of the predriver 5A, one is connected to the internal input terminal 1 and the other is connected to the mode control terminal 2 via the inverter 12. The output terminal of the NAND gate 43 is connected to the input terminal of the level shift circuit 17.

Of the two input terminals of the NOR gate 44 of the predriver 5A, one is connected to the internal input terminal 1 and the other is connected to the mode control terminal 2. NOR
The output terminal of the gate 44 is connected to the input terminal of the level shift circuit 18.

Next, the operation of the output circuit of the second embodiment shown in FIG. 2 will be described.

In the output circuit of FIG. 2, when the mode control signal S _MC of H level is supplied to the mode control terminal 2 (that is, in the operation mode of frequency 66 MHz / logic amplitude 3.3 V), the second output buffer The transistors 8 and 9 of the circuit 13A are turned off.

That is, in the pre-driver 5A of the second output buffer circuit 14A, the N is output via the inverter 12.
The L level signal is input to the AND gate 43, and NOR
An H level signal is input to the gate 44. for that reason,
The NAND gate 43 outputs the signal fixed at the H level to the gate of the transistor 8 via the level shift circuit 17, and the NOR gate 44 outputs the signal fixed at the L level to the gate of the transistor 9 via the level shift circuit 18. Output to. As a result, the transistors 8 and 9 are both turned off, and the transistor 1
The formation of a current path through grounds 1, 9 to ground is prevented.

The first output buffer circuit 13A generates an output signal S ₁ having a logical amplitude of 3.3V according to the power supply voltage V _DD1 as in the case of the output buffer circuit 13 of the first embodiment shown in FIG. Output from the output terminal 32.

That is, in the pre-driver 4A of the first output buffer circuit 13A, an H level signal is input to the NAND gate 41 and an L level signal is input to the NOR gate 42 via the inverter 12. for that reason,
Each of the NAND gate 41 and the NOR gate 42 is
The inverted signal of the input signal S _IN is output to the gates of the transistors 6 and 7. The transistors 6 and 7 are NAND
The signals output from the gate 41 and the NOR gate 42 are inverted to generate an output signal S ₁ having a logic amplitude of 3.3 V according to the power supply voltage V _DD1 and output from the output terminal 31.

The output switching circuit 20 includes a first output buffer circuit 4A as in the case of the output circuit of the first embodiment shown in FIG.
The output signal S ₁ output from the output terminal 31 is output to the external output terminal 3 via the transistor 10 in the ON state.

On the other hand, when the L level mode control signal S _MC is supplied to the mode control terminal 2 (that is, the frequency 1
33MHz / logic amplitude 1.5V operation mode),
Contrary to the above operation, the transistors 6 and 7 of the first output buffer circuit 13A are turned off, and the external output terminal 3
The formation of a current path from the transistor to the ground via the transistors 10 and 7 is prevented. Then, as in the case of the output buffer circuit 13 of the first embodiment of FIG. 1, the second output buffer circuit 14A causes the logical amplitude of 1.5 in accordance with the power supply voltage V _DD2.
V output signal S ₂ is generated and output from the output terminal 32,
The output switching circuit 20 outputs the output signal S ₂ to the external output terminal 3 via the transistor 11 in the ON state.

Also in the output circuit of the second embodiment of FIG. 2, the same effect as that of the output circuit of the first embodiment of FIG. 1 can be obtained.

Further, in the output circuit of the second embodiment of FIG. 2, the transistors 10 and 1 functioning as switch elements are provided.
There is also an effect that it is possible to prevent an unnecessary current path from being formed due to the variation of the threshold voltage V _th of 1.

(Third Embodiment) FIG. 3 is a circuit diagram showing a configuration of an output circuit according to a third embodiment of the present invention.

The output circuit of FIG. 3 is similar to the output circuit of the first embodiment of FIG. 1 except that the output switching circuit 20 is replaced by transfer gates 51 and 52 of complementary field effect transistors.
In addition to providing the output switching circuit 20A configured by
A level shift circuit 53 is added. The other configuration is the same as that of the output circuit of the first embodiment. Therefore, in FIG. 3, the same components as those of the output circuit of the first embodiment are designated by the same reference numerals as those in FIG. 1, and the description thereof will be omitted.

The output circuit of FIG. 3 has two transfer circuits.
Output switching circuit 20A composed of gates 51 and 52
Is equipped with. These transfer gates 51, 5
2 respectively function as switch elements.

The transfer gate 51 includes an n-channel field effect transistor 54 and a p-channel transistor 5.
It is composed of 5. These transistors 54, 55
Have a withstand voltage performance of 3.3V. The drain and source of the transistor 54 are the same as those of the transistor 55.
Are connected to the source and drain of respectively. The mutually connected drains and sources of the transistors 54 and 55 are connected to the output terminal 31 of the first output buffer circuit 13. The sources and drains of the transistors 54 and 55, which are connected to each other, are connected to the external output terminal 3. The gate of the transistor 54 is connected to the mode control terminal 2 via the level shift circuit 19.
The gate of the transistor 55 is connected to the mode control terminal 2 via the inverter 12 and the level shift circuit 53.

The transfer gate 52 includes an n-channel field effect transistor 56 and a p-channel transistor 5.
It is composed of 7. These transistors 56, 57
Have a withstand voltage performance of 3.3V. The drain and source of the transistor 56 are the same as those of the transistor 57.
Are connected to the source and drain of respectively. The mutually connected drains and sources of the transistors 56 and 57 are connected to the output terminal 32 of the second output buffer circuit 14. Sources and drains of the transistors 56 and 57, which are connected to each other, are connected to the external output terminal 3. The gate of the transistor 56 is the inverter 1
It is connected to the mode control terminal 2 via 2. The gate of the transistor 57 is connected to the mode control terminal 2.

In the output circuit of the third embodiment shown in FIG.
The output switching circuit 20A operates almost similarly to the output switching circuit 20A of the output circuit of the first embodiment shown in FIG.

That is, in the case of the operation mode of frequency 66 MHz / logic amplitude 3.3 V, the mode control terminal 2 is supplied with the H level mode control signal S _MC of logic amplitude 2.5 V. As a result, the level shift circuit 19 outputs an H level signal having a logic amplitude of 3.3V, the inverter 12 outputs an L level signal, and the level shift circuit 53 outputs an L level signal.

In the transfer gate 51 of the output switching circuit 20A, the H level output signal is input from the level shift circuit 19 to the gate of the transistor 54, and the L level output signal is input from the level shift circuit 53 to the gate of the transistor 55. To be done. Therefore, the transfer gate 51 is turned on, and the signal path from the output terminal 31 of the first output buffer circuit 13 to the external output terminal 3 is turned on. As a result, the output signal S ₁ of the first output buffer circuit (logic amplitude 3.3 V) is output to the external output terminal
Is output to.

On the other hand, in the transfer gate 52 of the output switching circuit 20A, the L-level output signal is input from the inverter 12 to the gate of the transistor 56, and the H-level signal is input from the mode control terminal 2 to the gate of the transistor 57. It Therefore, the transfer gate 52 is turned off, and the signal path from the output terminal 32 of the second output buffer circuit 14 to the external output terminal 3 is turned off. Therefore, the output signal S _{2 of} the second output buffer circuit 14 (logical amplitude 1.5 V) is not output to the external output terminal 3. Furthermore, from the output terminal 31 of the first output buffer circuit 13 to the output terminal 3 of the second output buffer circuit 14.
The signal path to 2 is also blocked.

In this way, the output signal S ₁ (logic amplitude 3.3 V) of the first output buffer circuit is taken out from the external output terminal 3 as the external output signal S _OUT .

In the operation mode of frequency 133 MHz / logic amplitude 1.5 V, the mode control signal S _MC of L level is supplied to the mode control terminal 2. As a result, the level shift circuit 19 outputs an L level signal and the inverter 12
Outputs an H level signal having a logical amplitude of 2.5V, and the level shift circuit 53 outputs an H level signal having a logical amplitude of 3.3V.

In transfer gate 52 of output switching circuit 20A, the output signal of H level is input from inverter 12 to the gate of transistor 56, and the signal of L level is input from mode control terminal 2 to the gate of transistor 57. Therefore, the transfer gate 52 is turned on, and the signal path from the output terminal 32 of the second output buffer circuit 14 to the external output terminal 3 is turned on. As a result, the output signal S ₂ of the second output buffer circuit
(Logical amplitude 1.5 V) is output to the external output terminal 3.

On the other hand, in the transfer gate 51 of the output switching circuit 20A, the L level output signal is input from the level shift circuit 19 to the gate of the transistor 54, and the level shift circuit 53 is input to the gate of the transistor 55.
To the H-level output signal. Therefore, the transfer gate 51 is turned off, and the signal path from the output terminal 31 of the first output buffer circuit 13 to the external output terminal 3 is turned off. Therefore, the output signal S ₁ (logic amplitude 3.3V) of the first output buffer circuit 13 is not output to the external output terminal 3. Further, the signal path from the output terminal 32 of the second output buffer circuit 14 to the output terminal 31 of the first output buffer circuit 13 is also cut off.

In this way, the output signal S ₂ (logical amplitude 1.5 V) of the second output buffer circuit is taken out from the external output terminal 3 as the external output signal S _OUT .

Also in the output circuit of the third embodiment of FIG. 3, the same effect as that of the output circuit of the first embodiment of FIG. 1 can be obtained.

Furthermore, transfer gates 51 and 52
The transistors 54, 55 and 56, 57 configuring the output of the first or second output buffer circuits 13, 14 have almost no decrease in logical amplitude even if the threshold voltage V _th is not set to "0 V". The signals S ₁ and S ₂ are transmitted to the external output terminal 3 as they are. Therefore, there is no possibility that an unnecessary current path is formed unlike the output circuit of the first embodiment of FIG.

(Modification) In the output circuits of the first and second embodiments described above, n-channel field effect transistors are used as the transistors 10 and 11 functioning as switch elements. Of course, it is possible to adopt a configuration using a transistor.

Further, in the output circuits of the first and third embodiments, the level shift circuits 17 and 18 of the second output buffer circuit 14 can be omitted. In that case, the inverters 23 and 24 forming the pre-driver 5 of the second output buffer circuit 14 may be driven by the power supply voltage of V _DD2 (= 1.5 V). In this respect, the same applies to the output circuit of the second embodiment.

[0114]

As described above, according to the output circuit of the present invention, it is possible to selectively output a plurality of output signals having different amplitudes, and at the same time, it is possible to operate at high speed while preventing a withstand voltage failure. Therefore, it is possible to selectively output a plurality of output signals having different amplitudes at a desired operation speed while preventing a decrease in reliability.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an output circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an output circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of an output circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a conventional output circuit.

[Explanation of symbols]

1 internal input terminal 2 mode control terminal 3 external output terminal 4, 4A pre-driver 5, 5A pre-driver 6, 8 p-channel field effect transistor for driver (output transistor) 7, 9 n-channel field effect transistor for driver (output transistor) 10, 11 n-channel field effect transistor (threshold voltage V _th = 0 V) 12 mode control signal inversion inverter 13, 13A first output buffer circuit 14, 14A second output buffer circuit 20, 20A output switching circuit 21, 22, 23 , 24 inverter 31 output terminal of first output buffer circuit 32 output terminal of second output buffer circuit 41, 43 NAND gate 42, 44 NOR gate 51, 52 transfer gate 53 level shift circuit 54, 56 n-channel field effect transistor 55 , 57 p Channel field effect transistor

Claims (6)

[Claims] 1. An output circuit provided between an internal circuit and an external output terminal, the output circuit being used as an interface when outputting an output signal of said internal circuit to said external output terminal, A plurality of output buffer circuits that receive and output each of a plurality of output signals having different amplitudes; and select one of the plurality of output buffer circuits and output the output signal of the selected output buffer circuit An output switching circuit for outputting to an external output terminal, wherein the output switching circuit cuts off a signal path from the output terminal of the selected output buffer circuit to the output terminal of the unselected output buffer circuit. Characteristic output circuit. 2. Each of the plurality of output buffer circuits comprises:
The output circuit according to claim 1, comprising an output transistor having a withstand voltage performance according to the amplitude of the output signal. 3. Each of the plurality of output buffer circuits comprises:
The output circuit of claim 2, wherein the output transistor is configured to be turned off when it is not selected by the signal switching circuit. 4. The signal switching circuit according to claim 1, wherein the signal switching circuit includes a plurality of switch elements provided between each of the output terminals of the plurality of output buffer circuits and the external output terminal. The output circuit according to claim 1. 5. The output circuit according to claim 4, wherein each of the plurality of switch elements is a field effect transistor. 6. The output circuit according to claim 4, wherein each of the plurality of switch elements comprises a transfer gate composed of a pair of complementary field effect transistors.