JPH02266612A - Transistor circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption, to improve the efficiency and to decrease a switching time by devising the title circuit such that a 2nd transistor(TR) is energized when a 1st TR is saturated so as to limit the base current of the 1st TR. CONSTITUTION:A collector of an output NPN TR 1 being a 1st TR connects to a base of a PNP TR being a 2nd TR and a base of the NPN TR 1 connects to the emitter of the PNP TR 2. Then the saturating state of the NPN TR 1 is detected by the PNP TR 2 and the negative feedback loop limits the base current to the NPN TR 1, then the NPN TR 1 is restored to the ON state nearly equal to the saturation state from the over-saturation state while a sufficient load current is being supplied to a load 10. Thus, the power consumption is small, the efficiency is improved and switching time is quickened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transistor circuit, and particularly to a transistor circuit that prevents saturation of an output transistor.

[Conventional technology]

FIG. 4 is a circuit diagram showing a conventional transistor circuit. In the figure, the collector of an output NPN transistor 1 is connected to the output terminal OUT, the emitter is connected to the ground potential GND, and the base is connected to the collector of a PNP transistor 3. The emitter of PNP transistor 3 is connected to the power supply voltage vcc, and the base is connected to PNP transistor 4.
connected to the base of. The base current of the NPN transistor 1 is supplied from the collector of the PNP transistor 3.

In addition, the emitter of the PNP transistor 4 is connected to the power supply voltage vc
c, and the collector and base are commonly connected. PNP) transistors 3 and 4 constitute a current mirror circuit.

The collector of the PNP transistor 4 is connected to the collector of the NPN transistor 5, and the base of the NPN transistor 5 is connected to the base of the NPN transistor. NPN) The base and collector of the transistor are connected in common. The emitter of the NPN transistor 5 is connected to the ground potential GND via a balance resistor 7.
The emitter of the NPN transistor 6 is connected to the ground potential GND via a balance resistor 8. The NPN transistor 5.6 constitutes a current mirror circuit whose current ratio is defined by a corresponding balance resistor 7.8.

Further, a constant current source 9 is connected between the power supply voltage Vcc and the collector of the NPN transistor.

Furthermore, the power supply voltage V. A load 10 is connected between C and the output terminal OUT.

Next, the operation will be explained. According to the ON10FF state of the switching element (not shown) in the constant current source 9, N
PN) Current is supplied to the transistor. A current defined by the resistance ratio between the supply current of the NPN transistor and the balance resistor 7.8 flows through the NPN transistor 5. The collector current flowing in the NPN transistor 5 and the collector current flowing in the PNP transistor 4 are equal, and since the PNP transistors 3 and 4 constitute a current mirror circuit, the collector current of the NPN transistor 5 and the collector current flowing in the PNP transistor 3 are equal. is equal to the collector current of . The collector current of the PNP) transistor 3 becomes the base current of the NPN) transistor 1, and when the NPN transistor 1 is turned on, the power supply voltage V. A load current flows from the output terminal OUT to the load 10, and further from the output terminal OUT to the NPN transistor 1.

[Problem to be solved by the invention]

Conventional transistor circuits are configured as described above, so even if there are variations in the characteristics of the output NPN ) was supplied to the base of transistor 1.

Therefore, there is a problem in that the extra base current increases power consumption and reduces load driving efficiency. Also,
There is also a problem that the switching time of the NPN transistor 1 becomes slow.

This invention was made to solve the above-mentioned problems, and aims to provide a transistor circuit that supplies sufficient current, has low power consumption, is highly efficient, and has a fast switching time. .

[Means to solve the problem]

A transistor circuit according to the present invention includes a first transistor of a first conductivity type in which a current path between a collector and an emitter is connected in series with a load, a base connected to the collector of the first transistor, and an emitter connected to the first transistor. A second transistor of a second conductivity type is connected to the base of the transistor, and the collector and emitter of the second transistor are connected to each other. It is equipped with a negative feedback loop that limits the flowing current.

[Effect]

The second transistor in this invention has a base connected to the first transistor.
Since the emitter is connected to the collector of the first transistor and the emitter is connected to the base of the first transistor, when the first transistor becomes saturated, it becomes conductive and limits the base current of the first transistor.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram showing a transistor circuit according to an embodiment of the present invention.

In the figure, the collector of the output NPN transistor 1 is connected to the base of the PNP transistor 2, and the base of the NPN transistor 1 is connected to the emitter of the PNP transistor 2. The emitter of PNP) transistor 2 is also connected to the collector of PNP) transistor 3, and PN
P The collector of transistor 2 is connected to balance resistor 7 and NP
N Connected to the connection point with the emitter of transistor 5. The other configurations and connection relationships are the same as those of the conventional transistor circuit shown in FIG. 4 described above.

Next, the operation will be explained. Similar to the conventional transistor circuit shown in FIG. 4 described above, the PNP)
A base current is supplied from the collector of transistor 3 to the base of transistor 1 (NPN).

Even if NPN transistor 1 is turned on, the potential difference between the base and collector of NPN transistor 1, that is, P
NP) The PNP transistor 2 is in the OFF state while the potential difference between the emitter and base of the transistor 2 does not reach the threshold voltage of the PN junction.

When an excessive base current is supplied to the base of NPN) transistor 1, the collector current of NPN) transistor 1 increases, and NPN) transistor 1 goes from a normal ON state to a supersaturated state, the potential of the collector of NPN) transistor 1 increases. The voltage drops to almost equal to the emitter potential.

The potential difference between the emitter and base of PNP) transistor 2 reaches the threshold voltage of the PN junction, and PNP) transistor 2
When PNP transistor 3 turns on, the collector current of PNP transistor 3 is divided into the base of NPN transistor 1 and the collector of PNP transistor 2. Therefore, NPN
The base current of transistor 1 is PNP) transistor 2
The base current of the NPN transistor 1 is limited.

NPN ) transistors 5, 6 and balance resistor 7.8
Current flows into the balance resistor 7 from the collector of the PNP transistor 2 outside the current mirror circuit, so the balance resistor 7
．． In order to maintain the ratio of current flowing to 8, the NPN transistor 5
collector current decreases. Following the decrease in the collector current of NPN) transistor 5, PNP) transistor 3
, 4 also decreases, and the base current of NPN transistor 1 also decreases. Therefore, the NPN transistor 1 returns from the supersaturated state to a completely ON state almost close to the saturated state. In addition, PNP) transistor 3.4 and N
The PN) transistor 5 constitutes a negative feedback loop that limits the collector current flowing to the PNP) transistor 2.

As described above, PNP) transistor 2 and PNP
) The negative feedback loop that limits the collector current flowing through the transistor 2 can prevent the NPN transistor 1 from becoming oversaturated.

In addition, the NPN) transistor 1 is supplied with a base current that is completely on, almost close to the saturated state, so it has a current driving ability comparable to that in the saturated state and can supply sufficient current to the load 10. I can do it.

FIG. 2 is a sectional view showing a part of the transistor circuit shown in FIG. 1 integrated on a semiconductor substrate.

In the figure, a Nu floating collector layer 51 is formed on a P-type substrate 50, and an N-type epitaxial layer 52 is formed on the N-type floating collector layer 51.

P-type isolation layers 53 are formed on both sides of the N-type epitaxial layer 52.

In the N type epitaxial layer 52, an N type diffusion layer 54,
A P-type base diffusion layer 55 and a P-type diffusion layer 56 are formed separately, and an N-type emitter diffusion layer 57 is formed within the P-type base diffusion layer 55. N-type diffusion layer 5
4 is connected to an output terminal 100 via an electrode 54M, and the N-type emitter diffusion layer 57 is connected to a ground terminal 200 via an electrode 57M.
is connected.

Next, the correspondence with each part of the transistor circuit shown in FIG. 1 will be explained. The base, emitter, and collector of the NPN transistor 1 shown in FIGS. 1 and 2 are each
P-type base diffusion layer 55 shown in FIG. N-type emitter diffusion layer 57. They correspond to the N-type floating collector layer 51 and the N-type epitaxial layer 52, respectively. 1st
The base, emitter, and collector of the PNP transistor 2 shown in FIG. P-type base diffusion layer 55. This corresponds to each of the P-type diffusion layers 56. Further, the output terminal 100 corresponds to the output terminal OUT shown in FIG. 1, and the ground terminal 200 corresponds to the ground potential GND shown in FIG. 1, respectively.

The PNP) transistor 2 can be easily formed in a parasitic manner by simply adding a P-type diffusion layer 56 on the semiconductor substrate on which the NPN) transistor 1 is formed. Therefore, when integrating the transistor circuit shown in FIG. 1 on a semiconductor substrate,
PNP transistor 2 for limiting the base current of NPN transistor 1 can be easily formed while suppressing an increase in mounting area.

FIG. 3 is a circuit diagram showing a bridge configuration transistor circuit according to another embodiment of the present invention.

Darlington-connected PNP) transistor 11 and NPN) transistor 12 are connected to the power supply voltage VC.

and the output terminal 0UT1. PNP)
The bases of transistors 11 are commonly connected to the bases of transistors 3 (PNP). The collector of the NPN transistor 1 is connected to the output terminal 0UT2, and the collector of the NPN transistor 1 is connected to the output terminal 0UT2.
A load 10 is connected between UT1 and output terminal 0UT2. Other configurations and connection relationships are as described in the first section above.
This is similar to the transistor circuit shown in the figure.

In this bridge configuration T-transistor circuit, the first
Similar to the transistor circuit shown in the figure, the base current of the NPN transistor 1 is limited by the PNP) transistor 2, and the load 10 is
can supply sufficient load current. Also, P.N.
Since the base of the P transistor 11 is commonly connected to the base of the PNP transistor 3, a negative feedback loop that limits the base current also operates for the PNP transistor 11, and the PNP transistor 11 and the NPN
) Oversaturation of the transistor 12 can be prevented.

As described above, in the embodiment of the present invention shown in FIGS. 1 and 3, the PNP transistor 2
The saturation state of transistor l is detected and the base current of NPN transistor 1 is limited by a negative feedback loop, so that while supplying sufficient load current to load 10,
The transistor 1 can be returned from a supersaturated state to a completely ON state that is almost close to a saturated state.

In the embodiments described above, it goes without saying that the same effect can be achieved even if a Darlington-connected transistor is used instead of the NPN transistor 1.

〔Effect of the invention〕

As described above, according to the present invention, the base of the second transistor is connected to the collector of the first transistor, and the emitter is connected to the base of the first transistor, so that the first transistor is not saturated. When this happens, it becomes conductive and limits the base current of the first transistor.

Therefore, it is possible to obtain a transistor circuit that has low power consumption, high efficiency, and quick switching time while supplying sufficient current.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a transistor circuit according to an embodiment of the present invention, FIG. 2 is a sectional view showing a part of the transistor circuit shown in FIG. 1 integrated on a semiconductor substrate, and FIG. 3 is a circuit diagram of a transistor circuit according to an embodiment of the present invention. A circuit diagram of a transistor circuit according to another embodiment of
FIG. 4 is a circuit diagram of a conventional transistor circuit. In the figure, 1 is an NPN) transistor, 2 is a PNP transistor, GND is a ground potential, OUT is an output terminal, and 5
1 is an N-type floating collector layer, 52 is an N-type epitaxial layer, 54 is an N-type diffusion layer, 55 is a P-type base diffusion layer, 56 is a P-type diffusion layer, 57 is an N-type emitter diffusion layer, 1
oo is an output terminal, and 2oo is a multipurpose ground terminal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) a first transistor of a first conductivity type in which a current path between a collector and an emitter is connected in series with a load; a base connected to the collector of the first transistor; and an emitter connected to the collector of the first transistor; The second connected to the base
Negative feedback is connected between a conductive type second transistor and the collector and emitter of the second transistor, detects the current flowing through the second transistor, and limits the current flowing through the second transistor. A transistor circuit with a loop.