JPH02266587A - Circuit substrate - Google Patents
Circuit substrateInfo
- Publication number
- JPH02266587A JPH02266587A JP8921389A JP8921389A JPH02266587A JP H02266587 A JPH02266587 A JP H02266587A JP 8921389 A JP8921389 A JP 8921389A JP 8921389 A JP8921389 A JP 8921389A JP H02266587 A JPH02266587 A JP H02266587A
- Authority
- JP
- Japan
- Prior art keywords
- holes
- intervals
- lead
- straight line
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 8
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 239000011295 pitch Substances 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
Landscapes
- Tests Of Electronic Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（概要）
回路基板に係り、抵抗器やコンデンサなどの電子部品を
接続してその信頬性評価における寿命試験を行う回路基
板の電極パターンの構成に関し、電子部品の種々の間隔
のリードを汎用的に接続することを目的とし、
絶縁基板に複数のスルーホールを一直線上に所定間隔で
備え、該スルーホールの中、少なくとも１個の第１のス
ルーホールを第１の導体パターンで接続し、残る第２の
スルーホールを第２の導体パターンで接続して構成する
。[Detailed Description of the Invention] (Summary) This invention relates to the configuration of the electrode pattern of a circuit board, which connects electronic components such as resistors and capacitors, and conducts a life test for reliability evaluation. The purpose of the present invention is to universally connect leads having a spacing of The remaining second through holes are connected by a conductive pattern and the remaining second through holes are connected by a second conductive pattern.
本発明は回路基板に係り、抵抗器やコンデンサなどの電
子部品を接続してその信顛性評価における寿命試験を行
う回路基板の電極パターンの構成に関する。The present invention relates to a circuit board, and more particularly, to the configuration of an electrode pattern of a circuit board to which electronic components such as resistors and capacitors are connected and a life test is performed to evaluate the reliability thereof.
信頬性評価の対象となる抵抗器やコンデンサなどの電子
部品の形状は様々であり、形状が異なる部品のリード間
隔毎に対応する導体パターンを備える回路基板を用意し
寿命試験を行っている。その点、不経済であるため、異
なるリード間隔に対し融通性があって経済性のよい汎用
の回路基板が要望されている。Electronic components such as resistors and capacitors that are subject to reliability evaluation come in a variety of shapes, and life tests are conducted using circuit boards with conductor patterns that correspond to the lead spacing of components with different shapes. Since this is uneconomical, there is a demand for a general-purpose circuit board that is flexible and economical for different lead spacings.
従来の回路基板は第２図の平面図に示すように、絶縁基
板１１に直流電源（図示路）の十電位を接続する正電極
パターン１１ａ（斜線で示す部分）と電位を接続する負
電極パターンｌｌｂを本線から３本の支線に分岐して互
い違いに組み合わせ、組み合わせた正電極パターンｌｌ
ａと負電極パターン１１ｂとの間隔Ａを接続する電子部
品、例えば抵抗器のリード間隔に合わせ、正電極パター
ン１１ａ、負電極パターンｌｌｂそれぞれにコンデンサ
を並列に接続するスルーホールｌ１ａ−１，ｌ１ｂ−１
を備えている。As shown in the plan view of FIG. 2, the conventional circuit board has a positive electrode pattern 11a (shaded area) that connects the ten potentials of the DC power supply (the path shown) to the insulating substrate 11, and a negative electrode pattern that connects the potential. Positive electrode pattern ll is created by branching llb from the main line into three branch lines and combining them alternately.
Through holes l1a-1 and l1b- are formed to connect capacitors in parallel to the positive electrode pattern 11a and the negative electrode pattern llb, respectively, in accordance with the lead spacing of an electronic component, such as a resistor, to connect the distance A between the negative electrode pattern 11b and the positive electrode pattern llb. 1
It is equipped with
そして、スルーホール１ｌａ−１，１１ｂ−１に抵抗器
１２のり一ド１２ａを２点鎖線で示すように半田付は接
続し、寿命試験を行っている。Then, the glue 12a of the resistor 12 was connected to the through holes 1la-1 and 11b-1 by soldering as shown by the two-dot chain line, and a life test was performed.
しかしながら、このような上記回路基板の電極パターン
構成によれば、抵抗器の形状が大きくなりリード間隔が
異なれば、リード間隔に合わせたピンチのスルーホール
を備える回路基板を必要とし、経済性が悪いといった問
題があった。However, according to such an electrode pattern configuration of the circuit board, if the shape of the resistor is large and the lead spacing is different, a circuit board with a pinch of through hole that matches the lead spacing is required, which is not economical. There was such a problem.
上記問題点に鑑み、本発明は電子部品の種々の間隔のリ
ードを汎用的に接続することのできる回路基板を提供す
ることを目的とする。In view of the above-mentioned problems, an object of the present invention is to provide a circuit board that can universally connect leads at various intervals of electronic components.
Ｃ課題を解決するための手段〕
上記目的を達成するために、本発明の回路基板において
は、絶縁基板に複数のスルーホールを一直線上に所定間
隔で備え、該スルーホールの中、少なくとも１個の第１
のスルーホールを第１の導体パターンで接続し、残る第
２のスルーホールを第２の導体パターンで接続して構成
する。Means for Solving Problem C] In order to achieve the above object, in the circuit board of the present invention, a plurality of through holes are provided in a straight line at predetermined intervals in an insulating substrate, and at least one of the through holes is the first of
The through holes are connected by the first conductor pattern, and the remaining second through holes are connected by the second conductor pattern.
直線上に所定間隔、例えば２．５４１ｉ＋あるいは１．
２７鰭ピツチのスルーホールを配列することにより、異
なるリード間隔の電子部品でもそのリード間隔に合わせ
てスルーホールを選択する接続することができるため、
１種類の回路基板で汎用的に融通適用することができる
。A predetermined interval on a straight line, for example 2.541i+ or 1.
By arranging through holes with 27 fin pitches, electronic components with different lead spacing can be connected by selecting the through hole according to the lead spacing.
One type of circuit board can be used for general purposes.
以下図面に示した実施例に基づいて本発明の要旨を詳細
に説明する。The gist of the present invention will be explained in detail below based on embodiments shown in the drawings.
回路基板は第１図の平面図に示すように、絶縁基板１に
複数のスルーホール２（図は９個を示す）を一直線上に
所定ピンチｐ、即ち２．５４鶴（あるいは１．２７ｎ）
で備え、該スルーホール２の中、少なくとも１個の第１
のスルーホール２ａ （図は３個を示す）を第１の導体
パターン２ａ−１（斜線で示す部分）で接続し、残りの
第２のスルーホール２ｂ （図は６個を示す）を第２の
導体パターン２ｂ−１で接続する。更に、この直線上に
連なる第１、第２の導体パターン２ａ−１，２ｂ−１を
平行に並列し、第１の導体パターン２ａ−１のそれぞれ
の一端を１つにまとめる正電極部２ａ−２に接続し、第
２の導体パターン２ｂ−１のそれぞれの一端を１つにま
とめる負電極部２ｂ−２に接続する。As shown in the plan view of FIG. 1, the circuit board has a plurality of through holes 2 (the figure shows nine) in an insulating substrate 1 in a straight line with a predetermined pinch p, that is, 2.54 holes (or 1.27 nm).
and at least one first hole in the through hole 2.
The through holes 2a (the figure shows three) are connected with the first conductor pattern 2a-1 (the shaded part), and the remaining second through holes 2b (the figure shows six) are connected to the second conductor pattern 2a-1 (the figure shows six). Connect with the conductor pattern 2b-1. Further, the first and second conductor patterns 2a-1, 2b-1 connected on this straight line are arranged in parallel, and one end of each of the first conductor patterns 2a-1 is combined into a positive electrode part 2a-. 2, and one end of each of the second conductor patterns 2b-1 is connected to a negative electrode part 2b-2 that brings together one end.
この回路基板に電子部品、例えば抵抗器を接続搭載して
寿命試験を行うには、第１．第２のスルーホール２ａ、
２ｂ間に抵抗器３のリード３ａを２点鎖線で示すように
半田付は接続する。リード３ａの接続は抵抗器３のリー
ド間隔により第１のスルーホール２ａを基準に第２のス
ルーホール２ｂのいずれかのスルーホールを選び接続す
る。コンデンサの寿命試験においても同様にリード間隔
に合わせスルーホールを選択することにより汎用性を有
して接続することができる。To conduct a life test by connecting and mounting electronic components, such as resistors, on this circuit board, first. second through hole 2a,
2b, the lead 3a of the resistor 3 is connected by soldering as shown by the two-dot chain line. The lead 3a is connected by selecting one of the second through holes 2b based on the first through hole 2a depending on the lead spacing of the resistor 3. Similarly, in capacitor life tests, by selecting through holes according to the lead spacing, connections can be made with versatility.
このように、スルーホールを一直線上に所定間ＩＩ （
２，５４鶴、１．２７鶴の他、特殊ピンチでもよい）の
配列することにより、リード間隔に合ったスルーホール
を選択し接続することができるため、１種類の回路基板
で異なるリード間隔の電子部品を自在に接続することが
でき、経済性が向上する。In this way, align the through holes in a straight line for a predetermined distance II (
By arranging 2.54 cranes, 1.27 cranes, or special pinch holes, you can select and connect through holes that match the lead spacing, so you can connect different lead spacings on one type of circuit board. Electronic components can be freely connected, improving economic efficiency.
また、スルーホールにソケットを介して電子部品を接続
してもよく、さらに経済性を高めることができる。Furthermore, electronic components may be connected to the through holes via sockets, further increasing economic efficiency.
Claims (1)
に所定間隔で備え、該スルーホール（２）の中、少なく
とも１個の第１のスルーホール（２ａ）を第１の導体パ
ターン（２ａ−１）で接続し、残る第２のスルーホール
（２ｂ）を第２の導体パターン（２ｂ−１）で接続して
なることを特徴とする回路基板。A plurality of through holes (2) are provided in a straight line at predetermined intervals in an insulating substrate (1), and among the through holes (2), at least one first through hole (2a) is connected to a first conductor pattern ( 2a-1) and the remaining second through hole (2b) is connected by a second conductor pattern (2b-1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8921389A JPH02266587A (en) | 1989-04-06 | 1989-04-06 | Circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8921389A JPH02266587A (en) | 1989-04-06 | 1989-04-06 | Circuit substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02266587A true JPH02266587A (en) | 1990-10-31 |
Family
ID=13964440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8921389A Pending JPH02266587A (en) | 1989-04-06 | 1989-04-06 | Circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02266587A (en) |
-
1989
- 1989-04-06 JP JP8921389A patent/JPH02266587A/en active Pending
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