JPH0226418A - Double integral type a/d converting circuit - Google Patents

Abstract

PURPOSE:To obtain a double integral type A/D converting circuit whose conversion time is short by determining more significant bits and after that, determining less significant bits based on the result. CONSTITUTION:When an A/D conversion is made, the more significant bits are determined by a first double integral type A/D converter 3 and based on the result, the less significant bits are obtained by a second double integral A/D converter 23. Consequently, the integral periods of the A/D converters 3 and 23 can be shortened and the conversion time can be shortened as a whole. Thus, the A/D converting circuit in which original advantages of the double integral type A/D converting circuit are made the best use of and the conversion time is shortened can be obtained.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a double integral type A/D (analog/digital) conversion circuit for converting an analog signal into a digital signal, and particularly relates to a double integration type A/D (analog/digital) conversion circuit for converting an analog signal into a digital signal. This invention relates to a double-integration type A/D conversion circuit designed to increase speed.

(B) Prior Art Various A/D conversion circuits for converting analog signals into digital signals have been proposed in the past, and are selectively used depending on the application. For example, as a low-speed A/D conversion circuit with a conversion time of several m8 or more, an integral type A/D conversion circuit is mainly used, and this is applied to digital multimeters, electronic scales, and the like. A successive approximation A/D conversion circuit is used as a medium-speed A/D conversion circuit with a conversion time of several microseconds to several hundred microseconds, and is applied to PCM communications, digital audio, and the like. Further, as a high-speed A/D conversion circuit with a conversion time of several hundred ns or less, a parallel comparison type A/D conversion circuit is used and is applied in the fields of video signal processing and measurement. Regarding A/D conversion circuits, please refer to 1 Illustrated A/D dated July 30, 1985.
It is explained in detail in "Introduction to D Converter".

By the way, a double integral type A/D conversion circuit is known as one type of integral type A/D conversion circuit. The A/D conversion circuit applies the voltage to be measured to the analog integrator, stops applying the voltage to be measured after a certain period of time, and instead applies a reference voltage of opposite polarity to the voltage to be measured to the analog integrator. Applied to the integrator. At the same time, a clock pulse having a known frequency is applied to the counter, and the supply of the clock pulse to the counter is stopped when the output voltage of the analog integrator returns to the initial reference value. At this time, the count value counted by the counter corresponds to the voltage to be measured, and a digital value is obtained from the count value of the counter. The double integration type A/D conversion circuit has the following advantages:
It has many advantages, such as being unaffected by fluctuations in the integral constant and long-term drift of clock pulses, and is widely used.

(c) Problems to be Solved by the Invention However, the double integration method has the disadvantage that the conversion time is slow because the conversion time is determined depending on the time constant during integration. A parallel comparison type A/D conversion circuit as mentioned above is an example of a device with a fast conversion time, but this A/D conversion circuit requires a very large number of elements when obtaining a high-order bit digital signal. Therefore, when integrated into an IC, there are problems in that the chip area increases and current consumption increases.

Therefore, a double integration type A/D conversion circuit with a fast conversion time has been desired.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and is a first double-integrating type A/R that generates a high-order bit digital signal corresponding to the level of an analog input signal. a D converter, a reference voltage generation circuit that selectively generates one of a plurality of reference voltages according to an output signal of the A/D converter, and an output reference voltage of the reference voltage generation circuit and the analog an arithmetic circuit that performs an arithmetic operation with an input signal; and a second double integration type A/D converter to which an output signal of the arithmetic circuit is applied and generates a digital signal of lower bits corresponding to the level of the analog input signal. It is characterized by consisting of.

(f) Function According to the present invention, the first double-integrating A/D converter first generates a digital signal of the upper bits corresponding to the level of the analog input signal.

Then, the reference voltage of the reference voltage generation circuit is selected according to the digital signal, the selected reference voltage is operated on the analog input signal, and the operation result is converted into a second double-integration type A/D conversion. A/D conversion is performed by the device. Therefore, a digital signal corresponding to the lower bits of the analog input signal can be obtained at the output end of the A/D converter.

(v) Embodiment The figure is a circuit diagram showing an embodiment of the present invention, in which (1) is an input terminal to which an analog input signal vx is applied, and (2) is a reference voltage (with a polarity opposite to that of the analog input signal). -Vref, )
The first reference power supply terminal to which (3) is applied is the first integrating circuit (4), the first comparator (5), and the first control circuit (6).
, a first double-integrating A/D converter, which comprises a first counter (7) and a first latch circuit (8), and determines the upper two bits corresponding to the level of the analog input signal v8;
9) is a first clock source for supplying clock pulses to the first control circuit (6), and (10) to (12) are first to third control signals (12) for supplying clock pulses to the first control circuit (6). S+-
1st to 3rd switches, (
13) to (16) are the second reference power supply terminals (17) ("V
ref, ) and the ground for generating a reference voltage, (18) to (21) are the resistors (13)
4th to 7th switches for selecting one of the plurality of reference voltages obtained at each connection point of (16), (22)
) is a subtraction circuit that performs subtraction between the analog input signal 8 and the reference voltage selected by the fourth to seventh switches (18) to (21), and (23) is a second integration circuit (24).
〉, second humparator (25), second control circuit (26)
, a second double-integrating A/D converter (29) comprising a second counter (27) and a second latch circuit (28) and determining the lower two bits corresponding to the level of the analog input signal v8; (30) is a second clock source for supplying clock pulses to the second control circuit (26); (30) is the first clock source;
The fourth to seventh circuits according to the output signal of the latch circuit (8)
Switches (18) to (21) and the eighth switch (31)
) control signal (S, .).

a third control circuit that generates (32) and (S, , );
33) are the ninth and tenth circuits of the second control circuit (26).
The ninth gate opens and closes in response to control signals (S, 1 and S, .)
and the tenth switch.

Next, Figure 0, which will explain the operation, is a circuit diagram when an analog input signal is converted into a 4-pit digital signal. First, in the initial state, the first control signal S1m is generated from the first control circuit (6) to close the first switch (10). (At this time, the second and third switches (11) and (
12) has been developed. ) Then, the first integrating capacitor (34) is discharged, so the output voltage of the first integrating circuit (4) becomes zero. Next, the first control circuit (6) starts receiving clock pulses from the first clock source (9). When the acquisition is started, the first control circuit (6) starts counting the clock pulses using a built-in counter, generates the second control signal Smm, and generates the second control signal Smm.
Only the switch (11) is closed.

At this time, the first and third switches (10) and (12
> is in the open state. When the second switch (11) is closed, the analog input signal vx is applied to the negative input terminal (-) of the first amplifier (35), and the signal 8 is integrated for a certain period of time. At this time, the current 11 flowing through the first resistor (36) is: 1, = V, /R, ...
...(1) [However, R8 is the resistance value of the first resistor (36)]. If the output voltage of the first integrating circuit is VOI, then Vll is Vel” Ltt/C+ ・・・・・・・・・・・・
・・・・・・・・・・・・(2) By substituting equation (1) into equation (2), the voltage Vel is Vo+= (1/C+)(Vx/R+)ntT””・
""'(3). When the first control circuit (6) counts a predetermined number of clock pulses, it generates a count completion signal, opens the second switch (11), and opens the third switch (11).
2) is closed.

When the third switch (12) is closed, the reference voltage -Vref, which has the opposite polarity to the signal v8, is applied to the negative input terminal (-) of the first amplifier (35).
4) Discharge occurs and a constant current (Vref I/R, )
flows through the first resistor (36). On the other hand, at the same time as the third switch (12) is closed, the first control circuit (6) passes the clock pulse from the first clock source (9).
is applied to the counter (7). Therefore, the first counter (7) starts counting.

The initial charging voltage of the first capacitor (34) is V. If it is 0, then the voltage is ■. . is Vco-Vat-(1/C+)(Vx/Rt)ntT"
...(4), the first capacitor (34)
The output voltage van of the first integrating circuit (4) during the discharging period is: -(1/CI)(Vx/Rt)ntT(
1/C+)(-Vref+/Rt)tt・”
...= (5) [where t is the discharge period]. The first capacitor (34) is discharged until the output voltage of the first integrating circuit (4) becomes zero. When the output voltage becomes zero, the first comparator (5) is inverted, and the first control circuit (6) stops supplying clock pulses from the first clock source (9) to the first counter (7). . If the count value of the clock pulses of the first counter (7) at this time is n, then the discharge period t is j! -n*・T ・・・・・・・・・・・・
It can be expressed as (6). Chapter (6)
Substituting the formula into the formula (5) and assuming that the output voltage Vat is the digital value n from the formula (5), nt=n+(Vx/Vrefl) m*+emmmme
++ (7) is obtained. Therefore, the analog input signal v
8 can be converted into a digital value n. The digital value n indicates a high-order bit digital signal corresponding to the level of the signal v8, and in the case of this embodiment, a 2-bit digital signal is generated, and the first latch circuit (8) generates a 2-bit digital signal. The signal is latched and generated at the first output terminal (37). Further, when the output digital signal of the first latch circuit (8) is applied to the third control circuit (30), the third control circuit (30)
30) generates control signals for opening and closing the fourth to seventh switches (18) to 21) and the eighth switch (31).

Now, suppose that the level of the analog input signal v8 is a value (V+ < Vx <'/!) between the reference voltages v1 and ■ generated at both ends of the resistor (15), respectively.
Control signal S6 from the third control circuit (30). Accordingly, of the fourth to seventh switches (1B) to (21), only the sixth switch (20) is closed, and the reference voltage (2) is applied to the subtraction circuit (22). At the same time, the third control circuit (30
), the eighth switch (31)
is closed.

Then, in the subtraction circuit (22), the analog input signal V! and the reference voltage V, and the subtraction result Δv(-vx-++) is applied to the second integrating circuit (2
4) Negative input terminal (-) of the second amplifier (38)
is applied to

The operation of the second double-integrating A/D converter (23) is similar to the operation of the first double-integrating A/D converter (3) described above, and first, the second control circuit (26) ) from the ninth control signal S
The ninth switch (32) closes in response to ob, the second capacitor (39) discharges, and the initial state is set. Thereafter, the aforementioned output voltage ΔV of the subtraction circuit (22) is integrated. As a result, the output pressure Vam of the second integrating circuit (24) is Ve * − (1/Cx) (ΔV/Rt)nsT
・= +++ +++ ++ (8). after that,
The 8th switch (31) is opened and the 10th switch (33) is opened.
) closes, the second capacitor (39) starts discharging, and the output voltage VO of the second integrating circuit (24) during the discharging period
W is v, tm - (1/Cri(ΔV/R*)nsI'-(1
/C,>(-vref+/R*)ts ・・−・−−
--(9) [where t is the discharge period]. Here, the second counter (2
If the count value of clock pulses in 7) is n4,
Discharge period t, is t, tm n4・engineer...
...(10), substitute the equation (10) into the equation (9), and get the output voltage ■. .

If is set to zero, then from equation (9), the digital value n4 is Q4mn, (ΔV/Vref+) ・””
(11) is obtained. Therefore, the input voltage ΔV, which is an analog input signal, can be converted into a digital value n4. The digital value n indicates the lower bit corresponding to the level of the analog input signal 8. In the case of this embodiment, a 2-bit digital signal is generated and latched by the second latch circuit (28). and the second output terminal (40)
occurs in

As a result, if the high-order 2-bit digital signal obtained at the first output terminal (37) and the low-order 2-bit digital signal obtained at the second output terminal (40) are arranged serially,
An output digital signal can be obtained as a result of A/D conversion of an input analog signal.

Now, in general, a double integration type A/D conversion circuit requires a maximum of 2×2N clocks (N is the number of clocks in the integration period) during the integration period of the input analog voltage, but in the present invention, the upper bit is After that, the lower bits are determined based on the result, so if the upper bits and lower bits have the same number of bits, the number of clocks for the A/D conversion circuit that determines the upper and lower bits can be reduced to half of the conventional one. (N/2). Therefore, the maximum number of clovers required in the example is (2×2"") and (
2×2””), resulting in 4×2 N/1 pieces. Therefore, compared to the conventional method, the number of steps is much smaller, and the conversion time can be significantly shortened. This is particularly effective when obtaining a high-order bit digital signal, and an example of this is shown below.

(Number of bits) (Number of clocks according to the present invention) (Number of conventional clocks) 4 bits 16 32 8
Bits: 64 pieces 512 pieces 16 bits: 1024 pieces 131072 pieces The conversion speed can be further improved if the integration period of the input analog signal in the embodiment is replaced with a sample and hold operation. or,
In the embodiment of FIG. 1, the first and second double integral type A
Although the first and second amplifiers (35) and (38) are used in the /D converters (3) and (23), respectively, they can also be used in common. Furthermore, in the embodiment, the case where the number of upper bits and the lower bit are equal has been explained, but this does not necessarily have to be the same, and the number of bits may be different.Furthermore, in the embodiment, ,
The reference pressure applied to the second reference power supply terminal (17) is set to the positive polarity (
+Vref*), a subtraction circuit (22) was used; however, depending on the polarity of the reference voltage, the subtraction circuit (22>) may operate as an addition circuit. However, this is essentially a subtraction operation.

<g) Effects of the invention As mentioned above, according to the present invention, when performing A/D conversion, the upper bits are determined by the first double integral type A/D converter, and the lower bits are determined based on the result. Since the bits are obtained by the second double integration type A/D converter, the integration period of each A/D converter can be shortened, and the overall conversion time can be shortened. . Therefore, it is possible to provide an A/D conversion circuit that can speed up the conversion time while taking advantage of the many advantages that the double-integration type A/D conversion circuit originally has.

[Brief explanation of the drawing]

The figure is a circuit diagram showing one embodiment of the present invention. (1)...Input terminal, (2)...First reference power supply terminal, (3)...First double integral type A/D converter, (
13> to (16)...Resistor, (22)...Subtraction circuit, (23)...Second double integral type A/D converter, (30)...Third control circuit.

Claims (3)

[Claims] (1) A first double-integrating A/D converter that generates a high-order bit digital signal corresponding to the level of an analog input signal, and a plurality of reference voltages depending on the output signal of the A/D converter. a reference voltage generation circuit that selectively generates one of the voltages;
an arithmetic circuit that performs an arithmetic operation on the output reference voltage of the reference voltage generation circuit and the analog input signal; and an arithmetic circuit to which the output signal of the arithmetic circuit is applied and generates a digital signal of lower bits corresponding to the level of the analog input signal. A double-integration type A/D conversion circuit comprising a second double-integration type A/D converter. (2) The reference voltage generation circuit includes a reference power source and a plurality of resistors connected in series between the reference power source and the ground, and uses the voltage obtained at the connection point of the plurality of resistors as the reference voltage. 2. A double integral type A/D conversion circuit according to claim 1. (3) The double integration type A/D conversion circuit according to claim 2, wherein the number of the plurality of resistors is made equal to the number of bits of the digital signal after A/D conversion.