JPH02261272A - High definition television receiver - Google Patents

Abstract

PURPOSE:To confirm a picture during present input even during freeze picture selection by selecting switchingly a slave pattern generating circuit always receiving an input picture signal and a master pattern generating circuit obtaining a freeze picture. CONSTITUTION:An input signal is inputted to an inter-frame interpolation circuit 6 in the normal mode via a terminal (a) of an NR circuit 2 and stored in field memories 3, 4. Moreover, a pattern reduction circuit 18 reduces the pattern of input picture signals and generates a picture signal for a slave pattern. When a freeze picture is requested, the circuit 2 is thrown to the position of the terminal (b) and selection circuits 19, 20, 22 are thrown to the position of the terminal (a) for an output period of a master pattern video signal and they are thrown to the position of the terminal (b) for an output period of the slave pattern video signal. Thus, the picture stored in the circuit 5 is observed by the master pattern and the picture sent at present is observed by the slave pattern. Thus, even when the freeze picture is requested, the existing picture is always confirmed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention is a high-definition television signal reception method that demodulates a band-compressed high-definition television signal into the original wideband high-definition television signal. In particular, the decoder circuit for obtaining frozen images has been improved.

(Prior Art) As a method of compressing a broadband high-definition television signal to a practical level for transmission, MUSE (MUSE) is a method of applying subsampling to the original high-definition television signal in a cycle of four fields. Multiple 5ub-Nyq
ulsut sampling encoding) method (“New transmission method for high-definition television - MUSE-, N
HK Giken Monthly Report, by Ninomiya, Vol. 27, No. 7, 1981).

FIG. 8 is an example of a decoder for demodulating a band-compressed high-definition television signal (hereinafter referred to as a MUSE signal) into the original wide-band high-definition television signal.

1 is a MUSE signal input terminal, and the MUSE signal 101 (sample rate 1B, 2M1
lz) is first input to the interframe interpolation unit 5. In the interframe interpolation section 5, the input signal 1o1 is input to an input switching circuit 2 (hereinafter referred to as NR circuit).

The NR circuit 2 alternately selects the signal 101 and the signal 104, performs interpolation processing, and supplies the output to the first field memory 2. The first field memory 3 outputs a signal C8 one field before the signal 101 and a signal three fields before the signal 101 as a signal 103 interpolated between frames. This signal 103 is supplied to the second field memory 4. Therefore, the second field memory 4 outputs the signal 2 fields before the signal 101 and the signal 4 fields before the signal 101 as a signal 104 interpolated between frames.

Therefore, in the NR circuit 2, processing is performed to replace the signal 1 (II) with the signal 4 fields earlier out of the 14, and the resulting signal 102 (sample rate 32.4 MIIz) is output. Ru.

The intra-field interpolation processing circuit 6 to which the signal 102 is supplied first extracts only the data of the white current field of the signal 102, and outputs the signal 105 subjected to intra-field interpolation processing from the data of this current field. , are manually input to the sample frequency conversion circuit 7 (hereinafter referred to as D/D in the figure).

In the sample frequency conversion circuit 7, the sample rate is 32
．． Signal 10B converted from 4MHz to 48.6MHz
is obtained and supplied to one input terminal of the mixing circuit 10.

On the other hand, the sample frequency conversion circuit 8 changes the sample rate of the signal 102 from 32.4 MHz to 48.4 MHz. eMHz (or 24JMHz) and its output signal 107
A luminance signal (hereinafter referred to as Y) is input to the interfield interpolation circuit 9. In the Y-field interpolation unit 9, the input signal 10
7 is used to generate a signal 108 by interpolating data for four fields between fields, and this signal is supplied to the other input terminal of the mixing circuit 10.

The mixing circuit 10 adjusts the mixing ratio of the signals 108 and 106 according to the motion detection signal from the motion detection circuit 15, outputs the mixed signal as a luminance signal output 114, and supplies it to the matrix circuit 17. There is.

The motion detection circuit 15 detects image motion using the signal 102 and obtains the motion detection signal 112 mentioned above.

In the MUSE signal, the color signal is compressed on the time axis and is line sequential. Therefore, the color signal included in the signal 102 is subjected to time axis expansion by the time axis expansion circuit 12. Furthermore, the color signal included in the signal 105 obtained from the field interpolation circuit 6 is also subjected to time axis expansion in the time axis expansion circuit 11. The color signal 109 obtained by the time axis expansion circuit 11 is supplied to one side of the mixing circuit 14. Further, the color signal 11.0 obtained by the time axis expansion circuit 12 is subjected to inter-field interpolation processing in the inter-color field (hereinafter referred to as "inter-C field") interpolation circuit 13, and the output signal 111 is sent to the mixing circuit 14. supplied to the other input terminal.

The mixing circuit 14 also receives the motion detection signal 1 from the motion detection circuit 15.
13, the mixing ratio of the signals 111 and 109 is adjusted, and the output signal 115 is supplied to the line sequential decoder 16. In the line sequential decoder 16 , the line sequential order of the color difference signal is resolved, and the (RY) signal and the CB-Y) signal become a signal 116 that is synchronized, and is supplied to the matrix circuit 17 .

As a result, the matrix circuit 17 outputs the luminance signal 114.
and color signals 116 to form and output R, G, and B high-definition television signals 117.

The above-described decoder has a frozen image processing function as disclosed in Japanese Utility Model Application No. 61-121083, and when a frozen image is requested, for example, the NR circuit 2 stops input switching and always outputs the signal 104. set to select. Therefore, since the signal 102 is not replaced with a newly received signal, the signal 102 whose contents do not change is repeatedly used to obtain a frozen image. Therefore, no newly received television signal is input to the decoder circuit from the time the frozen image is requested until the frozen image is released.

(Problems to be Solved by the Invention) As explained above, in the conventional MUSE signal decoder circuit, when a frozen image is requested, what kind of video is sent until the frozen image is released? The problem is that I don't understand.

Therefore, the present invention provides a high-definition television receiver that can display what kind of video is currently being sent even during a period when a frozen image is being obtained in a circuit that reproduces the MUSE signal. The purpose is to

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a circuit for creating a child screen to which an input high-definition television signal is always supplied, and from this circuit a circuit for creating a first display for the child screen. A video signal is obtained, and a second display video signal for the main screen is obtained from a main screen creation circuit that can obtain a frozen image, and when a frozen image is requested, a second display video signal from the child screen signal creation circuit is obtained. The first display video signal is inserted into a part of the period of the second display video signal for the main screen.

(Operation) With the above means, even if there is a request for a frozen image, it is possible to know through the sub-screen what kind of image the video signal currently being sent is.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. Input terminal 1 has M
A USE signal is supplied, and this MUSE signal is supplied to the interframe interpolation circuit 5 and the screen reduction circuit 18.

The frame interpolation circuit 5 has N
R circuit 2. The NR circuit 2 is composed of a first field memory 3 and a second field memory 4, and when the received signal is processed in the normal mode, the NR circuit 2 receives the signal 10 from the terminal a.
1 and the signal 1 (14) from the terminal side are switched alternately, and the data 4 fields before is replaced with the input data.However, when a frozen image is requested, the NR circuit 2 is switched from the terminal side. is switched to and held.

The output signal 102 of the NR circuit 2 is supplied to the field interpolation circuit 6, the sample frequency conversion circuit 8, the motion detection circuit 15, and the time axis expansion circuit 12.

The intra-field interpolation circuit 6 extracts data corresponding to the current field from the signal 102, performs intra-field interpolation using the data of the current field, and obtains the signal 105. This signal 105 is supplied to one terminal a of the selection circuit 19. The other terminal of the selection circuit 19 is supplied with the signal 118 for the child screen that has been generated by the screen generation circuit 18, and the selection circuit 19 selects one of them and derives it as the signal 119. . This signal 119 is supplied to the sample frequency conversion circuit 7 and the time axis expansion circuit 11.

The sample frequency conversion circuit 7 converts data with a sample rate of 32.4M)Iz into data with a sample rate of 48.8MHz, and the sample frequency conversion circuit 8 converts data with a sample rate of 32.4M)Iz into data with a sample rate of 48.8MHz.
．． Data with a sample rate of 4MIIz to 484MHz
Or convert it to data with a sample rate of 24.3Ml1z. Output signal 107 of sample frequency conversion circuit 8
is supplied to the Y interfield interpolation circuit 9 and subjected to interfield interpolation, and the resulting signal 108 is supplied to one input terminal of the mixing circuit 10. This mixing circuit 1
The output signal 106 from the sample frequency conversion circuit 7 is supplied to the other input terminal of the sample frequency conversion circuit 7.

The mixing circuit 10 adjusts the mixing ratio of the signals 108 and 106 according to the motion detection signal 112 from the motion detection circuit 15, and derives a signal 114 adapted to the motion. In other words,
In the moving image portion, the proportion of the signal 106 subjected to intra-field interpolation is increased, and in the still image portion, the proportion of the signal 10B subjected to inter-field interpolation is increased.

However, when a frozen image is requested, this mixing circuit 10 functions as a motion adaptive type during the output period of the main screen video signal, as described above, but during the output period of the child screen video signal, , signal 121 are set to fixed values, for example, and are controlled to derive only signal 10B. This is because the selection circuit 20 provided between the motion detection circuit 15 and the mixing circuit 10 is switched to select the fixed value signal 120 from the terminal 21 during the output period of the sub-screen video signal. It is from. Output signal 112 of motion detection circuit 15
is selected by the selection circuit 20 when the video signal for the main screen is output from the mixing circuit 10.

The output signal 114 of the mixing circuit 10 is output to the matrix circuit 17.
is supplied to one terminal of the On the other hand, the time axis expansion circuit 11
expands the time axis of the color signal included in the signal 119 and supplies the output signal 109 to one input terminal of the mixing circuit 14. Further, the time axis expansion circuit 12 expands the time axis of the color signal included in the signal 102 and converts the output signal +10 to C.
It is input to the interfield interpolation circuit 13. This C inter-field interpolation circuit 13 supplies the output signal Ill subjected to intra-field interpolation processing to the other of the mixing circuits 14.

The mixing circuit 14 also receives the detection signal 11 from the motion detection circuit 15.
3, the mixing ratio of the signal 109 and lll is adjusted, and a signal 115 adapted to the movement is derived.

That is, in a moving moving image portion, the proportion of the signal 109 subjected to intra-field interpolation is increased, and in a still image portion, the proportion of the signal 111 subjected to inter-field interpolation is increased.

However, even in this mixing circuit 14, when a freeze image is requested, it is controlled by the signal 123 corresponding to the detection signal 113 during the output period of the main screen video signal, but during the output period of the sub screen video signal. It is controlled by a signal 123 corresponding to a fixed value signal 122. This is because the selection circuit 22 provided between the motion detection circuit 15 and the mixing circuit 14 is switched to select the signal 122 from the terminal 23 during the output period of the child screen video signal.

The output signal 115 of the mixing circuit 14 is sent to a line sequential decoder 16.
supplied to In the line-sequential decoder 16, the line-sequential order of the color difference signal is resolved and the (R-Y) No. 1 and (B-Y) signals are synchronized, and the output signal 116 is sent to the matrix circuit 17.
supplied to The matrix circuit forms and outputs R, G, and B high-definition television signals 117 using the luminance signal 114 and the color signal 116.

As described above, during the video signal output period of the main screen, the selection circuits 19, 20, and 22 are switched to the terminal a side shown in the figure, and during the video signal output period of the child screen, they are switched to the terminal side shown in the figure. , when a frozen image is requested,
The frozen image can be viewed on the main screen, and the image of the video signal currently being sent can be viewed on the sub screen.

FIG. 6 shows an example of the configuration of the screen reduction circuit 18.

The input signal 101 is input to the interpolation filter 30 and is derived as a signal 130 with the aliasing component attenuated. This signal 130 is input to a sub-sampling circuit 31, and as shown in FIG. 7, for example, it is thinned out every three samples in the horizontal direction and every three lines in the vertical direction, and is output as image data 131 of a reduced screen.

FIG. 7 shows a sampling pattern of the MUSE signal, and the black circle portion is data sampled for the reduced screen. Furthermore, in the MUSE signal, the color signals are line-sequential, and when the sub-sample circuit 31 generates image data for a reduced screen, the color signals are set to maintain a line-sequential relationship even in the signal 131. There is.

This signal 131 is written into the field memory 32, 33 and read out as a signal 118 (32.4 MHz rate) during the child screen period. Field memories 32 and 33 are used so that while image data 131 is being written to one, image data 118 is being read from the other. Note that the interpolation filter 30 may be omitted if image disturbance due to aliasing of the child screen is not a concern.

FIG. 2 shows another embodiment of the invention. This example is
In the screen reduction circuit 18, when generating the signal II8 of the reduced screen, the data of the reduced screen of the luminance signal is set to 48.8.
It is configured so that it is output as a signal 124 at a MHz rate and does not need to be passed through the frequency conversion circuit 7. Therefore, in this embodiment, the output signal 124 of the screen reduction circuit 18
A selection circuit 24 is provided for switching between the output signal 106 of the frequency conversion circuit 7 and the output signal 106 of the frequency conversion circuit 7. Then, when a freeze image is requested, the selection circuit 24 selects the signal 124 during the output period of the child screen video signal, selects and derives the signal 10B during the output period of the main screen video signal, and outputs the signal to the mixing circuit. 1
It will be supplied to 0. Note that other parts are the same as those in the embodiment shown in FIG. 1, so the same reference numerals as in FIG. 1 are given.

In this embodiment as well, the same effects as in the embodiment shown in FIG. 1 can be obtained. In this embodiment, the selection circuit 24 is
It may also be provided at a stage subsequent to the interfield interpolation circuit 9, so that the output signal 108 or the signal 124 of this circuit can be selectively switched.

When configured in this way, the mixing circuit 10 is set to derive 100x the signal from its selection circuit.

FIG. 3 shows yet another embodiment of the invention.

When compared to the circuit in FIG. 1, this embodiment has a configuration in which the selection circuit 20 in FIG. 1 is eliminated and the motion detection signal 112 from the motion detection circuit 15 is directly supplied to the control terminal of the mixing circuit 10. ing. Furthermore, in the screen reduction circuit 18,
Brightness signal reduced screen signal 124 (32,4MHz
rate) and a reduced screen signal 118 of the color signal are generated.

The signal 124 is then converted to 48
．． It is converted into a signal 126 with a sample rate of 8 MHz and supplied to a terminal of the selection circuit 27. This selection circuit 2
The output signal 114 of the mixing circuit 10 is connected to the other terminal a of 7.
is supplied. When there is a request for a frozen image, the selection circuit 27 selects the mixing circuit 1 during the video signal output period of the main screen.
The output signal 114 of 0 is selected, and the signal 128 is selected and derived for the video signal output period of the sub-screen, and the matrix circuit 1
Supply to 7. Note that other parts are the same as those in the embodiment shown in FIG. 1, so the same reference numerals as in FIG. 1 are given.

In this embodiment as well, the same effects as in the embodiment shown in FIG. 1 can be obtained. In this embodiment, signal 124 is connected to 48. - When generating at a rate of 4J4 if z, the frequency conversion circuit 26 is not required.

FIG. 4 shows yet another embodiment of the invention.

This embodiment differs from the embodiment shown in FIG. 1 in the path of the output signal 118 of the screen reduction circuit 18. Screen reduction circuit 1
The output signal 1111 of 8 (32.4 MHz rate) is supplied to one terminal of the selection circuit 28.

The other terminal of the selection circuit 28 is supplied with the MUSE signal 101 . The output signal 128 of the selection circuit 28 is configured to be supplied to the terminal a of the NR circuit of the interframe interpolation circuit 5. The output signal 102 of the NR circuit 2 is also supplied to one terminal of a selection circuit 29, and this selection circuit 29 selects either the signal 102 or the output signal 105 from the field interpolation circuit 6. configured to derive.

In the previous example, when a frozen image is requested, N
R circuit 2 was controlled to always select the terminal, but
In this embodiment, when a frozen image is requested, the selection circuit 2 selects terminal A during the video signal output period for the main screen, and selects terminal A during the video signal output period for the child screen. controlled. When a freeze image is requested, the selection circuit 28 selects the signal 101 for the video signal output period for the main screen, and selects the signal 1111 from the screen reduction circuit 18 for the video signal output period for the child screen. Derive. Furthermore, when a freeze image is requested, the selection circuit 29 selects the output signal 105 from the intra-field interpolation circuit 6 during the video signal output period for the main screen, and selects the output signal 105 from the intra-field interpolation circuit 6 during the video signal output period for the child screen. , the output signal 102 from the NR circuit 2 is selected and derived, and controlled to be supplied to the frequency conversion circuit 7 and the color signal time axis expansion circuit 11.

In this embodiment as well, the same effects as in the embodiment shown in FIG. 1 can be obtained. Note that the same parts as in the embodiment of FIG. 1 are given the same reference numerals as in FIG.

In the above embodiment, the selection circuit 29 may be omitted and the output signal 105 of the field interpolation circuit 6 may be used during the video signal output period for the child screen.

However, in this case, during the video signal output period for the sub screen,
The selection circuit 20.2 is configured such that the mixing circuits 10 and 14 derive 100% of the output signal 106 from the frequency conversion circuit 7 and the output signal 109 from the time base expansion circuit 11, respectively.
It is necessary to control via 2.

As explained above, in this embodiment, when the image freezes, the normal MUSE is used during the main screen video signal output period.
Decoding is performed, and in the child screen video signal output period, an output signal is obtained from the latest one field of image data.

FIG. 5 shows yet another embodiment of the invention.

This embodiment is different from the embodiment shown in FIG. 1 in that the motion detection signal 113 from the motion detection circuit 15 is directly supplied to the control terminal of the mixing circuit 14. Further, in this embodiment, the output signal 11B of the line sequential decoder 16 is supplied to the terminal a of the selection circuit 34.
The other terminal of is supplied with a fixed value from terminal 35;
The output signal 133 of this selection circuit 34 is configured to be supplied to the matrix circuit 17.

In this example, if a frozen image is requested, N
The R circuit 2 switches to select the signal 104, and the selection circuits 19 and 34 select the terminal a during the main screen video signal output period.
side, the terminal side is controlled to be selected during the video signal output period for the child screen. Therefore, since the selection circuit 34 selects the terminal side for the video signal of the sub-screen, no color signal is output, only the luminance signal is output, and the sub-screen becomes a monochrome screen.

[Effects of the Invention] As explained above, the present invention shows the configuration of a conventional MUSE decoder which obtains a frozen image as a parent screen when a frozen image is requested, and displays the currently sent image as a child screen. It is a circuit diagram.

2...NR circuit, 3.4...Field memory, 5
...Inter-frame interpolation circuit, 6...Intra-field interpolation circuit, 7,8.26...Frequency conversion circuit, 9...Y
Interfield interpolation circuit, 10.14...Mixed circuit, 1
1.12... Time axis expansion circuit, 13... C-field interpolation circuit, 15... Motion detection circuit, 16... Line sequential decoder, 17... Matrix circuit, 18...
・Screen reduction circuit, 19, 20, 22, 24, 25° 27
．． 28°29.34...Selection circuit.

Claims (6)

[Claims] (1) In a decoder circuit of a high-definition television receiver that demodulates a high-definition television signal that is band-compressed using the sub-sampling method, which is interlaced and goes around in n fields, into the original wideband high-definition television signal. , means to obtain a video signal for a sub-screen by reducing the screen of the video signal that is currently being sent sequentially, and to freeze the image using the output video signal of a holding circuit using field memory when a freeze image is requested. It is characterized by comprising means for obtaining a video signal for the main screen for the image, and a selection means for switching and outputting the video signals for the child screen and the main screen in a child screen period and a main screen period, respectively. A high-definition television receiver. (2) In a decoder circuit of a high-definition television receiver that demodulates a high-definition television signal that has been band-compressed using subsamples that are interlaced and circulate in n fields to the original wide-band high-definition television signal, a first field memory that stores (n/2) fields of compressed high-definition television signals;
/2) a first means having a second field memory for storing fields, and performing interframe interpolation processing on the n fields worth of high-definition television signals; and an output signal from the interframe interpolation means. a second means for performing inter-field interpolation processing on the signal and outputting an inter-field interpolation signal; and performing intra-field interpolation processing on the output signal from the inter-frame interpolation means and outputting an intra-field interpolation signal. a third means for detecting a motion image signal portion of the signal using the output signal from the interframe interpolation means; and a ratio based on the motion detection output from the fourth means. in,
fifth means capable of mixing the inter-field interpolated signal applied to one input and the intra-field interpolated signal applied to the other input; when a frozen image is requested; a sixth means for retaining the contents of the field memory in the insertion processing section and obtaining a video signal for a freeze image; a seventh means for accumulating in a field memory to obtain a video signal for a reduced screen; and switching each output video signal from the fifth means and the seventh means between a main screen period and a sub-screen period. 8th output
A high-definition television receiver characterized by comprising means for. (3) The eighth means supplies the intra-field interpolation signal to the other input terminal of the fifth means during the main screen video signal output period, and supplies the intra-field interpolation signal from the seventh means during the child screen period. a ninth input terminal that supplies a signal for the reduced screen to the other input terminal;
3. A high-definition television receiver according to claim 2, characterized in that it has means for:. (4) The eighth means supplies the output signal from the fifth means to the matrix circuit during the video signal output period for the main screen, and supplies the output signal from the seventh means to the matrix circuit during the video signal output period for the child screen. 3. A high-definition television receiver according to claim 2, further comprising tenth means for supplying an output signal of 1 to the matrix circuit. (5) In a decoder circuit of a high-definition television receiver that demodulates a high-definition television signal that has been interlaced and band-compressed by subsamples circulating in n fields into the original wideband high-definition television signal, a first field memory that stores (n/2) fields of compressed high-definition television signals;
/2) a first means having a second field memory for storing fields, and performing interframe interpolation processing on the n fields worth of high-definition television signals; and an output signal from the interframe interpolation means. a second means for performing inter-field interpolation processing on the signal and outputting an inter-field interpolation signal; and performing intra-field interpolation processing on the output signal from the inter-frame interpolation means and outputting an intra-field interpolation signal. a third means for detecting a motion image signal portion of the signal using the output signal from the interframe interpolation processing means; and a motion detection signal based on the motion detection output from the fourth means. fifth means capable of mixing the inter-field interpolated signal and the intra-field interpolated signal in a ratio, and when a frozen image is requested, retaining the contents of the field memory in the inter-frame interpolator and generating the frozen image; a sixth means for obtaining a video signal for a reduced screen; subsampling and extracting the band-compressed high-definition television signal; storing the extracted signal in a field memory; and obtaining a video signal for a reduced screen. a seventh means; and the fifth means switches the output signal of the field interpolation means which is the third means and the signal of the reduced screen from the seventh means between the main screen period and the child screen period. and controlling the fifth means so that during the child screen period, the fifth means always selects and derives the output signal of the intra-field interpolation means. A high-definition television receiver characterized by comprising the ninth means. (6) In a decoder circuit of a high-definition television receiver that demodulates a high-definition television signal that has been band-compressed using subsamples that are interlaced and circulate in n fields into the original wide-band high-definition television signal, a first field memory capable of storing (n/2) fields of the compressed high-definition television signal; and a second field memory capable of storing (n/2) fields of the band-compressed high-definition television signal. a first means for performing inter-frame interpolation processing on the high-definition television signal for the n fields, and performing inter-field interpolation processing on the output signal from the inter-frame interpolation means; a second means for performing intra-field interpolation processing on the output signal from the inter-frame interpolation means and outputting an inter-field interpolated signal; fourth means for detecting a motion image signal portion of this signal using the output signal from the interpolation means; and a ratio based on the motion detection output from the fourth means;
fifth means capable of mixing the inter-field interpolated signal applied to one input and the intra-field interpolated signal applied to the other input; when a frozen image is requested; a sixth means for retaining the contents of the field memory shown in the insert and obtaining a video signal for a frozen image; a seventh means for accumulating in a memory to obtain a video signal for a reduced screen; and an eighth means for switching and supplying the input signal of the first field memory of the interframe interpolation means to the interframe interpolation means for the child screen, and inputting the input signal of the first field memory of the interframe interpolation means to the second field memory during the main screen period. and a ninth means for switching the output signal of the field interpolation means to the output signal of the eighth means during the child screen period, and switching the output signal of the field interpolation means to the output signal of the other of the fifth means during the main screen period. tenth means for supplying the output of the interframe interpolation means to the other input section of the fifth means during the child screen period; and eleventh means for controlling said fifth means to select and derive only the signal of the input section of said high-definition television receiver.