JP2624745B2 - High Definition Television Receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention demodulates a band-compressed high-definition television signal into an original wideband high-definition television signal and reproduces the same. The present invention relates to a receiver and particularly to a decoder circuit for obtaining a good image when a frozen image is obtained.

(Prior Art) As a method of band-compressing a wideband high-definition television signal to a practical level for transmission, the original high-definition television signal is converted into four bands.
MUSE (Multip
le Sub-Nyqist Sampling Encoding) method (“MUSE, a new transmission method for high-definition television”, NHK Giken Monthly Report, Ninomiya,
(Vol. 27, No. 7, 1984).

FIG. 5 shows a band-compressed high-definition television signal (hereinafter referred to as MU).
FIG. 1 shows a decoder for demodulating an SE signal into an original wideband high-definition television signal.

The input terminal 1 is supplied with a MUSE signal (2), and the MUSE signal (2) is input to the inter-frame interpolation unit 6 as a signal (5) via the switch 3 which is closed during normal demodulation. The switch 3 is turned off when a signal requesting a freeze image for freeze playback is input to the terminal 4 and a new signal is output.
The input of the MUSE signal to the inter-frame interpolation unit 6 is prohibited.

In the frame interpolating unit 6, a signal one field before the input signal (5) and a signal three fields before the input signal (5) are interpolated in the field memory 9 to generate a signal (10). The signal (12) is created by interpolating the signal and the signal four fields before. Then, in the input switching circuit 7, the signal four fields before included in the signal (12) is replaced with a new input signal (5), that is, the signal (8) in which the current signal and the signal two fields before are interpolated between frames. ).

The signal (8) is supplied to a field interpolation unit 17 for field interpolation. The field interpolation unit 17
A field-interpolated signal (18) is generated from the data of the current field and supplied to the mixing circuit 51. The inter-field interpolation unit 47 delays the signal (8) by the delay line of the field interpolation unit 17 by an amount corresponding to the delay amount in the field interpolation unit 17 (for example, the luminance signal is 2H and the chrominance signal is 4H). , H is one horizontal period) and the signal (46) is input. The inter-field interpolating unit 47 interpolates data for four fields using the signal (46) to obtain a signal (48) and supplies it to the mixing circuit 51. The motion detection section 49 detects an image motion using the signal (8) and obtains a motion detection signal (50). The mixing circuit 51 outputs a signal (1) at a ratio corresponding to the motion detection signal (50).
Mix 8) and (48). In the case of a moving image, the ratio of the signal (18) increases, and in the case of a still image, the ratio of the signal (48) increases.

The above-mentioned decoder has a freeze function as disclosed in Japanese Utility Model Laid-Open Publication No. Sho 61-121083. When a freeze image is requested, the switch 3 is turned off by a freeze signal supplied to the terminal 4 and a new signal (2) is inhibited from being input to the interframe interpolation unit 6. Input switching circuit 7
Stops input switching, selects only the output signal (12) of the field memory 11, and derives it as the signal (8). As a result, the four fields of data in the field memories 9 and 11 are cyclically processed and held, and a high-definition television signal of a frozen image can be obtained at the output unit 52.

However, in the above-described circuit, the image data of the same field is always transmitted as the signal (8) during the period in which the freeze image is requested.
Is not always output. Therefore, when there is a motion in the stored original image, the frozen image causes flicker at the moving portion.

(Problems to be Solved by the Invention) In a conventional MUSE decoder, when a freeze image is requested, a flicker failure occurs in a moving portion of the freeze image, and the image quality may be degraded.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-definition television receiver capable of obtaining a high-quality freeze image without flickering.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides the first and second methods when a frozen image is requested.
Means for inhibiting writing of high-definition television signals to the frame interpolating means having the second field memory is provided. Switching means for alternately inputting the output of the first field memory and the output of the second field memory for each field as an input signal to the field interpolation means constituting the demodulation unit is provided. Further, the signal input to the inter-field interpolation means is input by delaying the luminance signal and the chrominance signal so as to match the delay amount of the inter-field interpolation means. Using the normal signal of the line corresponding to the interlace, an auxiliary signal of a line not corresponding to the line is formed for the luminance signal and the chrominance signal, and the auxiliary signal and the normal signal are selectively switched for each field and derived. Is supplied to the mixing means as a final signal subjected to field interpolation processing.

(Operation) When a frozen image is requested by the above means,
Since a field signal having the same content is always taken out from the inter-frame interpolation section and supplied to the frame interpolation section, flickering may occur even if a moving portion is stored in the memory of the frame interpolation section. There is no. In addition, since the interlace correction for the interlace is separately performed for the luminance signal and the chrominance signal, it is possible to obtain a high-quality frozen image without causing flicker due to interlace even if the same data is repeatedly used as a frozen image. it can.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. A MUSE signal (2) supplied to an input terminal 1 is input to a frame interpolator 6 via a switch 3 which is turned on during a normal operation. The frame interpolating section 6 has an input switching circuit 7, a field memory 9, and a field memory 11 in a cyclic manner, and has a configuration similar to that described with reference to FIG.

In the present apparatus, when the signal from the inter-frame interpolation section 6 is supplied to the field interpolation section 17, the input side signal (8) and the output side signal (10) of the field memory 9 are selected by a selector.
13 can be supplied selectively. The field interpolation unit 17 generates a field-interpolated signal (18) from the data of the current field, and
To supply.

When a freeze image is requested, switch 3 is connected to terminal 4
Is turned off by the freeze signal given to the input switching circuit 7, and the input switching circuit 7 enters a state where only the signal (12) from the frame memory 11 is selected. Further, when the freeze signal is supplied to the terminal 14, the selector 13 alternately selects the signals (8) and (10) for each field in response to the field switching signal supplied to the terminal 15, and It is supplied to the interpolation section 17. Therefore, a signal having the same content is always tracked and introduced into the field interpolation unit 17.

The MUSE signal (2) is an interlaced signal. Therefore, if the same signal is always selected by the selector 13, the relevant line and the non-relevant line become the image data of the same line, and the signal (18) is not an interlaced signal. If this is projected as it is, one line flicker will occur.

Therefore, in the present embodiment, the signal (18) is supplied to the interlace correction circuit 19 to reproduce the interlaced signal (38). Interlace correction circuit 19
Has an interlace correction system for luminance signals and an interlace correction system for color signals. The luminance signal interlace correction circuit includes a 1H delay line 20 and an adder 22.
22 adds and averages the signal (21) and the signal (18) from the 1H delay line 20 to obtain a signal (23). The signal (23) and the previous signal (18) are derived by switching over each field by the selector 24 when a freeze image is requested. Note that during normal demodulation processing, the selector 24 selects and derives only the signal (18). Selector 24 is connected to terminal 25
When the freeze signal is supplied to the terminal 26, the signals (23) and (1) are responded to the field switching signal supplied to the terminal 26.
8) are alternately selected and derived, and when no freeze signal is given, only the signal (18) is selected and derived. The output signal (27) of the selector 24 is supplied to the selector 36.

On the other hand, the color signal interlace correction circuit uses a 2H delay line 2
8, an adder 30 and a selector 32 are provided.

As shown in FIG. 4, the color signals in the MUSE signal are transmitted in a line-sequential manner by switching between a _CW signal and a CN signal, which are color difference signals, line by line. Now, the line (b, d, f, h) shown by a solid line in FIG. 4 is the line corresponding to interlace, and the line (a, c, e, g) shown by a broken line is a line not relevant. And Lines a, b, e, and f are CW
The signals c, d, g, and h are assumed to be CN signals. At the time of image freeze, the line of the solid line may be used as it is in the field of the line, but in the next non-relevant field, a signal of the dashed line is newly generated from the signal of the solid line input again. I need to do it. At this time, for example, if a CW signal indicated by a dotted circle in the figure is to be generated, a line b
It is made by adding the signals of f and f at a ratio of 1: 3. Therefore, when the signal of the line f is input, the signal of the line b needs to be delayed by two line periods and added.

To perform the above processing, the color signal line correction system
A 2H delay line 28 is provided. The selector 32 uses the signal (18) as it is in the field for deriving the solid line in FIG. 4, and when deriving the signal for the dashed line in FIG. 4, the selector 32 outputs the signal from the adder 30 obtained by the above-described principle. The signal (31) is selected and derived. Therefore, even when the image is frozen, the color signal (35) derived from the selector 32 becomes a signal having an interlace relationship and is supplied to the selector 36. The selector 32 is controlled to select only the signal (18) during normal reproduction. That is, when there is no freeze signal at the terminal 33, only the signal (18) is selected and derived, and when the freeze signal is supplied to the terminal 33, the signal (18) is changed to the signal (18) by the field switching signal given to the terminal 34. (31) are alternately selected for each field, and are derived as a signal (35).

The selector 36 selects and derives the signal (27) during the luminance signal period of the MUSE signal, and selects and derives the chrominance signal (35) during the chrominance signal period, based on the timing signal supplied to the terminal 37. As described above, the signal (18) from the field interpolation unit 17 is interlace-corrected independently for both the luminance signal and the chrominance signal by the interlace correction circuit 19, and becomes the field interpolation signal (38). Supplied.

Next, in the present apparatus, the signal (46) supplied to the inter-field interpolation unit 47 is a signal obtained by delaying the signal (8) by the delay circuit 39.

The signal (46) input to the inter-field interpolation section 47 needs to be delayed by the amount corresponding to the signal delay of the previous field interpolation section 17. Conventionally, the field interpolation
The delay line of 17 ensures a delay of, for example, the luminance signal 2H and the chrominance signal 4H. However, in the present embodiment, at the time of image freeze, since each field signal input to the field interpolation unit 17 is a signal interpolated between the same frames, the delay line in the field interpolation unit 17 If the output is used as an input of the inter-field interpolation section 47, normal inter-field interpolation cannot be obtained.

In this embodiment, the 2H delay line 40, the 4H delay line 42, and the selector 44 are used to obtain a signal (46) corresponding to the delay amount of the field interpolation unit 17 and supply the signal (46) to the interfield interpolation unit 47. The signal (46) is obtained by the delay circuit 39. Selector 44
Is controlled by a timing signal applied to a terminal 45, and during the luminance signal period, the output signal (4
1) is selected and derived, and during the color signal period, the output signal (43) of the 4H delay line 42 is selected and derived. The signal (46) is subjected to inter-field interpolation processing in an inter-field interpolation section 47,
The signal is derived as a signal (48) and supplied to the mixing circuit 51.

The mixing circuit 51 controls and mixes the ratio between the signals (38) and (48) according to the motion detection signal (50), and outputs a high-quality video signal to the output terminal 52. The motion signal is detected by the motion detection unit 49 using the signal (8).

FIG. 2A shows another embodiment of the interlace correction circuit 19, and FIG. 2B shows another embodiment of the delay circuit 39. When performing interlace correction, the luminance signal period and the chrominance signal period can be distinguished in the MUSE signal, so the 1H delay lines 53 and 54 are connected in series, and the 1H delay line 53 is used for luminance signal line correction and color signal line correction. It is used for both times. That is, the 1H delay signal (21) and the signal (18) are added to each other.
22 and the output signal of the 2H delay line 54 and the signal (18) are supplied to the adder 30. With this configuration, the line correction signal of the luminance signal at the time of requesting the freeze image is obtained from the adder 22, and the line correction signal of the color signal is obtained from the adder 30. The selectors 24, 32, 36 are controlled in the same manner as in the previous embodiment.

FIG. 9B shows another embodiment of the delay circuit 39. In this example, 2H delay lines 55 and 56 are connected in series, and 2H delay line 55 output signal (41) and 2H delay line 56 output signal (43) (signal (8)
Is delayed by 4H) to the selector 44. The selector 44 outputs the signal (41) during the luminance signal period.
Is selected and the signal (43) is selected during the color signal period, as in the previous embodiment.

FIG. 3 shows still another embodiment of the interlace correction circuit 35.

In this embodiment, the 1H delay lines 53 and 55 are connected in series, the output (21) of the 1H delay line 53 and the signal (18) are added by the adder 22, and the output of the adder 22 is supplied to one of the selectors 55. Supply. The selector 55 selects and derives the signal (23) during the luminance signal period when the timing signal is supplied to the terminal 55 and supplies it to the selector 58 as the signal (57). When a freeze image is requested, the selector 58 alternately selects and derives the signal (57) and the signal (18) for each field by the field switching signal supplied to the terminal 60, and performs interlace correction. Deriving a luminance signal. In the color signal period, the output signal (29) of the 1H delay line 54 and the signal (18) are added by the adder 30, and the added signal (31) is supplied to the other input of the selector 55. The selector 55 selects and derives the signal (31) under the control of the timing signal during the color signal period.
Therefore, the output signal (57) of the selector 55 becomes an interlace correction signal of the color signal and is supplied to the selector 58. When a freeze image is requested, the selector 58
As described above, the signal (57) and the signal (18) are alternately selected and derived for each field, and the interlaced signal (38) is output.

[Effects of the Invention] As described above, according to the present invention, even when a freeze image is requested, a high-definition television receiver capable of eliminating a flicker obstacle and obtaining a high-quality freeze image can be obtained. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 (a) is a diagram showing another embodiment of the interlace correction circuit of FIG. 1, and FIG. 2 (b) is a delay of FIG. FIG. 3 is a diagram showing another embodiment of the circuit, FIG. 3 is a diagram showing another embodiment of the interlace correction circuit, FIG. FIG. 1 is a block diagram showing a conventional MUSE decoder. 3 ... MUSE signal, 6 ... frame interpolation unit, 7 ... input switching circuit, 9, 11 ... field memory, 13, 24, 32, 36,
44… Selector, 17… Field interpolation unit, 19… Interlace correction circuit, 20, 53, 54… 1H delay line, 28, 40,
55, 56: 2H delay line, 22, 30, adder, 42: 4H delay line, 47: interpolator between fields, 49: motion detector, 51
…… mixed circuit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Fumio Minami 8-8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Home Appliances Research Laboratory, Toshiba Yokohama Works (56) References JP-A-62-104386 (JP, A JP-A-64-60081 (JP, A) JP-A-64-60173 (JP, A) JP-A-6-1121083 (JP, U)

Claims (2)

(57) [Claims] 1. A high-definition television signal which is band-compressed by sub-samples interlaced and loops in n fields and in which color signals are line-sequentially inputted, and stores n / 2 fields of the high-definition television signal. Frame interpolating means for serially interpolating between the first and second field memories and circulating through the signals of the first and second field memories. Means for performing field interpolation on the high-definition television signal output from the means, and a field for performing field interpolation on the high-definition television signal from the field interpolation means Interpolation means; motion detection means for obtaining an image motion detection signal using the high-definition television signal from the frame interpolation means; In a decoder circuit comprising a mixing means for mixing the output of the inter-field interpolation means and the output of the field interpolation means at a ratio based on the motion detection signal, when a freeze image is requested, Means for inhibiting a new high-definition television signal from being written to the field memory; and, when the freeze image is requested, the first field memory as the input signal to the field interpolation means. Switching means for alternately inputting the output and the output of the second field memory for each field; and using a normal signal of the line corresponding to the interlace from the field interpolation means to select a line not corresponding to the line. Auxiliary signals are created for the luminance signal and the chrominance signal, respectively, and the auxiliary signal and the normal signal are selectively switched for each field. High definition television receiver, characterized by comprising the interlaced auxiliary means for supplying the derived said mixing means Te. 2. When the freeze image is requested, a signal input to the interpolating means is delayed by a luminance signal and a chrominance signal so as to correspond to a delay amount of the interpolating means. 2. The high-definition television receiver according to claim 1, further comprising delay means for inputting the input signal.