JPH02255928A - Addressing device - Google Patents

Abstract

PURPOSE:To improve the memory efficiency by securing a constitution where a subaddress signal generating circuit outputs a subaddress signal to designate a relative address of the area to receive an access among the prescribed areas of a memory specified by an address signal. CONSTITUTION:When the instruction decoded by an instruction decoding circuit 1 is equal to a read-back instruction of the address data, an address control circuit 2 controls an address signal generating circuit 6 and a subaddress signal generating circuit 7 and outputs the data on both circuits 6 and 7 to an internal bus 5. In addition, the circuit 2 controls an address data exchange circuit 4 and outputs the data sent to the bus 5 to an internal CPU bus 3. Then the circuit 2 completes an instruction if a conditional flag F sent from a memory shows an end state. In such a way, the output of a subaddress signal is possible in order to designate a relative address of the area to receive an access. Thus the memory can be addressed for each desired bit and the memory efficiency is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an addressing device capable of addressing a memory in units of a predetermined number of bits, for example 8 bits, 16 bits, 32 bits or 64 bits.

[Prior Art] Figure 4 shows a memory and peripherals controlled by a microprocessor that processes data in 32-bit units, such as the Motorola 32-bit Microprocessor rMc68020 (trademark) (hereinafter simply referred to as a microprocessor). FIG. 3 is a diagram showing connections with devices. In Figure 4, 1
0 is memory that can read and write data in 32-bit units.
11 is a 32-bit data bus, and 12 is a peripheral device such as an LSI.

This microprocessor (not shown) has a so-called dynamic bus size function that allows the 32-bit data bus 11 to be individually controlled by strobe signals every 8 bits. Therefore, depending on the data processing unit of the peripheral device l2, the memory 10 can read and write data in units of 8 bits, 16 bits, or 32 bits.

When the peripheral device 12 processes data in bytes, the microprocessor uses the lower bits 0 to 7 of the data bus 11 to transfer data in bytes to the peripheral device 12 .

Further, since data cannot be directly exchanged between the peripheral devices connected to the upper bit side of the data bus 11 and the peripheral devices connected to the lower bit side, data is exchanged via the microprocessor.

[Problems to be Solved by the Invention] The microprocessor described above can be operated efficiently because peripheral devices that process data in units of 8 bits, 16 bits, or 32 bits can be placed in the same system.

However, when using a peripheral device 12 that processes data in bytes, the data bus 11
Since only the lower 8 bits are used and the other 24 upper bits are not used, there is a problem that the efficiency of the system as a whole is poor.

Also, since data cannot be directly exchanged between the peripheral devices connected to the upper bits of the data bus and the peripheral devices connected to the lower bits, the microprocessor must mediate the transfer of data. There was a problem in that it took time to send and receive data, and prompt data processing was not possible.

The present invention has been made to solve the above problems,
The object of the present invention is to provide an addressing device capable of 8-bit, 16-bit, 32-bit or 64-bit addressing.

[Means for Solving the Problems] An addressing device according to the present invention includes an instruction decoding circuit that decodes an instruction related to address control and outputs a decoded signal, and based on the instruction related to address control,
an address signal generation circuit that outputs an address signal for addressing in longword units; an addressing control signal generation circuit that outputs an addressing control signal that specifies the number of bits to be accessed by the address signal based on an instruction regarding address control; A sub-address signal generating circuit is provided which outputs a sub-address signal specifying a relative address in a predetermined area of the memory specified by the address signal based on a command regarding address control.

[Function] In the addressing device configured as described above, when the instruction decoding circuit decodes an instruction related to address control, the address signal generation circuit outputs an address signal for addressing in longword units, and the addressing control signal generation circuit performs addressing control. A subaddress signal generation circuit outputs a subaddress signal.

Using this address signal, addressing control signal, and subaddress signal, the memory can be addressed in desired bit units.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of an addressing device according to an embodiment of the present invention. In FIG. 1, 1 is an instruction decode circuit that decodes instructions, 2 is an address control circuit, and 3 is an instruction decode circuit that decodes instructions.
is the internal CPU bus, 4 is the address/data exchange circuit, and 5 is the internal CPU bus.
6 is an internal bus, 6 is an address signal generation circuit that outputs address signal A, 7 is a subaddress signal generation circuit that outputs subaddress signal SA, and 8 is addressing control signal S.
This is an addressing control signal generation circuit that outputs C.

The instructions decoded by the instruction decoding circuit 1 include instructions related to address control, such as an address data set instruction and an address data read pack instruction.

In addition to these instructions, there are instructions for incrementing or decrementing the address data of the address signal generation circuit 6 and the subaddress signal generation circuit 7.

The address control circuit 2 performs an address control circuit 2 based on a decode signal and a condition flag signal F from a memory (not shown).
The data exchange circuit 4, address signal generation circuit 6, subaddress signal generation circuit 7, and addressing control signal generation circuit 8 are controlled.

Under the control of the address control circuit 2, the address/data exchange circuit 4 selects address data from the instruction field or the internal CPU bus 3 when the instruction decode circuit 1 decodes the instruction, modifies the selected data, and converts the address Signal generation circuit 6 and subaddress signal generation circuit 7
Output to.

Since the data on the data bus is arranged from the LSB side to the bottom, this modification is performed to align the data position with the memory (not shown).

The address/data exchange circuit 4 also has a function of reading back address data from the address signal generation circuit 6 and the subaddress signal generation circuit 7.

Address signal generation circuit 6 operates under the control of address control circuit 2, and generates address signal A in longword units based on data input from address/data exchange circuit 4 via internal bus 5.

Further, the address signal generation circuit 6 has a function of incrementing or decrementing the address signal A in addition to storing the address data outputted from the address/data exchange circuit 4 to the internal bus 5.

Under the control of the address control circuit 2, the addressing control signal generating circuit 8 outputs a 3-bit addressing control signal AC that provides timing for determining the address signal A1 and the sub-address signal SA.

This addressing control signal AC is composed of an address strobe signal and an access code signal. Address strobe signal indicates permission/disapproval of memory access1
This is a bit signal. Further, the access code signal is a 2-bit signal indicating whether to access the memory among longword access, word access, halfword access, or byte access.

Table 1 is a table showing the meaning of the addressing control signal AC.

Table 1 As shown in Table 1, the address strobe signal is rHJ
At this time, address signal A1, subaddress signal SA, and access code are inactive. Also, when the address strobe signal is rLJ, the access code is "0".
Longword access, word access, halfword access, or byte access corresponds to "0", "01", "10", or "11", respectively.

Note that longword access, word access, halfword access, and byte access are 8-byte, 4-byte, 2-byte, and 1-byte data accesses.

Subaddress signal generation circuit 7 outputs a 3-bit subaddress signal SA under the control of address control circuit 2. This sub-address signal SA indicates a relative address within the ten word specified by address signal A.

Table 2 is a table showing the meaning of subaddress signal SA.

× × Don't Care Table 2 As shown in Table 2, the combination of the sub address signal SA and the addressing control signal AC causes the address signal A to be
Of the 64-bit area of memory identified in
．． This means that 1B or 8-bit areas can be addressed.

FIGS. 2(a) to 2(n) are diagrams showing areas (shaded areas) that are addressed according to the logical conditions of the addressing control signal AC and the sub-address signal SA. For example, the addressing control signal AC is rL 10J, and the subaddress signal SA whose upper 2 bits are valid is ro 1
In the case of XJ, the area from the 47th bit to the 32nd bit will be addressed (see Figure 2(d)).
.

The sub-address generation circuit 7 not only stores the address data output from the address/data exchange circuit 4 to the internal bussler, but also has the function of incrementing or decrementing the sub-address signal SA.

When the subaddress signal SA is incremented and a carry occurs, the address signal generation circuit 6 increments the address signal A. This is the sub address signal SA
The same is true when decrementing .

Next, the operation of the addressing device shown in FIG. 1 will be explained with reference to the flowchart shown in FIG.

(1) Step Sl The instruction decode circuit 1 decodes the instruction and outputs a decode signal to the address control circuit 2. Address control circuit 2
The instruction decoded by the instruction decoding circuit 1 is an address data set instruction, an address data read pack instruction,
Or, it is determined whether the instruction is an address data increment/decrement instruction (step 82). Processes from steps 83 to S8 are executed depending on the type of instruction.

(2) Steps 82 to S6 When the decoded instruction is an address data set instruction, the address control circuit 2 performs the following steps based on the decode signal.
Whether the data to be set is in the instruction field or not
It is determined whether the data is being output to the PU bus 3, and the address/data exchange circuit 4 is controlled to determine the data bus (step 93).

In this case, the address control circuit 2 performs data modification to adjust the data to an appropriate bit width and bit position.

The address/data exchange circuit 4 uses the data in the instruction field or the internal CPU according to the control of the address control circuit 2.
The data being output to the bus 3 is selectively output to the internal bus 5.

The address control circuit 2 controls the address signal generation circuit 6 and the sub-address signal generation circuit 7, and causes the address signal generation circuit 6 and the sub-address signal generation circuit 7 to take in the data selectively output to the internal bus 5 (step 84).
.

Address signal generation circuit 6 and subaddress signal generation circuit 7 output address signal A and subaddress signal SA, respectively, based on the captured data.

The address control circuit 2 controls the addressing control signal generation circuit 8 and notifies the memory side of the determination of the address (
Step 85).

When the condition flag F output from the memory indicates the completion of preparation (step S6), the addressing control signal AC is made inactive to complete one instruction.

When the decoded instruction is an increment/decrement instruction, the address control circuit 2 does not control the address/data exchange circuit 4, but controls the address signal generation circuit 6 and sub-address signal generation circuit 7 to increment or decrement the data. Execute.

When the address signal generation circuit 6 increments or decrements the data, the address signal A indicating address A becomes address A+1 or address A-1.

Similarly, when the sub-address signal generating circuit 7 increments or decrements data, the relative sub-address SA within the area indicated by the address signal A becomes S
It becomes address A+1 or address SA-1.

Note that the address signal generation circuit 6 and the sub-address signal generation circuit 7 do not increment/decrement the address signal A and the sub-address signal SA, respectively, but add/subtract desired values, thereby increasing the degree of freedom in memory access. You can also do that.

(3) Steps 87 to S8.9B If the decoded instruction is an address data read pack instruction, the address control circuit 2 controls the address signal generation circuit 6 and the sub-address signal generation circuit 7 to generate an address signal. Circuit 6 and subaddress signal generation circuit 7
data is output to the internal bus 5 (step S7).

Further, the address control circuit 2 controls the address/data exchange circuit 4 to output the data output to the internal bus 5 to the internal CPU bus 3 (step S8).

The address control circuit 2 completes one instruction when the condition flag F output from the memory indicates completion (step 9B).

In this embodiment, an addressing device that can address memory in 8-bit, 18-bit, 32-bit, or 64-bit units has been described, but the addressing unit can be changed, for example, if necessary, the address can be controlled in 1-bit units. good.

Further, in this embodiment, an addressing device applied to a CPU has been described, but the present invention may also be applied to a CRT controller or the like that handles image data. Since the addressing device can specify a desired relative address and number of bits within a predetermined area specified by address signal A, CR
By applying it to the T controller, it becomes possible to display images with added gradations.

Further, the operations of the addressing device and the memory may be synchronized by vibration line control instead of the condition flag F.

Furthermore, by appropriately combining these, an addressing device suitable for the purpose can be obtained.

[Effects of the Invention] As described above, according to the present invention, the address signal generation circuit outputs an address signal for addressing in units of long words, and the addressing control signal generation circuit outputs a predetermined memory address signal specified by the address signal. Outputs an addressing control signal that specifies the number of bits to be accessed out of the area, and the subaddress signal generation circuit specifies the relative address of the area to be accessed out of the predetermined area of the memory specified by the address signal. Since the signal is output, an addressing device that can address the memory in desired bit units and improve memory efficiency can be obtained.

Furthermore, since the data width is determined by the addressing mode, handling of variable length data becomes easier.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an addressing device according to an embodiment of the present invention, FIG. 2 is a diagram showing the meaning of the sub-address signals shown in FIG. 1, and FIG. 3 is a block diagram of the addressing device shown in FIG. 1. Flowchart showing the operation, Figure 4 is 32
FIG. 2 is a connection diagram between memory and peripheral devices controlled by a BIT microprocessor. DESCRIPTION OF SYMBOLS 1... Instruction decode circuit, 2... Address control circuit, 3... Internal CPU bus, 4... Address data conversion circuit, 5... Internal bus, 6... Address generation circuit, 7... ...Sub address generation circuit, 8...Addressing control signal generation circuit.

Claims (1)

[Claims] An instruction decoding circuit that decodes an instruction related to address control and outputs a decoded signal; and an address signal generation circuit that outputs an address signal for addressing in longword units based on an instruction related to address control. , an addressing control signal generation circuit that outputs an addressing control signal specifying the number of bits to be accessed out of a predetermined area of the memory specified by the address signal based on the instruction regarding address control; 1. An addressing device comprising: a sub-address signal generation circuit that outputs a sub-address signal specifying a relative address in a predetermined area of a memory specified by the address signal.