JPH0225572B2 - - Google Patents

Abstract

PURPOSE:To improve the confidentiality by providing a gate circuit operating an exclusive OR between a signal from a memory and a burst signal so as to prevent the leak of content of communication when a channel other than a designated channel is designated because of mis-operation. CONSTITUTION:A clock pulse from transmission interface circuits 1-1a-3-1a at the transmission side is counted by address counters 1-2a-3-2a and the result is given as a read address of memories 1-3a-3-3a transmitting a pattern different from each channel. The exclusive OR between the signal from the memories 1-3a-3-3a and the burst signal from the circuits 1-1a-3-1a is conducted by exclusive OR gates 1-4a-3-4a and the result is given to a time division multiplex circuit 101. The output of the circuit 101 is inputted to the exclusive OR gates 1-4b-3-4b at the reception side and exclusively ORed with an output of the memories 1-3b-3-3b read by being addressed by address counters 1-2b-3-2b. Thus, the leak of content of communication due to the misoperation is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a simple method for preventing the contents of other channels from leaking to others when a channel other than the assigned channel is erroneously specified in a time division multiplex communication device. It concerns the secret circuit.

1 and 2 are a block diagram showing an outline of a time division multiplexing communication device to which the present invention is applied, and a timing chart showing the timing of signals in each part.On the transmitting side, the transmitting interface circuit 1-
Input signals 10a, 20 at 1a, 2-1a...
a... into a burst signal, and this burst signal 1
1a(a), 21a(b),... to the channels CH1, CH2,... of the time slots assigned to each of the transmission interface circuits 1-1a, 2-1a,... 101, and in the time division multiplexing circuit 101, the burst signal 11
a(a), 21a(b),... as time division multiplexed signal 102(d)
It is to be sent out after that.

On the receiving side, in a plurality of receiving interface circuits 1-1d, 2-1d, etc., to which this time division multiplexed signal 102(d) is commonly given, each receives the time slot channel assigned to it.
Only the signals of CH1, CH2, . . . are separated and sent out as output signals 10b, 20b, .

Note that in this device, since communications of multiple channels are transmitted via one common transmission path, the received signals given to the receiving interface circuits 1-1b, 2-1b,... Signals other than the channels specified are also multiplexed and included.

Therefore, the reception interface circuit 1-1b,
In 2-1b, . . . , if a channel other than the originally assigned channel is erroneously designated, the content of the signal of the erroneously designated channel is sent out as an output signal, causing crosstalk.
That is, for example, the reception interface circuit 1
When channel CH1 is assigned to -1b, the signal of channel CH1 is received from the time division multiplexed signal 102, but if channel CH2 is specified, the receiving interface circuit 1-1b
Channel CH2 of the time division multiplexed signal 102
signals, easily causing crosstalk.

The present invention has the purpose of solving the above problems,
An address counter that counts the clock pulses of the transmitting interface circuit, a memory that receives a read address specified by the count output of this address counter and sends out a signal with a different pattern for each channel, and a signal from this memory and a burst signal. An exclusive OR gate is provided on the transmitting side for each transmitting interface, which receives the input and sends the output to the time division multiplexing circuit, and an address counter that counts the clock pulses of the receiving interface circuit, and a count of this address counter. A memory that receives a read address specified by its output and sends out a signal with the same pattern as the memory of the corresponding channel on the sending side, receives the signal from this memory and a time division multiplexed signal as input, and sends the output to the receiving interface circuit. The present invention provides an extremely effective simple confidential communication circuit for a time division multiplex communication device in which an exclusive OR gate is provided on the receiving side for each receiving interface circuit.

The details of the present invention will be explained below with reference to the block diagram of FIG. 3 showing an embodiment.

This figure is basically the same as FIG. 1, but on the sending side, memories 1-3a and 2-3 using ROM etc.
Address counters 1-2a, 2 which count the clock pulses 14a, 24a, . . . of the transmission interface circuits 1-1a, 2-1a, . -2a,... count output 1
5a, 25a, ... receive the read address designation, and the signals 12a, 2 of different patterns are received.
2a,..., and perform exclusive OR (hereinafter,
EXOR) is applied to one input of gates 1-4a, 2-4a, .

The other input of the EXOR gates 1-4a, 2-4a,... is connected to the transmission interface circuit 1-1.
Burst signals 11a, 2 from a, 2-1a, ...
1a,... are given, EXOR conditions for both inputs are taken, and these output signals 13a, 2
3a, . . . are sent to the time division multiplexing circuit 101.

On the other hand, on the receiving side, memory 1-3 such as ROM
b, 2-2b, ... memory 1-3a, 2-3a,
Address counters 1-2b, 2-2b, . . . store signals of the same pattern corresponding to the clock pulses 14b, 24b, .
A read address is specified by the count outputs 15b, 25b, . . . of the EXOR gates 1-4b, 2-4b, .
... to the inputs of EXOR gates 1-4b,
If we take the EXOR condition in 2-4b,..., the burst signals 11a, 21a,... on the transmitting side are EXOR.
Output signal 11 of gates 1-4b, 2-4b,...
b, 21b, . . .

Therefore, taking the receiving interface circuit 1-1b as an example, if a channel other than the assigned channel CH1, for example, channel CH2, is designated, then a channel from among the time division multiplexed signals 102 is designated.
Among CH1, CH2, ..., the signal of channel CH2 is selected, but the pattern of signal 12b sent from memory 1-3b is that of channel CH2.
Since the pattern of the signal 22a sent from the memory 2-3a is different from that of the EXOR gate 1-4, the
The output signal 11b from the transmitter b is a different signal from the burst signal 21a on the transmitting side, making it possible to prevent crosstalk.

As is clear from the above explanation, according to the present invention, even if a channel other than the assigned channel is specified due to an erroneous operation, the contents will not be leaked, and this is effective in maintaining the confidentiality of the communication contents. Remarkable effects can be obtained in time division multiplexed communication devices.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an overview of the conventional example;
This figure is a timing chart showing the signals of each part in FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the present invention. 1-1a, 2-1a, 3-1a...transmission interface circuit, 1-1b, 2-1b, 3-1b
...Reception interface circuit, 1-2a, 2-
2a, 3-2a, 1-2b, 2-2b, 3-2b
...Address counter, 1-3a, 2-3a, 3
-3a, 1-3b, 2-3b, 3-3b...Memory, 1-4a, 2-4a, 3-4a, 1-4b,
2-4b, 3-4b...EXOR (exclusive OR)
Gate, 101...Time division multiplexing circuit.

Claims (1)

[Claims] 1. A plurality of transmitting interface circuits that convert input signals into burst signals and transmitting the converted signals to assigned channels, and a time division multiplexing circuit that transmits the burst signals from each of the interface circuits as time division multiplexed signals. A time division multiplexing communication device comprising a transmitting side consisting of a transmitting side, and a receiving side consisting of a plurality of receiving interface circuits that separate only the signals of the channel assigned to itself in the time division multiplexed signal. an address counter that counts clock pulses of the interface circuit; a memory that receives a read address designation based on the count output of the address counter and sends out a signal with a different pattern for each channel; and a signal from the memory and the transmission interface. An exclusive OR gate is provided on the transmitting side for each of the transmitting interface circuits, which inputs the burst signal from the interface circuit and sends the output to the time division multiplexing circuit. an address counter for counting, a memory for receiving a read address designated by the count output of the address counter and sending out a signal having the same pattern as the memory of the corresponding channel on the transmitting side, and a signal from the memory and the time division multiplexing. A simple time division multiplex communication device characterized in that an exclusive OR gate is provided on the receiving side for each of the receiving interface circuits, the exclusive OR gate receiving a signal as an input and sending an output to the receiving interface circuit. Secret circuit.