JPH02254818A - Pll circuit - Google Patents

Abstract

PURPOSE:To allow the PLL circuit to follow a timing pulse in a short time even when the timing pulse is inputted in a same frequency by keeping the oscillation of the clock frequency just before an input timing pulse is lost in the PLL circuit. CONSTITUTION:A couple of noninverting and inverting clocks 501, 502 are generated from an output of a VCO 4 and the phase of the clocks and that of an input timing pulse 101 are compared. Then charge/discharge current control pulses 301, 302 are obtained and they are fed to a smoothing circuit 3. When the input timing pulse 101 is lost, the time of charge/discharge control pulses 301, 302 is made coincident. The charge/discharge time is coincident, a mean value of a smoothing circuit 303 is unchanged and the output of a VCO 4 keeps a constant value for the said period. Thus, even when the input timing pulse 101 is lost, the circuit keeps oscillating the clock frequency equal to that just before and the circuit follows in a short time at the input of the succeeding timing pulse.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a PLL circuit, and in particular, uses two signals obtained by comparing the phases of each clock of a two-phase clock and an input timing pulse, and smoothing the smoothing circuit after the phase comparison. The present invention relates to a PLL circuit having a phase comparator that controls charging and discharging.

[Conventional technology]

P L L (Phase-Locked Loop)
The circuit is well known. In the conventional PLL circuit, as shown in FIG.
The operation shown in FIG. 3 will be explained with reference to FIG. 4.

The input timing pulse 101 and the clock 102 are compared in phase to obtain comparison signals 103 and 104. The smoothing circuit 3 is discharged while the comparison signal 103 is at a high level,
The comparison signal 104 is charged while it is at a high level, and the output of the smoothing circuit 3 becomes a signal shown as a smoothing circuit output 105, thereby controlling the VCO 4.

[Problem to be solved by the invention]

'In the conventional PLL circuit described above, when the input timing pulse 101 disappears, only charging is performed as shown in FIG. 4, and the output voltage changes greatly, so the oscillation frequency of the VCO 4 changes similarly, and Input timing pulse 10
1 is input, there is a drawback that it takes a long time to make the oscillation output of the VCO 3 match the frequency and phase of the input timing pulse 101.

[Means to solve the problem]

The PLL circuit according to the present invention generates a pair of normal-phase and anti-phase clocks from the output of vC○, performs a phase comparison between these clocks and an input timing pulse, and uses two comparison outputs obtained to charge and discharge a smoothing circuit. control and holding the immediately previous output value even when the input timing pulse disappears.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which - pair OR
Gates 1 and 2, smoothing circuit 3, VCO 4 and buffer 5
Of these configurations, OR gate 1.2 and buffer 5 are directly related to the present invention.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

FIG. 2 is a diagram of main waveforms of the embodiment shown in FIG.

The operation of the embodiment shown in FIG. 1 will be described below with reference to FIG.

The VCO output 401 output from the VCO 4 is input to a buffer 5 that obtains both forward and inverted power, and generates a pair of two-phase clocks, a positive phase clock 501 and a negative phase clock 502.
The positive phase clock 501 is supplied to the OR gate 1, and the negative phase clock 02 is supplied to the OR gate 2.

The OR gate 1 performs a phase comparison based on the logical sum of the input timing pulse 101 and the positive phase clock 501 to obtain a charging current control pulse 301 and supplies it to the smoothing circuit 3 .

The OR gate 2 compares the phases of the input timing pulse 101 and the anti-phase clock 502 to obtain a discharge current control pulse 302, and supplies this to the smoothing circuit 3.

In the waveform diagram shown in FIG. 2, in period ■, when the negative phase clock 502 is at a low level,
1 is input to the OR gate 2, the duty of the discharge current control pulse 302 changes and the high level period becomes longer, and the discharge time is longer than the charging time of the smoothing circuit 3 by the charging current control pulse 301. Therefore, the average value of the smoothing circuit output 303 exhibits a decreasing characteristic.

During period ■, the duties of the charging current control pulse 301 and the discharging current control pulse 302 both change, but their values are the same, so the charging and discharging times are equal and the smoothing circuit output 30
As shown in Figure 3, the average value exhibits certain characteristics.

Period ■ indicates a period state in which the input timing pulse 101 disappears; in this period, the charging current control pulse 301 and the discharging current control pulse 302 match, and in this period, the charging and discharging times match, and the smoothing circuit output The average value of 303 does not change, and the output of VCO 4 maintains a constant value.

In this way, even when the input timing pulse 101 disappears, by continuing to oscillate the clock frequency immediately before it, it is possible to follow up in a short time when the next timing pulse is input.

〔Effect of the invention〕

As explained above, the present invention allows the PLL circuit to continue oscillating the frequency of the previous clock even when the input timing pulse disappears, so that even when the next timing pulse of the same frequency is input, it can be applied in a short time. It has the effect of being able to follow.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the PLL circuit of the present invention, and FIG.
The figure shows the main waveform diagram of the embodiment shown in Fig. 1, and Fig. 3 shows the conventional PL.
A block diagram of the L circuit, FIG. 4 is a main waveform diagram of the PLL circuit of FIG. 3. 1.2...OR gate, 3...smoothing circuit, 4...
VCO15...Buffer, 6...Phase comparison circuit.

Claims (1)

[Claims] A pair of positive phase and negative phase clocks are generated from the output of the VCO, and the two comparison outputs obtained by comparing the phases of these clocks and the input timing pulse are used to control charging and discharging of the smoothing circuit. 1. A PLL circuit comprising means for retaining a previous output value even when the output value disappears.