JPH05308285A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To attain the intermittent operation by keeping a stable output frequency and to reduce the power consumption. CONSTITUTION:A phase comparator 9 outputs a lock signal in the lock state. A lock signal detection section 13 detects the lock signal and outputs a detection signal. A timer control section 14 outputs a delay signal based on the detection signal and a control voltage outputted from a loop filter 6. A switch control section 12 delays and outputs a switching signal based on the delay signal and a power supply control section 11 outputs a delayed intermittent signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used in a power-saving frequency synthesizer.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional frequency synthesizer.

Conventionally, the frequency synthesizer has a structure as shown in FIG. 5 as a power saving type. In FIG. 5, the reference frequency of the reference frequency generator 1 is input to the phase comparator 9A of the phase locked loop unit 2. The frequency divider 8 divides the output frequency of the voltage controlled oscillator 5 and outputs the frequency division frequency to the phase comparator 9A.
Output to. The phase comparator 9A compares the phases of the reference frequency and the divided frequency and gives a phase difference signal to the charge pump 7. The charge pump 7 is driven by this phase difference signal and outputs a phase difference current. The loop filter 6 filters this phase difference current and supplies a control voltage to the voltage controlled oscillator 5. The voltage controlled oscillator 5 generates an output frequency based on this control voltage.

The carrier frequency can be switched by changing the frequency division ratio of the frequency divider 8 or by changing the reference frequency. A switch 10 for opening and closing the phase locked loop is provided in front of the loop filter 6 for power saving, and when the power sources of the reference frequency generator 1, the frequency divider 8 and the phase comparator 9A are "off", the loop is an open loop. The output frequency of the voltage controlled oscillator 5 is held by the charge voltage of the capacitor of the filter 6, and the power supply is restarted to the closed loop state again before the output frequency falls below an allowable level due to the discharge of the capacitor, thereby performing power saving. Was measuring.

[0005]

However, in such a conventional frequency synthesizer, the control voltage of the voltage controlled oscillator 5 is charged and discharged by charging and discharging the capacitor of the loop filter 6 in the frequency synchronization process of the phase locked loop unit 2 at the time of channel switching. However, the charge voltage cannot be held because the dielectric absorption current exists immediately after the voltage changes in the capacitor. Therefore, there is a problem that the output frequency fluctuates during the open loop in the intermittent operation during channel switching.

The present invention solves the above problems.
An object of the present invention is to provide a frequency synthesizer capable of performing stable operation while maintaining a stable output frequency and reducing power consumption.

[0007]

SUMMARY OF THE INVENTION The present invention is based on a control section including a power supply control section for outputting an intermittent signal at a predetermined cycle and a switch control section for outputting an opening / closing signal based on the intermittent signal, and based on the intermittent signal. A reference frequency generator that intermittently generates a reference frequency, a voltage controlled oscillator that generates an output frequency based on an input control voltage, and an output frequency that is obtained by intermittently dividing the output frequency based on the intermittent signal. A frequency divider, a phase comparison means for intermittently comparing the phase of the reference frequency with the frequency division frequency based on the intermittent signal, and outputting a phase difference current, and the phase difference current intermittently based on the switching signal. In a frequency synthesizer provided with a switch to output and a phase-locked loop unit including a loop filter that filters the phase difference current and outputs the control voltage, Serial phase comparing means includes means for outputting a lock signal when the locked state, the control unit,
The power supply control unit and the switch control unit respectively include the detection unit that detects the lock signal and outputs the detection signal, and the timer control unit that outputs the delay signal based on the detection signal and the control voltage. And a means for delaying the output of the output signal based on the above.

Further, according to the present invention, the phase comparison means intermittently compares the phases of the divided frequency and the reference frequency based on the intermittent signal, and outputs a phase difference signal and locks in the unlocked state. A phase comparator that outputs a lock signal when in the state and a charge pump that outputs the phase difference current based on the phase difference signal can be included.

Further, according to the present invention, the phase locked loop section is inserted between the power supply control section and the phase comparison means, and controls the frequency divider based on an initial phase control signal when the power is turned on to control the reference frequency. It is possible to include an initial phase synchronization circuit for aligning the frequency and the frequency division frequency to the phase comparison means.

[0010]

The phase comparison means outputs the lock signal when in the locked state. The control unit detects the lock signal by the detection unit and outputs the detection signal, and the timer control unit outputs the delay signal based on the detection signal and the control voltage output from the loop filter. The power supply controller and the switch controller each delay the output of the output signal based on the delay signal until the charge voltage of the loop filter becomes stable.

As described above, the stable output frequency can be maintained to perform the intermittent operation, and the power consumption can be reduced.

[0012]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a frequency synthesizer according to an embodiment of the present invention. FIG. 2 is a block diagram of the timer circuit of the frequency synthesizer of the present invention. FIG. 3 is a block diagram of the initial phase synchronization circuit of the frequency synthesizer of the present invention.

1 to 3, the frequency synthesizer includes a control unit 3 including a power supply control unit 11 which outputs an intermittent signal at a predetermined cycle and a switch control unit 12 which outputs an open / close signal based on the intermittent signal, and A reference frequency generator 1 that intermittently generates a reference frequency based on an intermittent signal, a voltage controlled oscillator 5 that generates an output frequency based on an input control voltage, and an output frequency is intermittently divided based on the intermittent signal. A frequency divider 8 for outputting a divided frequency, and a phase comparison means for intermittently comparing the phase of the reference frequency with the divided frequency based on the intermittent signal and outputting a phase difference current,
A switch 10 for intermittently outputting the phase difference current based on the switching signal and a phase locked loop unit 2 including a loop filter 6 for filtering the phase difference current and outputting the control voltage are provided.

A feature of the present invention is that the phase comparison means includes means for outputting a lock signal in the locked state, and the control section 3 detects the lock signal and outputs a detection signal. The lock signal detection unit 1 as the detection means
3 and a timer controller 14 that outputs a delay signal based on the detection signal and the control voltage.
1 and the switch controller 12 each include means for delaying the output of the output signal based on the delay signal.

The phase comparison means intermittently compares the phases of the divided frequency and the reference frequency based on the intermittent signal, outputs a phase difference signal in the unlocked state, and outputs the phase difference signal in the locked state. It includes a phase comparator 9 that outputs a lock signal, and a charge pump 7 that outputs the phase difference current based on the phase difference signal.

Further, the phase locked loop unit 2 is inserted between the power supply control unit 11 and the phase comparator 9, and controls the frequency divider 8 at power-on based on the initial phase control signal to control the reference frequency and the frequency division. It includes an initial phase synchronizing circuit 4 which aligns the phase with the peripheral frequency and supplies it to the phase comparing means.

The timer control section 14 also includes a voltage follower 16 for inputting a control voltage output from the loop filter 6, a delay circuit 19 for delaying a voltage change of the voltage follower 16, a voltage follower 16 and a delay circuit 1.
It includes comparators 17 and 18 for receiving the outputs of 9 and a NAND gate 20 for taking the NAND of the outputs of the comparators 17 and 18 and outputting the result to the switch control unit 12.

Furthermore, the initial phase synchronization circuit 4, the inputs the output frequency Sf _D clock input reference frequency Sf _r a flip-flop 22 to be input to the D input, Q output Sf _r 'and the power control of the flip-flop 22 The AND gate 24 which takes the logical product of the initial phase control signal SP1 output from the section 11 and supplies it to one input of the phase comparator 9, and the logical product of the initial phase control signal SP1 and the frequency division frequency Sf _V ′ are calculated. AND gate 25 applied to the other input of the comparator 9.
When, including the initial phase control signal SP1 and the flip-flop 23 to perform the initial phase control applied to the frequency divider 8 the Q output receives a reference frequency Sf _r is input to the D input to the clock input.

The operation of the frequency synthesizer having such a configuration will be described. FIG. 4 is a timing chart of signal waveforms of respective parts at the time of initial phase synchronization of the frequency synthesizer of the present invention.

1 to 4, in the standby mode, power is supplied to all of the reference frequency generator 1, the phase locked loop unit 2 and the controller 3 to generate a carrier for a control channel for communication control. When the predetermined time is continued, the intermittent signal and the open / close signal become "L", the switch 10 becomes "OFF" as shown in FIG. 2, and the capacitor C ₁ of the loop filter 6 is in the state of holding the previous voltage. At the same time when the circuit becomes an open loop, the power supplies of the respective parts other than the voltage controlled oscillator 5 in the reference frequency generation part 1 and the phase locked loop part 2 are turned “off”, but the voltage controlled oscillator is generated by the charge voltage of the capacitor C ₁ of the loop filter 6. The output frequency from 5 holds the frequency before the power supply of each part is turned off. After a predetermined time has passed in this state, the intermittent signal is returned to "H", and the power source of each main part is turned on. At this time, the divided frequency obtained by dividing the output frequency of the voltage-controlled oscillator 5 by the divider 8 is almost equal to the previous standby operation and almost coincides with the reference frequency, but the initial phase does not coincide. If the phases are not aligned before being input to the phase comparator 9, the synchronization will be lost. The synchronization of the initial phase is performed by gate processing of the frequency division frequency of the frequency divider 8, and the initial phase of the reference frequency and the frequency division frequency are aligned and output to the phase comparator 9. Since the switch 10 is closed at this time, the frequency is not greatly deviated in the phase comparison process, and the phase locked loop unit maintains stability.

During a call, a frequency frequently occurs by switching channels to establish a distant frequency. At this time, the value of the charge voltage of the capacitor C ₁ of the loop filter 6 changes due to the charging / discharging action from the charge pump 7 during the synchronization process of the phase locked loop unit 2. Phase comparator 9 when switching channels
After that, the unlock signal is output until the synchronization is established, and the lock signal is output after the synchronization is established, indicating that the system is stable. However, the capacitor C ₁ of the loop filter 6
However, since there is a dielectric absorption current immediately after the voltage changes, it is in an unstable state in which the charge voltage cannot be held. For this reason, the lock signal detection unit 13 detects the unlock signal, and of course, after the lock signal is detected, the timer control unit 14 outputs the intermittent signal from the switch control unit 12 and the power supply control unit 11 for a time corresponding to the amount of change in the control voltage. It kept "H", the capacitor C ₁ is stabilized in the same manner as in the standby previous need to perform the intermittent operation resulting from. When switching channels, the control voltage increases or decreases based on the changed channel frequency. A positive / negative comparator 17, which receives the value of the control voltage by the voltage follower 16 having a high input impedance and delays the voltage change through the delay circuit 19,
Receive at 18. When the difference between the “+” and “−” input voltages of the comparator input with respect to the offset voltage of the comparator becomes small, the outputs of the comparators 17 and 18 both become “H”, and the switch control unit 12 receives the signal via the NAND gate 20. By applying a gate to this signal, it is possible to lengthen the time during which the switch 10 is closed according to the amount of change in the control voltage. As a result, the voltage is controlled as a closed loop during a period in which the dielectric absorption current is reduced to a problem-free magnitude due to a voltage change due to charging / discharging at the capacitor C ₁ of the loop filter 6 at the time of channel switching, and the voltage is controlled to an open loop after the capacitor voltage stabilizes. Therefore, intermittent operation can be performed while maintaining a stable output frequency.

[0022]

As described above, the present invention has an excellent effect that the stable output frequency can be maintained and the intermittent operation can be performed and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a frequency synthesizer according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram of a timer circuit of the frequency synthesizer of the present invention.

FIG. 3 is a block configuration diagram of an initial phase synchronization circuit of the frequency synthesizer of the present invention.

FIG. 4 is a timing chart of signal waveforms of respective parts at the time of initial phase synchronization of the frequency synthesizer of the present invention.

FIG. 5 is a block diagram of a conventional frequency synthesizer.

[Explanation of symbols]

1 Reference Frequency Generating Unit 2, 2A Phase Locked Loop Unit 3, 3A Control Unit 4 Initial Phase Synchronization Circuit 5 Voltage Controlled Oscillator 6 Loop Filter 7 Charge Pump 8 Divider 9, 9A Phase Comparator 10 Switch 11 Power Supply Control Unit 12 Switch control unit 13 Lock signal detection unit 14 Timer control unit 16 Voltage follower 17, 18 Comparator 19 Delay circuit 20, 21 NAND gate 22, 23 Flip-flop 24, 25 AND gate C ₁ Capacitor Sclose Closed signal (closed) Sf _D Output frequency Sf _r, Sf _r 'reference frequency Sf _V, Sf _v' divided frequency SP1 initial phase control signal SQ1 output signal of the flip-flop (22)

Claims (2)

[Claims] 1. A control unit including a power supply control unit that outputs an intermittent signal at a predetermined cycle and a switch control unit that outputs an opening / closing signal based on the intermittent signal, and a reference frequency is generated intermittently based on the intermittent signal. A reference frequency generator, a voltage controlled oscillator that generates an output frequency based on an input control voltage, a frequency divider that intermittently divides the output frequency based on the intermittent signal to output a divided frequency, and the intermittent signal. Phase comparison means for intermittently comparing the phases of the reference frequency and the frequency division frequency to output a phase difference current, a switch for intermittently outputting the phase difference current based on the switching signal, and the phase difference current. And a phase-locked loop unit including a loop filter that outputs the control voltage. The control unit includes means for outputting a lock signal when in a state of being in a state, and the control unit detects the lock signal and outputs a detection signal, and a timer control for outputting a delay signal based on the detection signal and the control voltage. A frequency synthesizer, wherein the power supply control unit and the switch control unit each include means for delaying the output of the output signal based on the delay signal. 2. The phase comparison means intermittently compares the phases of the divided frequency and the reference frequency based on the intermittent signal, outputs a phase difference signal in the unlocked state, and outputs the phase difference signal in the locked state. A phase comparator that outputs a lock signal,
The frequency synthesizer according to claim 1, further comprising a charge pump that outputs the phase difference current based on the phase difference signal.