JPH0225107A - Overvoltage suppression circuit for semiconductor switch element - Google Patents

Abstract

PURPOSE:To suppress an overvoltage by connecting a series circuit comprising a Zener diode and a capacitor between a drain and a gate of a FET. CONSTITUTION:A DC power supply 8 and a load 7 are connected in series between the drain and source of a switching MOSFET 1. A gate drive circuit 6 is connected between the gate and source of the FET 1 via a resistor 4. If a drain-gate voltage VDG exceeds a Zener voltage VZD of the Zener diode 2 when the FET 1 is turned off, a current flows to a series circuit comprising the diode 2 and a capacitor 3, the gate-source voltage VGS rises, the OFF operation of the FET is relaxed to suppress the overvoltage. The similar effect is obtained by connecting a series circuit comprising a Zener diode and a capacitor between the collector and base of a switching bipolar transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit that suppresses overvoltage that occurs when a semiconductor switch/2-chi element that performs a switching operation is turned off.

[Prior Art] A power conversion device such as an inverter is configured by bridge-connecting MOSFETs as semiconductor switching elements, and converts DC power into AC power by sequentially turning on and off these MOSFETs. are doing.

Wiring inductance exists in the conductor that connects this inverter and the DC power supply that supplies DC power, and the energy stored in this wiring inductance increases the voltage change speed when the MOSFET is turned off. This MOSFET becomes high voltage, so-called surge voltage.
There is a risk of damaging it.

Therefore, between the drain and source of this MOSFET,
By connecting a surge absorption circuit, generally called a snubber, in parallel, the surge voltage applied to the MO3FET is alleviated and the MOSFET is prevented from being damaged.

FIG. 4 is a circuit diagram showing a first conventional example of a snubber attached to a semiconductor switch element, which is composed of a snubber resistor and a snubber capacitor between the drain and source of MO5FETI as a semiconductor switch element. RC snubbers 21 are connected in parallel.

FIG. 5 is a circuit diagram showing a second conventional example of a snubber attached to a semiconductor switch element, which is composed of a snubber resistor, a snubber capacitor, and a snubber diode between the drain and source of MO3FETI as a semiconductor switch element. The RCD snubbers 22 are connected in parallel.

FIG. 6 is a circuit diagram showing a third conventional example of a snubber attached to a semiconductor switch device, in which a plurality of (in this FIG. 6, two) MO3FETI semiconductor switch devices are used.
A circuit in which these are connected in series is collectively connected in parallel with a collective snubber 23 composed of a snubber resistor, a snubber capacitor, and a snubber diode.

These various snubbers 21, 22, and 23 are all MO3
The wiring inductance stored energy released when the FETI turns off is absorbed by the snubber capacitor, and then the MO
By consuming the energy accumulated in the snubber capacitor in the snubber resistor when the S FET is turned on, the surge voltage applied to the MO3FE 71 is suppressed.

[Problem to be solved by the invention]

As the capacity of a power converter, such as an inverter, becomes larger and its structural dimensions become larger, the snubber used therein also needs to have a larger capacity and larger size. By the way, as the device becomes larger in size, it becomes difficult to install the snubber very close to the semiconductor switching element, such as the MOSFET. It will not be possible to make it smaller.

The inductance present in this snubber wiring reduces the snubber effect, making it impossible to sufficiently suppress the surge voltage that occurs when the MOSFET turns off, so it is necessary to increase the snubber capacitance.
This has caused problems such as increasing the size of the device and increasing loss in the snubber.

SUMMARY OF THE INVENTION An object of the present invention is to effectively suppress the surge voltage generated due to the wiring inductance of a power supply circuit or a snubber circuit when a semiconductor switch element is turned off.

[Means to solve the problem]

In order to achieve the above object, the overvoltage suppression circuit of the present invention includes a constant voltage diode and a capacitor between the drain and gate of a MOSFET that performs switching operation, or between the collector and gate of a bipolar transistor that performs switching operation. The series circuits shall be connected in parallel.

[Function] Taking MOSFET as an example, when this MOSFET is turned off, the drain of MO3FET is
When the gate-to-gate voltage VIIG suppresses the zener voltage VZD of the voltage regulator diode connected in parallel, current flows to the capacitor connected in series with the voltage regulator diode, and the gate
Source-to-source voltage ■. increases, the off-operation of this MOSFET becomes gradual, and overvoltage is suppressed. Such operation is similar to the case of bipolar transistors.

〔Example〕

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In this FIG. 1, MO as a semiconductor switch element
A series circuit consisting of a DC power supply 8 and a load 7 is connected in series between the drain and source of the 5FETI, and this MO3F
A gate drive circuit 6 is connected between the gate and source of the ETI via a resistor 4.

Note that numeral 5 is also a resistor.

In the present invention, in the above-described circuit configuration, the drain current 1a flowing through the MO3FETI is intermittent by turning on and off the output voltage (1) of the gate drive circuit 6. In order to suppress the surge voltage, a series circuit of a constant voltage diode 2 and a capacitor 3 is connected in parallel between the train and gate of this MO3FETI. By this series circuit of the constant voltage diode 2 and the capacitor 3, the MO
Drain-gate voltage VI when 3FETI turns off
When IG suppresses the zener voltage V211 of constant voltage diode 2, a current of IX flows to capacitor 3 and this MOS
Since the gate-source voltage VCS of the FETI rises, the off-operation of the MO3FETI becomes gradual, and overvoltage is suppressed.

It goes without saying that the zener voltage v2° of the voltage regulator diode 2 is selected to be higher than the power supply voltage and lower than the voltage allowed between the drain and gate of the MOSFET I. This is because, in the operating mode of the embodiment shown in FIG. 1, the gate-source voltage V of MOSFET I. Since is a negligibly small value compared to the drain-source voltage V, the drain-source voltage ■. , can be considered to be approximately equal to the drain-gate voltage V□.

FIG. 2 is an operation waveform chart showing the operation of the first embodiment circuit shown in FIG. 1, in which (a) shows the change in the drain-gate voltage VIIG, and (b) shows the drain current (2). change of,
(c) is the current flowing through capacitor 3! 8 change, (d)
(e) shows the change in the gate-source voltage VSS, and (e) shows the change in the output voltage V of the gate drive circuit 6, respectively.

In FIG. 2, when an off signal (that is, the output voltage of the gate drive circuit 6 is made zero...see FIG. 2 (e)) is applied to MOSFET I at time T, the gate
Source-to-source voltage ■. 3 is the gate of this MOSFETI.
At the same time, the drain-source voltage VSS starts to decrease according to a time constant determined by the source-source junction capacitance and the resistance values of the resistors 4 and 5 (see FIG.
That is, the MOSFET starts to turn off. ...Second
(See figure (a)).

Then, at time TI, this drain-source voltage VS
The value of S is the gate-source voltage VSS and the Zener voltage v2
When the total value of .degree. and As a result, the rate of rise in the drain-source voltage V is also slowed down, suppressing surge voltage, and the energy stored in the wiring inductance is consumed inside this MOSFET, and the T output voltage is reduced. The off-operation is completed (that is, the drain current 1. becomes zero) at the time.

FIG. 3 is a circuit diagram showing the second embodiment of the present invention. The second embodiment circuit shown in FIG. 3 replaces the MOSFET I in the first embodiment circuit shown in FIG. 11, and the gate drive circuit 6 is replaced with the base drive circuit 16, and the other constant voltage diode 2, capacitor 3, resistors 4 and 5, load 7, and DC power supply 8 are those shown in FIG. and these operations are also the same as in the case of FIG. 1, so a description of the operations in FIG. 3 will be omitted.

In the embodiment circuits shown in FIGS. 1 and 3, even if a snubber shown in FIG. 4, 5, or 6 is attached to the MOSFETI or bipolar transistor 11 as a semiconductor switching element, The gist of the invention
Of course, this is not the case.

(Effect of the invention) According to this invention, a MOS as a semiconductor switch element
By connecting a series circuit of a constant voltage diode and a capacitor in parallel between the drain and gate of a FET or between the collector and base of a bipolar transistor, the surge voltage when the semiconductor switching element turns off can be controlled at a predetermined level. If this value is exceeded, the rate of fall of the gate voltage or base voltage for turning off will be slowed down, and the energy stored in the wiring inductance will be consumed inside this semiconductor switch element, so the voltage applied to the semiconductor switch element will be reduced. It is possible to suppress the surge voltage that occurs.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the first embodiment of the present invention;
The figure is an operation waveform diagram showing the operation of the first embodiment circuit shown in FIG. 1, FIG. 3 is a circuit diagram showing the second embodiment of the present invention, and FIGS. The figures show a first conventional snubber and a second conventional example of a snubber attached to a semiconductor switch element, respectively.
FIG. 7 is a circuit diagram showing a conventional example and a third conventional example. 1... MOSFET, 2... Constant voltage diode, 3
...Capacitor, 4,5...Resistor, 6...Gate drive circuit, 7...Load, 8...DC power supply, 11...
- Bipolar transistor, 16... Base drive circuit, 21... RC snubber, 22... RCD snubber, 2
3...-Block snubber. Diagram

Claims (1)

[Claims] 1) A semiconductor switch characterized in that a series circuit of a constant voltage diode and a capacitor is connected in parallel between the drain and gate of a metal oxide semiconductor field effect transistor (MOSFET) that performs a switching operation. Element overvoltage suppression circuit. 2) An overvoltage suppression circuit for a semiconductor switching element, characterized in that a series circuit of a constant voltage diode and a capacitor is connected in parallel between the collector and base of a bipolar transistor that performs a switching operation.