JPH0225075A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a poly-silicon pattern whose end face is flat in slope and surface is smooth by a method wherein a second poly-silicon is grown through a vapor growth on a poly-silicon layer at the temperature lower than the growth temperature of the poly-silicon layer, which is subjected to an isotropic dry etching using a resist pattern as a mask. CONSTITUTION:A high temperature growth poly-silicon layer insulating film PA1 and a low temperature growth poly-silicon layer insulating film PA2 are grown through a vapor growth method and laminated. Next, the layer PA2 first and then the layer PA1 are etched through an isotropic dry etching method using a resist pattern 15 as a mask. By these processes, an etching rate of the layer PA2 is higher than that of the layer PA1, so that an end face of a side etching section 10 grows to be a slope whose angle of inclination becomes gradually smaller downward, and as an ion implantation is not performed, the slope having smooth face becomes a flattened poly-silicon pattern PA and a dielectric breakdown strength between the pattern PA and a laminated conductor layer can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, particularly a method for forming a polysilicon pattern, the present invention provides a method for forming a poly-Si pattern that does not cause surface roughness and can flatten the etched edges. In order to form a polysilicon pattern, a first polysilicon layer is grown in a vapor phase on the first polysilicon layer at a temperature lower than the growth temperature of the first polysilicon layer. and patterning the second polysilicon layer and the first polysilicon layer below it by isotropic dry etching using a resist pattern as a mask. It consists of:

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a polysilicon pattern.

EPROMs and EEPROMs disposed on highly integrated semiconductor ICs such as LSIs have become extremely highly integrated, and the electrode width and thickness of their control gates have also been extremely reduced.

As a result, disconnection of the control gate electrode becomes apparent at the uneven step portion of the control gate forming surface, especially at the step portion that occurs at the end of the floating gate 1 electrode.
Improvement is desired.

[Conventional technology]

Is Figure 5 EPRO? A plan view schematically showing the structure of I (a
), A-A cross-sectional view ('b), and B-B cross-sectional view (
It is C1.

In the figure, 1 is a p-type silicon (Si) substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a floating gate electrode made of a lower poly-Si layer (PA), 5 is an inter-gate insulating film, and 6 is an upper layer A word line made of a poly-Si layer (PB) or the like, 7 an n-type source region, 8 an n-type drain region 9 an oxide film for blocking impurities, 10 a glabella insulating film made of phosphosilicate glass (PSG), 11 a contact window,
Reference numeral 12 indicates a bit line made of aluminum or the like. Note that the channel stopper is not shown.

As shown in this figure, in the EPROM, the lower poly-Si layer (PA
) A zero level difference of about 3,000 layers corresponding to the thickness is formed at the edge of the pattern. Initially, the lower poly-Si layer (
PA) was patterned using a reactive ion etching method that has etching anisotropy.
As shown in the figure, a steep, almost vertical step is formed at the end of ijiF (PA), and therefore, the step of the word [6] which is extended and arranged on the floating gate electrode 4 along this step is formed at the end of the ijiF (PA). coverage in the department has deteriorated,
A problem arises in that a disconnection N13 as shown in the figure is formed in the stepped portion, and the word line 6 is disconnected at that portion.

This problem has become more apparent as the width and thickness of the word line 6 has been reduced due to higher integration, and in order to reduce the word line resistance and increase speed, the word line has been made to be thinner than poly-Si. When the resistor is formed of a high melting point metal silicide such as tungsten silicide (WSiz), the occurrence of wire breakage becomes even more noticeable due to poor step coverage during the formation of the high melting point metal silicide layer.

Conventionally, the ends of the lower poly-Si layer (PΔ), which will become the floating gate electrode, are flattened by the method described below with reference to the process cross-sectional views shown in FIGS. 5(a) to 5(C). Word line breakage was prevented.

Refer to FIG. 6 fa) That is, after forming a gate oxide film 3 on a p-type Si substrate 1 in which an element formation region 14 is defined by a field oxide film 2, a thickness of 300 mm, which is the material of the floating gate electrode, is
About 0 people form a 0 step doped poly-Si layer (PA),
Next, a high dose (1
Phosphorus is ion-implanted at a CID of about 0" to 10" CID -2. Reference numeral 14 indicates a phosphorus ion (P) implanted region.

Note that in this implanted region 14, a concentration distribution of p (P) is generated that gradually decreases from the surface of the poly-Si layer (PA) toward the inside.

FIG. 6 (see BL) Next, a first resist pattern 15 having a shape defining both end portions facing each other in one direction of the floating gate bridge is formed on the poly-Si layer (PA), and then the resist pattern 15 is A poly-Si layer (P
Etching the exposed surface of A).

In this case, the etching rate due to fluorine radicals (F.) is faster on the surface area with high phosphorus concentration and is low on n? Since the etching speed decreases as the depth goes deeper, the amount of side etching, ie, the width of the side etching portion 16 (4), is also large at the surface and becomes smaller as it goes deeper.

FIG. 6 (See C1) At the end of the poly-Si layer (PA) that has been patterned, a tapered portion 17 of, for example, θ=60 to 45 degrees is formed. This taper has a large dose of P. The smaller the angle, the more gradual the formation.

[Problem to be solved by the invention]

However, in the conventional poly-Si layer planarization technology described above,
Poly 5iN (P), which is the material of the floating gate electrode,
Since impurities are implanted into the surface of A) at a high dose, the surface becomes rough and fine irregularities are formed on the surface of the poly-Si layer (PA). ) When the inter-gate insulating film 5 is formed by thermal oxidation on the inter-gate insulating film 5, the film quality of the insulating film 5 deteriorates due to the thin thickness of the inter-gate insulating film 5, and the word formed on the inter-gate insulating film 5 deteriorates. The dielectric strength between the wire 6 and the floating gate electrode 4 formed by the lower poly-Si layer (PA) is extremely reduced, and the E
A problem arises in that the authenticity of the information in FROM is selected.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a poly-Si pattern that does not cause surface roughness and can flatten the etched edges.

[Means to solve the problem]

The above issues arise when forming polysilicon patterns.
a step of vapor phase growing a first polysilicon layer; a step of vapor growing a second polysilicon layer on the first polysilicon layer at a temperature lower than the growth temperature of the first polysilicon layer; The method of manufacturing a semiconductor memory device according to the present invention includes the step of patterning the second polysilicon layer and the first polysilicon layer thereunder by isotropic dry etching using a resist pattern as a mask. be done.

[For production]

FIG. 1 is a process sectional view showing the principle of the present invention.

That is, in the method of the present invention, as shown in FIG.
A second poly-Si layer (PAD) is grown at a lower temperature than the first poly-Si layer (PAD). (18 is an insulating film) and as shown in FIG. , resist pattern 1
5 as a mask, the second poly-Si layer (PA2) and the first poly-Si layer (F.
AI) is then etched.

FIG. 2 is a diagram showing the relationship between the growth temperature of the poly 54 layer and the etching rate in the above-mentioned etching. The etching rate is 1 of the etching rate of the poly-Si layer grown at a high temperature of about 650°C.
．． Since it will be about 4 times as large, the side etching width will also have a similar ratio.

Therefore, the end surface of the side etched portion 16 at the bottom of the resist pattern 15 shown in FIG. 1('b) is formed into a sloped shape with a widened base.

When the patterning is completed, a poly-Si pattern (PA-P) having a sloped end surface with a widening base of θ=60 to 45 degrees is formed as shown in FIG. 1 fcl.

Note that the above Taber angle θ is the high temperature growth layer PA and the low temperature growth layer Ji.
It is controlled by the combination of the thickness with r'Az, and the larger the ratio of the film thickness of the low temperature growth layer PA, the smaller θ and the formation of a flatter pattern becomes possible.

As described above, in the method of the present invention, when forming a poly-Si layer pattern (PA-P) whose side surfaces are flattened in an inclined shape, impurity ions are not implanted into the poly-Si layer. No unevenness is formed on the surface of the poly 34 layer pattern (PA-P) due to surface roughness.

Therefore, the high quality of the thin insulating film grown on the poly 34 layer pattern (PA-P) is ensured, and the poly 5tJW pattern (PA-P) is grown through the poly Si layer pattern (PA-P) and the insulating film. P) The dielectric strength between the conductor layer and the conductor layer laminated thereon is improved.

〔Example〕

The present invention will be described below with reference to an embodiment of the present invention for forming an EFROM, with reference to FIG. 3 (al to fdl) and FIG. 4 (
A detailed explanation will be given with reference to process cross-sectional views shown in a) to (d).

Refer to FIGS. 3(a) and 4(a). That is, after forming a gate oxide film 3 on a p-type Si substrate 1 in which an element formation region 14 is defined by a field oxide film 2, Thickness 2500° C. by chemical vapor deposition from ordinary monosilane (SiHs)
Grow the first poly-Si layer (FAI) by high temperature growth at 550°C, then grow the first poly-Si layer (FAI) at 550°C.
A second poly 5iJi (PAz) is grown by low temperature growth to a thickness of about 500 nm.

Note that impurity diffusion for lowering resistance is done for each layer, that is, FAI.
, performed for each PAZ.

3 ('111) and 4 (see bl) Next, floating data 1 is placed on the second poly 5iji (PAz).
- Forming a first resist pattern 15 having a shape defining both end portions facing each other in one direction (Y direction in the figure) of the electrode, then masking the resist pattern 15, and using, for example, a down-flow method using a fluorine-based gas. The second poly-Si layer (pAz) and subsequently the exposed surface of the first hole J 5iJi (FAI) are etched by isotropic dry etching means. At this time, the etching rate due to fluorine radicals (F.) and the amount of side etching associated with this are such that the poly-Si layer (PAz) grown at low temperature is large and the poly-Si layer (FAI) grown at high temperature is small, as described above. is etched into a slope.

Refer to FIG. 3(C) and FIG. 4(C). This figure shows the resist pattern 15 after patterning is completed.
The first poly-Si layer (PAI) and the second poly-Si layer for forming a floating gate are shown in the figure.
Lower poly-Si pattern (PA-) consisting of i-layer (PA2)
A tapered portion 17 having an angle of, for example, θ=60 to 45 degrees is formed at the end of P). As described above, this taber becomes gentler as the thickness ratio of poly 5iii (PAz) grown at low temperature increases.

Referring to FIG. 3 (dl) and FIG. 4 (dl), an inter-gate insulating film 9 with a thickness of about 500 mm is formed on the surface of the lower poly-Si pattern (PA-P) by thermal oxidation or the like according to the usual manufacturing method. The thickness is about 2000 mm to form word lines of polycide structure on the substrate.
An upper poly-Si layer (PB) is grown in a vapor phase, and then a layer of, for example, tungsten silicide (WS i z) N20 is formed on it to a thickness of about 1000 by sputtering,
The above hsi, Ji 20, the upper poly-Si layer (PB), and the lower poly-Si pattern (PA-P) below are patterned by ordinary lithography, and the word line 6 having a polycide structure and the poly-Si layer below it are patterned. A floating gate electrode 4 is formed, and then impurities are introduced using the gate electrode as a mask to form an n-type source region 7 and an n-type drain region 8. Next, an oxide film 9 for impurity blocking is formed, and then an oxide film 9 is formed using PSG or the like. interlayer insulating film 10
A contact window 11 exposing the drain region 8 is formed in the core interlayer insulating film 10, and a
A bit line 12 made of I or the like is formed.

Thereafter, although not shown, a covering insulating film is formed, and an EFROM using the method of the present invention is completed.

As shown in the above embodiment, the end face of the poly-Si floating gate electrode formed using the method of the present invention in the word line extending direction is flattened to a slope of about 45 to 60 degrees, so that the floating gate electrode Defects such as faults do not occur at the end of the floating gate of the word line extending along the word line, and increases in wiring resistance and disconnection are prevented.

In addition, when forming a poly-Si pattern for forming a floating electric bridge, impurity ions are not implanted at a high concentration, so there is no uneven surface roughness on the surface of the floating gate electrode, and the inter-gate insulating film is High quality is guaranteed and high dielectric strength between the floating gate and the word line is ensured.

In addition to the embodiments described above, the present invention can of course be applied to an EEFROM having a stacked gate structure, and can also be applied as a means for flattening the surface on which electrode wiring is formed.

〔Effect of the invention〕

As described above, according to the present invention, the end face of a poly-Si pattern can be easily flattened into a sloped shape, and when forming the poly-Si pattern having the slope-like end face, a high concentration is applied to the poly-Si pattern. Since impurities are not ion-implanted, uneven surface roughness does not occur on the poly-Si layer pattern.

Therefore, according to the present invention, in a configuration in which wiring is formed across the poly-Si pattern via a thin insulating film, disconnection of the wiring on the edge of the poly-Si pattern is prevented, and 'The high quality of the thin insulating film on the JSi pattern is guaranteed, and the high dielectric strength voltage between the poly-Si pattern and the wiring above it is ensured. The reliability of a semiconductor memory device having a laminated structure such as OM can be improved.

[Brief explanation of the drawing]

Figure 1 (al to (C)) is a process cross-sectional view showing the principle of the present invention, Figure 2 is a diagram showing the relationship between poly-Si growth temperature and etching rate, and Figure 3 (al to (d) is a process cross-sectional view showing the principle of the present invention. A process plan view of an example of
FIG. 4(a) to fdl are process cross-sectional views of embodiments of the present invention;
Figure 5 is a plan view (a) schematically showing the EFROM.
6(a) to 6(C) are process sectional views of the conventional method. In the figure, 1 is a p-type silicon substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a floating gate electrode, 5 is an inter-gate insulating film, 6 is a word line, 7 is an n-type source region, 8 is a n-type drain region, 9 is an oxide film for impurity blocking, 10 is an insulating film between the eyebrows, 11 is a contact window, 12 is a pitch line, 13 is a cross section, 14 is an element formation region, 15 is a resist pattern, 16 is a side Etched portion, 17 is a tapered portion, 18 is an insulating film, 19 is an etched end face, 20 is a WSi 2 layer, PA is a lower poly-Si layer, PB is an upper poly-SiN layer, PA+ is a first poly-Si layer grown at high temperature, PA, The second poly-Si layer PA-P grown at low temperature shows a poly-Si pattern. The R principle of the present invention is shown in Section 1.
Funeral map No. 1 Kasumi (splint side view (b) Arrow view to A- IIfTIfI mouth (C,) B-B Schematic diagram of the top a town view EP shaku OM foil 5' mouth

Claims (1)

[Claims] When forming a polysilicon pattern, a step of vapor-phase growing a first polysilicon layer on the first polysilicon layer at a temperature lower than the growth temperature of the first polysilicon layer. and patterning the second polysilicon layer and the first polysilicon layer below it by isotropic dry etching using a resist pattern as a mask. A method for manufacturing a semiconductor device, comprising: