JPH02250423A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To relieve the labor of a detailed calculation of delay of data signal by providing a 2nd latch circuit to a pre-stage of a 1st latch circuit so that a flip-flop circuit latches a logic state before a data signal changes. CONSTITUTION:When a data signal DT fetched by a latch circuit 7 reaches a transfer gate 3 of a latch circuit 2 of a next stage, the transfer gate 3 is already conductive and the latch circuit 2 latches a logic value of the data signal DT latched by the latch circuit 7 before block signal CL rises. Then since a 3rd stage latch circuit 2a latches the signal at the trailing of the clock signal CL, the data signal DT with a logic value latched in the latch circuit 7 before the clock signal CL rises is outputted to an output terminal 6 of the flip-flop circuit. Thus, even when the data signal DT changes as soon as the clock signal CL rises, the logic value of the output signal Q is confirmed and the labor of delay the detailed calculation of delay of the logic signal is relieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a flip-flop 71 circuit designed by a gate array method, a standard cell method, or the like.

[Conventional technology]

Conventionally, in this type of semiconductor integrated circuit, as a flip-flop circuit, two latch circuits 2, 2 each having a data input terminal 1 as an input terminal for a data signal DT, as shown in FIG.
．． are connected in series, and when the clock signal CL to the clock input terminal 5 rises, the logic value of the data signal DT applied to the data input terminal 1 is held.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, when a logic circuit such as a shift register is constructed using such a flip-flop circuit, the data signal to the flip-flop circuit changes almost simultaneously with the rising edge of the clock signal, so Whether the flip-flop circuit holds the logic value before the change in the data signal or the logic value after the change is determined by the subtle time difference between the data signal and the clock signal. Therefore, due to variations in the usage environment or manufacturing of LSIs, their logic operation becomes unstable, and when designing logic circuits, they are subject to circuit configuration constraints and require detailed logic signal delay calculations, which is time-consuming. There is a drawback.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention has two series-connected circuits having a logical configuration in which a data signal changes almost simultaneously with a clock signal.
In a semiconductor integrated circuit including a flip-flop circuit including a plurality of first latch circuits, a second latch circuit is provided at a stage preceding the first latch circuit so that the flip-flop circuit maintains a logic state before the change of the data signal. It has a circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

As shown in FIG. 1, a flip-flop circuit configured on a semiconductor integrated circuit is a flip-flop circuit configured on a semiconductor integrated circuit as shown in FIG. Two-stage first latch circuit 2.2. In addition, a second latch circuit 7 is added between the data input terminal 1 and the latch circuit 2. Here, the latch circuit 7 holds the logical value of the data signal DT applied to the data input terminal 1 when the clock signal CL input to the clock input terminal 5 falls.

FIG. 2 is a waveform diagram for explaining the operation of the embodiment shown in FIG. The operation of the first embodiment will be explained below with reference to FIG.

In the embodiment shown in FIG. 1, at the same time as the clock signal CL input to the clock input terminal 5 rises, the data signal DT
When is changed to time tD shown in FIG. It will be done. However, when the data signal DT taken into the latch circuit 7 reaches the transfer gate 3 of the latch circuit 2 at the next stage, the transfer gate 3 is already in a conductive state, and the latch circuit 2 is in the latch circuit 7. The logic value of the data signal DT held before the rise of the clock signal CL is held, and when the clock signal CL falls, the third stage latch circuit 2. Since the flip-flop circuit holds this signal, the data signal DT of the logic value held in the latch circuit 7 before the clock signal CL rises is outputted to the output terminal 6 of this flip-flop circuit.

In this way, in this embodiment, as shown in the state of the data signal DT and the clock signal at time 1g shown in FIG. is held and the next clock signal CL
The logic value of the output signal Q can be determined even if the data signal DT changes at the same time as the rise of the clock signal CL.

〔Effect of the invention〕

As explained above, in the case of configuring a logic in which a data signal changes almost simultaneously with the rise of a clock signal, such as a shift register, the present invention provides an additional layer between a flip-flop circuit composed of two stages of latch circuits and a data input terminal. By inserting a stage latch circuit, the logical value of the data signal applied to the data input terminal at the falling edge of the clock signal can be
When the next clock signal rises, it can be obtained as an output signal regardless of the logic value of the data signal to the data input terminal, reducing constraints on the logic configuration when designing logic circuits, and allowing detailed data signals to be output. This has the effect of reducing the time and effort required for delay calculations.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the embodiment of FIG. 1, and FIG. 3 is a circuit diagram of an example of a conventional semiconductor integrated circuit. . 1...Data input terminal, 2,2. ．． 7...Latch circuit, 3.8...Transfer gate, 4,9...
Inverter, 5...clock input terminal, 6...output terminal, CL...clock signal, DT...data signal, Q...output signal.

Claims (1)

[Claims] In a semiconductor integrated circuit comprising a flip-flop circuit consisting of two first latch circuits connected in series and having a logic configuration in which a data signal changes almost simultaneously with a clock signal, the flip-flop circuit A semiconductor integrated circuit comprising a second latch circuit at a stage preceding the first latch circuit to maintain a logic state.