JPH02244633A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02244633A
JPH02244633A JP6421089A JP6421089A JPH02244633A JP H02244633 A JPH02244633 A JP H02244633A JP 6421089 A JP6421089 A JP 6421089A JP 6421089 A JP6421089 A JP 6421089A JP H02244633 A JPH02244633 A JP H02244633A
Authority
JP
Japan
Prior art keywords
layer
hole
fib
ion beam
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6421089A
Other languages
Japanese (ja)
Inventor
Takashi Honto
本戸 高志
Atsushi Sasaki
篤 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6421089A priority Critical patent/JPH02244633A/en
Publication of JPH02244633A publication Critical patent/JPH02244633A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form a highly reliable connection structure regardless of the thickness of an insulating material layer by a method wherein a connecting hole is opened in the insulating material layer interposed between conductors with a focused ion beam and the hole is filled with a metal layer by a deposition treatment using a focused ion beam. CONSTITUTION:An SiO2 insulating film 2, a PSG layer 3, an Al layer 6 which is a lower wiring layer and a PSG layer 5 are formed on an Si substrate 1. A focused ion beam (an FIB) is irradiated on part of the surface of the layer 5 to open a connecting hole 7 and when the hole 7 reaches the surface of the layer 6, a perforating treatment is stopped. Then, W(CO)4 is introduced in a treating chamber and when Ga<+> ions of the FIB are irradiated on the hole 7, a reduced W layer (an interlayer connecting layer) 8 is filled in the hole 7. Then, an Al layer 9 is applied and is patterned to form an upper wiring layer.

Description

【発明の詳細な説明】 〔概 要〕 本発明は多層配線の眉間接続の如く、導電体間に介在す
る絶縁材料層を通して導電体どうしを接続する処理法に
関し、 絶縁材料層の厚さには無関係に、微細領域に信転性の高
い接続構造を形成する処理法を提供することを目的とし
、 導電体間に介在する絶縁材料層に集束イオンビームで接
続孔を開け、該孔を集束イオンビームを用いる堆積処理
によって金属で充填する工程を包含して構成される。
[Detailed Description of the Invention] [Summary] The present invention relates to a processing method for connecting conductors to each other through an insulating material layer interposed between the conductors, such as a glabella connection in multilayer wiring, and the thickness of the insulating material layer Regardless, the purpose of this study is to provide a processing method for forming a highly reliable connection structure in a microscopic region, by making a connection hole in an insulating material layer interposed between conductors using a focused ion beam, and filling the hole with a focused ion beam. The structure includes filling with metal by a beam-based deposition process.

(産業上の利用分野〕 本発明は半導体集積回路(IC)の層間接続の如き接続
電極構造の形成方法に関わり、特に集束イオンビームを
用いて微細領域に層間接続電極を形成する処理法に関わ
る。
(Industrial Application Field) The present invention relates to a method for forming a connection electrode structure such as an interlayer connection in a semiconductor integrated circuit (IC), and particularly relates to a processing method for forming an interlayer connection electrode in a minute area using a focused ion beam. .

半導体ICは益々高集積化、微細化が進行しているが、
それに伴って多層配線の眉間接続を如何に形成するかと
いう問題が重要になっている。これは、眉間接続に利用
し得る面積が微細化したにもかかわらず、絶縁層の厚さ
がさほど減少しないため、接続孔のアスペクト比が大と
なり、段切れを生じないよう、接続孔を充填しながら上
層配線を形成することが困難となったことに因るもので
ある。この状況は半導体基板に作り込まれた素子にコン
タクト電極を形成する場合も同様である。
Semiconductor ICs are becoming increasingly highly integrated and miniaturized,
Accordingly, the problem of how to form glabellar connections in multilayer wiring has become important. This is because even though the area that can be used for connecting between the eyebrows has become smaller, the thickness of the insulating layer does not decrease much, so the aspect ratio of the connection hole increases, and the connection hole has to be filled to prevent breakage. However, this is due to the fact that it has become difficult to form upper layer wiring. This situation is the same when contact electrodes are formed on elements built into a semiconductor substrate.

接続孔のアスペクト比が小さい場合、即ち開口寸法に比
べて深さが小である場合は、絶縁層に接続孔を開け、蒸
着などの方法で上層配線を形成すれば、下層配線との接
続は出来上がる。これに対し開口寸法が小でアスペクト
比が大である場合には、被覆性の十分でない方法で導電
材料を被着したのでは孔底や肩の部分で不連続になり、
接続電極として機能しないものになる。
If the aspect ratio of the connection hole is small, that is, if the depth is small compared to the opening size, connection with the lower layer wiring can be made by drilling the connection hole in the insulating layer and forming the upper layer wiring by a method such as vapor deposition. It's done. On the other hand, if the opening size is small and the aspect ratio is large, if the conductive material is deposited using a method that does not provide sufficient coverage, it will become discontinuous at the hole bottom or shoulder.
It will not function as a connection electrode.

そのような事情から、被覆性の良い処理法で導電材料を
被着し、エッチバンクして接続孔内だけに導電材料を残
す工程を追加し、接続孔を充填してから上層配線を形成
することが行われるようになっている。
For this reason, we added the process of depositing a conductive material using a process that provides good coverage, etch-banking it and leaving the conductive material only inside the contact hole, and then forming the upper layer wiring after filling the contact hole. things are being done.

この接続孔充填処理としては、減圧CVD法とRIEの
組み合わせや、タングステン(W)の選択成長などが知
られているが、いずれも処理時間が長く、スルーブツト
の低下という問題を残すものである。
As this connection hole filling process, a combination of low pressure CVD and RIE, selective growth of tungsten (W), etc. are known, but all of them require a long process time and still have the problem of reduced throughput.

従って、作業性が良くスルーブツトの低下を来すことの
ない接続孔充填技術が提供されれば、ICの高集積化に
資するところ大となる。
Therefore, if a connecting hole filling technique that is easy to work with and does not cause a drop in throughput could be provided, it would greatly contribute to higher integration of ICs.

C従来の技術と発明が解決しようとする課題〕近年、集
束イオンビーム(focused ion beam、
以下FIBと略記)の利用技術が開発され、選択イオン
注入やイオンビームエツチングを行う装置が実用に供さ
れている。FIBを用いたイオンビームエツチングによ
れば0.1μm単位の選択エツチングが可能であり、エ
ツチングの異方性が顕著であることから、高精度に選定
された位置にサブミクロンの接続孔を開けることが可能
となっている。
C. Prior art and problems to be solved by the invention] In recent years, focused ion beams,
A technology utilizing FIB (hereinafter abbreviated as FIB) has been developed, and apparatuses for selective ion implantation and ion beam etching have been put into practical use. Ion beam etching using FIB allows selective etching in units of 0.1 μm, and because the anisotropy of etching is remarkable, it is possible to drill submicron connection holes at precisely selected positions. is possible.

しかしながら、このように微小でアスペクト比の大きい
接続孔を金属材料で選択的に充填する処理は従来知られ
ておらず、FIBによる層間接続体の形成は行われてい
ない。
However, a process for selectively filling such a small connection hole with a large aspect ratio with a metal material has not been known in the past, and an interlayer connection body has not been formed by FIB.

本発明の目的はFIBを用いて微小接続孔を開けると共
に、FIBを用いて該接続孔を充填する処理法を提供す
ることであり、より微細な領域に層間接続が形成された
ICを提供することである。
An object of the present invention is to provide a processing method for opening micro connection holes using FIB and filling the connection holes using FIB, and to provide an IC in which interlayer connections are formed in finer areas. That's true.

〔課題を解決するだめの手段〕[Failure to solve the problem]

」−起重的を達成するため、本発明の半導体装置の製造
方法には 被接続導電体の表面を被覆する絶縁材料層に集束イオン
ビームを選択的に照射して接続孔を形成する工程、およ
び 前記接続孔にイオンビームを照射しながら気相の金属化
合物を供給し、前記照射位置である前記接続孔中に、前
記化合物を構成する金属を堆積する工程 が包含される。
- In order to achieve this, the method for manufacturing a semiconductor device of the present invention includes a step of selectively irradiating an insulating material layer covering the surface of a conductor to be connected with a focused ion beam to form a contact hole; and a step of supplying a metal compound in a vapor phase while irradiating the connection hole with an ion beam, and depositing a metal constituting the compound in the connection hole, which is the irradiation position.

即ち、本発明の特徴となる処理工程を典型的な例に即し
て言えば、眉間絶縁層にFIBで接続孔を開け、該孔を
FIB照射で還元された金属で充填する処理が行われる
That is, to describe a typical processing step that is a feature of the present invention, a connection hole is opened in the glabella insulating layer using FIB, and the hole is filled with metal reduced by FIB irradiation. .

〔作 用] 金属の有機化合物、例えばW(Co)、、はFIBのエ
ネルギによって還元され、単体金属(W)を析出する。
[Function] An organic compound of a metal, such as W (Co), is reduced by the energy of the FIB, and a simple metal (W) is precipitated.

この還元反応は金属表面でFIB照射を受けることによ
って進行するから、FIBを穿孔位置に固定的に照射し
、有機金属の蒸気を供給すれば、開けられた孔に金属が
堆積して層間接続孔の充填が行われる。
This reduction reaction progresses when the metal surface is exposed to FIB irradiation, so if FIB is fixedly irradiated at the perforation position and organic metal vapor is supplied, the metal will deposit in the drilled hole and form the interlayer connection hole. Filling is carried out.

作業精度はFIBの照射位置制御と同程度であるから、
微細領域に極めて小さい接続孔を開け、その間孔位置に
再びFIBを照射することは容易であり、微細な接続孔
を還元された金属で充填することが可能となる。
The work accuracy is on the same level as FIB irradiation position control, so
It is easy to make an extremely small connection hole in a micro area and then irradiate the hole position again with FIB, making it possible to fill the minute connection hole with the reduced metal.

〔実施例〕〔Example〕

第1図は本発明の実施例の工程を示す断面模式図である
。以下、該図面を参照しながら説明する。
FIG. 1 is a schematic cross-sectional view showing the steps of an embodiment of the present invention. The following description will be given with reference to the drawings.

(a)図は下層配線上に眉間絶縁膜が設けられた状態を
示す。図中、1はSi基板、2は下層配線である。1層
、3と5は230層で4は表面平坦化のだめに塗布され
た5oc4である。このような構造は通常のIC形成工
程に於いて普通に見られるものである。
The figure (a) shows a state in which a glabella insulating film is provided on the lower layer wiring. In the figure, 1 is a Si substrate, and 2 is a lower layer wiring. Layer 1, 3 and 5 are 230 layers, and 4 is 5oc4 coated to flatten the surface. Such structures are commonly found in conventional IC forming processes.

上層配線との接続を設ける位置に、(ト))図に示され
るようにFIBを照射し、接続孔6を開ける。
FIB is irradiated to the position where the connection with the upper layer wiring is to be made as shown in the figure (g)) to open the connection hole 6.

PSGの厚さは1μm程度であり、これに例えば開口が
1.0μm X 1.、0μmの孔を開ける。処理条件
は、例えば使用するイオンがGa”で穿孔対象がPSG
の場合、通常の如く加速電圧は30KeV、圧力は0.
1〜0.2 Torrとする。ビーム電流は400pA
である。穿孔の進捗状況は放出される2次電子を観測す
ることで知り得るので、/IJI表面にまで到達したこ
とを確認して穿孔処理を停止する。
The thickness of the PSG is about 1 μm, and the opening is, for example, 1.0 μm×1. , a hole of 0 μm is drilled. The processing conditions are, for example, the ions used are Ga'' and the drilling target is PSG.
In this case, the accelerating voltage is 30 KeV and the pressure is 0.
1 to 0.2 Torr. Beam current is 400pA
It is. Since the progress of drilling can be known by observing the emitted secondary electrons, the drilling process is stopped after confirming that the secondary electrons have reached the /IJI surface.

このような接続孔は一つのICチップに多数設けられる
ものであるが、本実施例では、FIB照躬装置にセット
されたウェハ毎に、必要な接続孔を全て開けてから、次
の充填処理に進むものとする。処理位置−ケ所毎に開孔
と充填を繰り返し°ζもよいことは勿論である。
A large number of such connection holes are provided in one IC chip, but in this example, all necessary connection holes are opened for each wafer set in the FIB comparison device before the next filling process. shall proceed to. Of course, it is also possible to repeat drilling and filling at each treatment location.

次いで、W(CO)6を10−’−10−’Torrの
圧力で処理室に導入し、FIBの照射位置を接続孔の一
つに合わせてGa”イオンを30KeVで照射すると、
孔底のA1面或いはW面上でW(Co)6の分解が進行
し、還元されたWが孔内に堆積するので、(C)図の如
く接続孔がWによって充填される。
Next, W(CO)6 is introduced into the processing chamber at a pressure of 10-'-10-'Torr, and Ga'' ions are irradiated at 30 KeV by aligning the irradiation position of the FIB with one of the connection holes.
The decomposition of W(Co)6 progresses on the A1 plane or the W plane at the bottom of the hole, and the reduced W is deposited in the hole, so that the connecting hole is filled with W as shown in FIG.

一つの接続孔の充填が終われば、次の接続孔をFIBで
照射して同様にWの充填が行われ、ウェハ内の全ての接
続孔の充填が完了すれば、次のウェハの穿孔と充填を行
う。
When one connection hole is filled, the next connection hole is irradiated with FIB and filled with W in the same way, and when all the connection holes in the wafer are filled, the next wafer is drilled and filled. I do.

次いで、蒸着またはスパッタリングにより■−層配線と
なるAffi層8を被着し、バターニングして上層配線
を形成する。この状態が(d)図に示されており、7は
Wの眉間接続である。
Next, an Affi layer 8, which will become a (1)-layer wiring, is deposited by vapor deposition or sputtering, and patterned to form an upper layer wiring. This state is shown in figure (d), where 7 is the glabella connection of W.

本発明はまた、各種素子の接続電極にも、例えばトラン
ジスタのオーミックコンタクトの形成にも適用できる。
The present invention can also be applied to connection electrodes of various elements, for example, to the formation of ohmic contacts of transistors.

その場合も、穿孔の完了は2次電子の観測によって知る
ことが出来るので、浅いエミッタに対しても接合を破壊
することなく確実にコンタクトが形成される。
In that case as well, the completion of the drilling can be determined by observing secondary electrons, so that even with a shallow emitter, a contact can be reliably formed without destroying the junction.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明の方法によれば微細領域に
確実に眉間接続を形成することが出来るので、ICの高
集積化が可能になる。
As explained above, according to the method of the present invention, glabellar connections can be reliably formed in minute areas, making it possible to achieve high integration of ICs.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(a)は実施例の工程を示す断面模式図
であって、 図に於いて 1はSi基板、 2は5iOz膜、 3.5はPSG層、 4はSOG層、 6は下層配線のA1層、 7は接続孔、 8は眉間接続であるW、 9は上層配線のA1層 である。
FIGS. 1(a) to 1(a) are schematic cross-sectional views showing the steps of the example, in which 1 is a Si substrate, 2 is a 5iOz film, 3.5 is a PSG layer, 4 is a SOG layer, 6 is the A1 layer of the lower layer wiring, 7 is the connection hole, 8 is W which is the connection between the eyebrows, and 9 is the A1 layer of the upper layer wiring.

Claims (1)

【特許請求の範囲】 被接続導電体の表面を被覆する絶縁材料層に集束イオン
ビームを選択的に照射して接続孔を形成する工程、およ
び 前記接続孔にイオンビームを照射しながら気相の金属化
合物を供給し、前記照射位置である前記接続孔中に、前
記化合物を構成する金属を堆積する工程 とを包含することを特徴とする半導体装置の製造方法。
[Claims] A step of forming a connection hole by selectively irradiating an insulating material layer covering the surface of a conductor to be connected with a focused ion beam, and forming a gas phase while irradiating the connection hole with an ion beam. A method for manufacturing a semiconductor device, comprising the steps of: supplying a metal compound; and depositing a metal constituting the compound into the connection hole, which is the irradiation position.
JP6421089A 1989-03-16 1989-03-16 Manufacture of semiconductor device Pending JPH02244633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6421089A JPH02244633A (en) 1989-03-16 1989-03-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6421089A JPH02244633A (en) 1989-03-16 1989-03-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02244633A true JPH02244633A (en) 1990-09-28

Family

ID=13251493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6421089A Pending JPH02244633A (en) 1989-03-16 1989-03-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02244633A (en)

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