CN112366177A - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN112366177A CN112366177A CN202011245018.XA CN202011245018A CN112366177A CN 112366177 A CN112366177 A CN 112366177A CN 202011245018 A CN202011245018 A CN 202011245018A CN 112366177 A CN112366177 A CN 112366177A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
Abstract
The invention provides a semiconductor device and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate; forming a groove in the substrate, wherein the groove is provided with a first area and a second area which are mutually communicated, and the depth of the second area is greater than that of the first area; forming a conductive layer in the groove, wherein the thickness of the conductive layer formed in the second area is larger than that of the conductive layer formed in the first area; forming a conductive interconnect layer on the substrate, the conductive interconnect layer including conductive pillars in contact with the conductive layer at the second region. The invention has the advantages that the grooves with different depths are formed in the substrate, and then the conductive layers with different thicknesses are formed, so that the electromigration time of the corresponding area of the conductive column can be prolonged, and the reliability of the semiconductor device is greatly improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
Semiconductor devices, such as three-dimensional memories, must be manufactured through a series of process flows that include various semiconductor device processing steps such as etching and photolithography. The conventional process flow is divided into two main sub-process flows, namely Front End of Line (FEOL) and Back End of Line (BEOL). The back-end processes may include formation of metal layers, and formation of metal interconnects and contact holes between different layers of metal on the wafer. Among them, the conductive interconnection structure is an important structure for realizing electrical connection between semiconductor chip devices, and various conductive interconnection structures and formation processes, such as a copper interconnection structure, have been developed.
However, the back-end process of the conventional semiconductor device has defects, so that the prepared semiconductor device has poor reliability and cannot meet the requirements.
Disclosure of Invention
The invention aims to provide a semiconductor device and a forming method thereof, which can prolong the electromigration time and improve the reliability of the semiconductor device.
In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: providing a substrate; forming a groove in the substrate, wherein the groove is provided with a first area and a second area which are mutually communicated, and the depth of the second area is greater than that of the first area; forming a conductive layer in the groove, wherein the thickness of the conductive layer formed in the second area is larger than that of the conductive layer formed in the first area; forming a conductive interconnect layer on the substrate, the conductive interconnect layer including conductive pillars in contact with the conductive layer at the second region.
Optionally, the step of forming a trench in the substrate further comprises:
forming a patterned photoresist layer on the substrate, wherein the photoresist layer is provided with a process window, the process window comprises a first window exposing the first area and a second window exposing the second area, and the width of the second window is greater than that of the first window;
and etching the substrate by using plasma by taking the photoresist layer as a mask to form the groove.
Optionally, the conductive layer is made of copper metal, and the conductive pillar is made of tungsten metal.
Optionally, the step of forming a trench in the substrate further comprises:
a patterned photoresist layer on the substrate, the photoresist layer including a process window exposing the substrate, a first photoresist region and a second photoresist region, the photoresist thickness of the second photoresist region being less than that of the first photoresist region, and the second photoresist region being connected to the process window;
and etching by taking the photoresist layer as a mask, and forming a groove on the substrate corresponding to the process window and the second photoresist region, wherein the depth of the groove corresponding to the process window is greater than that of the groove corresponding to the second photoresist region.
Optionally, the first region extends along a preset direction, and the second region is disposed on a path of the first region.
Optionally, the step of forming a conductive interconnect layer on the substrate further comprises:
forming a dielectric layer on the substrate;
imaging the dielectric layer, and forming a via hole in the dielectric layer corresponding to the second area, wherein the via hole exposes the conductive layer;
and forming a conductive column in the via hole, wherein the conductive column is in contact with the conductive layer.
The present invention also provides a semiconductor device, comprising:
the device comprises a substrate and a first electrode, wherein the substrate is provided with a groove, the groove is provided with a first area and a second area, and the depth of the second area is greater than that of the first area;
the conducting layer is formed in the groove of the substrate, and the thickness of the conducting layer formed in the second area is larger than that of the conducting layer formed in the first area;
a conductive interconnect layer disposed on the substrate, the conductive interconnect layer including conductive pillars in contact with the conductive layer at the second region.
Optionally, the first region extends along a preset direction, and the second region is disposed on a path of the first region.
Optionally, the conductive layer extends along a preset direction, and a width of the conductive layer formed in the second region is greater than a width of the conductive layer formed in the first region in a direction perpendicular to the preset direction.
Optionally, the conductive interconnection layer includes a dielectric layer disposed on the substrate, and the conductive pillar penetrates through the dielectric layer at a position corresponding to the second region.
The invention has the advantages that the grooves with different depths are formed in the substrate, and then the conductive layers with different thicknesses are formed, so that the electromigration time of the corresponding area of the conductive column can be prolonged, and the reliability of the semiconductor device is greatly improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a conductive interconnect region of a prior art semiconductor device;
FIG. 2 is a schematic step view of a semiconductor manufacturing method according to a first embodiment of the present invention;
fig. 3A to 3L are process flow charts of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;
FIG. 4 is a schematic view of a step of forming a recess in a semiconductor manufacturing method according to a second embodiment of the present invention;
fig. 5A to 5E are process flow charts of forming a recess in a manufacturing method of a semiconductor device according to a second embodiment of the present invention;
fig. 6 is a scanning electron microscope image of the semiconductor device of the present invention.
Detailed Description
The following detailed description of embodiments of a semiconductor device and a method for forming the same according to the present invention will be made with reference to the accompanying drawings.
The back-end process of the existing semiconductor device has defects, so that the prepared semiconductor device has poor reliability and can not meet the requirements. Specifically, referring to fig. 1, which is a schematic cross-sectional view of a conductive interconnection region of a conventional semiconductor device, a metal conductive layer 11 is disposed in a substrate 10, and a conductive interconnection layer 12 is disposed on the substrate 10. The conductive interconnection layer 12 includes a dielectric layer 121 and a via 122 penetrating through the dielectric layer 121, and the via 122 exposes the metal conductive layer 11. A metal material is filled in the via hole 122 to form a conductive pillar 123.
The inventors have found that the reason for the poor reliability of the conventional semiconductor device is that, due to the limitation of the manufacturing process, when the via hole 122 is formed, a portion of the metal conductive layer 11 is also removed, so that the thickness of the metal conductive layer 11 in the region corresponding to the via hole 122 becomes thinner (as indicated by the arrow in the figure), and when the metal conductive layer 11 is too thin, the electromigration time of the metal conductive layer 11 becomes shorter, and the reliability of the semiconductor device becomes worse.
In order to solve the above problems, the present invention provides a semiconductor device and a method for manufacturing the same, which can improve the electromigration time of a conductive layer, thereby improving the reliability of the semiconductor device. Fig. 2 is a schematic step diagram of a semiconductor manufacturing method according to a first embodiment of the present invention, and fig. 3A to 3L are process flow diagrams of the semiconductor device manufacturing method according to the first embodiment of the present invention.
Referring to step S20 and fig. 3A, fig. 3A is a schematic cross-sectional view illustrating a substrate 30 is provided. The substrate 30 may be a semiconductor substrate having devices fabricated therein. The substrate 30 includes an array region and a peripheral circuit region, and in this embodiment, the method for manufacturing a semiconductor device of the present invention is described by taking the peripheral circuit region as an example.
Referring to step S21, a trench 31 is formed in the substrate 30, the trench 31 has a first region 31A and a second region 31B connected to each other, and the depth of the second region 31B is greater than the depth of the first region 31A. The trench 31 is recessed from the upper surface of the substrate 30 toward the inside of the substrate 30. Wherein the groove 31 extends along a predetermined direction. For example, as shown in fig. 3F, the grooves 31 extend in the X direction.
This embodiment exemplifies a method of forming the trench 31. The concrete description is as follows:
referring to fig. 3B, which is a cross-sectional view, a photoresist layer 300 is coated on the substrate 30.
Referring to fig. 3C, which is a schematic cross-sectional view, the photoresist layer 300 is patterned to form the photoresist layer 320 by using a mask 310 as a mask.
The mask 310 includes an opening 311. Referring to fig. 3D, which is a schematic top view of the mask 310, in the embodiment, the trench 31 to be formed extends along the X direction, and the opening 311 of the mask 310 also extends along the X direction. The opening 311 includes a first opening region 311A and a second opening region 311B, and a width of the second opening region 311B is greater than a width of the first opening region 311A in a direction perpendicular to an extending direction of the opening 311, i.e., in a direction perpendicular to the X direction.
Fig. 3E is a top view of the structure shown in fig. 3C, referring to fig. 3E, the openings 311 of the mask 310 correspondingly form the process windows 321 of the photoresist layer 320 on the photoresist layer 320. The first opening region 311A of the opening 311 corresponds to the first window 321A of the process window 321, and the second opening region 311B of the opening 311 corresponds to the second window 321B of the process window 321. The first window 321A and the second window 321B are arranged along a preset direction, and in a direction perpendicular to the preset direction, the width of the second window 321B is greater than that of the first window 321A. Specifically, in this embodiment, the preset direction is an X direction, and a direction perpendicular to the preset direction is a Y direction, the first window 321A and the second window 321B are arranged along the X direction, and in the Y direction, the width of the second window 321B is greater than the width of the first window 321A.
Referring to fig. 3F, which is a schematic cross-sectional view, the substrate 30 is etched by plasma using the patterned photoresist layer 320 as a mask to form the trench 31. Specifically, in this step, a pattern of the photoresist layer 320 is transferred onto the substrate 30 by using a plasma etching method to form the trench 31, where the trench 31 has a first region 31A and a second region 31B, and a depth of the second region 31B is greater than a depth of the first region 31A. The groove 31 extends along a predetermined direction, and the first region 31A and the second region 31B are arranged along the predetermined direction. Specifically, the grooves 31 extend in the X direction, and the first region 31A and the second region 31B are arranged in the X direction. When the plasma etching is carried out, the wider the width of the groove is, after the plasma is consumed in the etching reaction, the plasma in the reaction cavity can be supplemented more easily, and the reaction can be accelerated; and the wider the groove width is, the easier the byproducts generated by plasma etching can be discharged, and the less the byproducts are accumulated on the reaction interface and less the reaction interface is shielded in the same reaction time, so that the reaction is further accelerated. For example, in the present embodiment, the width of the second region 31B of the trench 31 in the direction perpendicular to the predetermined direction (the Y direction shown in fig. 3F) is greater than the width of the first region 31A of the trench 31, after the etching reaction consumes the plasma, the replenishment rate of the plasma in the second region 31B is greater than that of the first region 31A, and the byproduct accumulation in the second region 31B is less than that of the first region 31A, so that the reaction rate of the second region 31B is greater than that of the first region 31A, and after the same reaction time, the etching depth of the second region 31B is greater than that of the first region 31A. In the embodiment, the trenches with different depths are formed by utilizing the etching characteristics of the plasma etching process to the regions with different widths, no additional new process step is added, the process is not changed, and the cost is not increased.
Referring to step S22, fig. 3G and fig. 3H, wherein fig. 3G is a schematic cross-sectional view, and fig. 3H is a schematic top view, a conductive layer 32 is formed in the trench 31, and a depth of the conductive layer formed in the second region 31B is greater than a depth of the conductive layer formed in the first region 31A. Specifically, since the depth of the second region 31B of the trench 31 is greater than the depth of the first region 31A, after the conductive layer 32 is formed, the depth of the conductive layer formed in the second region 31B is greater than the depth of the conductive layer formed in the first region 31A. That is, the thickness H2 of the conductive layer formed in the second region 31B is greater than the thickness H1 of the conductive layer formed in the first region 31A. In this step, the conductive layer 32 may be formed by using a chemical vapor deposition, physical vapor deposition, or the like. In particular, the conductive layer 32 is flush with the substrate 30. The conductive layer 32 includes, but is not limited to, a metal layer, such as a copper layer.
Referring to step S23, a conductive interconnection layer 33 is formed on the substrate 30, where the conductive interconnection layer 33 includes a conductive pillar 331, and the conductive pillar 331 is in contact with the conductive layer 32 located in the second area 31B of the trench 31.
The present embodiment provides a method for forming the conductive interconnection layer 33, which is described in detail below.
Referring to fig. 3I, which is a schematic cross-sectional view, a dielectric layer 332 is formed on the substrate 30. The dielectric layer 332 is an insulating layer, which may be a multi-layer structure, for example, the dielectric layer 332 includes a nitride layer 3321, such as a silicon nitride layer, disposed on the substrate 30, an oxide layer 3322, such as a silicon oxide layer, disposed on the nitride layer 3321, and the like.
Referring to fig. 3J and fig. 3K, in which fig. 3J is a schematic cross-sectional view, and fig. 3K is a schematic top view, the dielectric layer 332 is patterned, a via hole 333 is formed in the dielectric layer 332 corresponding to the second region 31B of the trench 31, and the conductive layer 32 is exposed from the via hole 333. In this embodiment, the via 333 exposes a portion of the conductive layer 32.
In this step, when the via hole 333 is formed, the conductive layer 32 is partially removed under the influence of a process, and the thickness of the conductive layer 32 in the region corresponding to the via hole 333 is thicker, so that even if the conductive layer 32 is partially removed, the thickness of the conductive layer is still thicker than that in the corresponding region in the prior art, thereby improving the electromigration time compared with the prior art, and further improving the reliability of the semiconductor device.
Referring to fig. 3L, which is a schematic cross-sectional view, a conductive pillar 331 is formed in the via 333, and the conductive pillar 333 is electrically connected to the conductive layer 32. The conductive pillar 331 may be formed by filling the via 333 with a conductive material, which may be metal tungsten.
In this embodiment, in the manufacturing method of the semiconductor device, trenches with different depths are formed by using the etching characteristics of the plasma process on the regions with different widths, so as to form conductive layers with different thicknesses, thereby prolonging the electromigration time of the region corresponding to the conductive pillar, and greatly improving the reliability of the semiconductor device.
The invention also provides a second embodiment. The second embodiment is different from the first embodiment in the method of forming the trench. Fig. 4 is a schematic view of a step of forming a recess in a semiconductor manufacturing method according to a second embodiment of the present invention, and fig. 5A to 5E are process flow charts of forming a recess in a semiconductor device manufacturing method according to the second embodiment of the present invention.
Referring to step S40, fig. 5A and 5B, wherein fig. 5A is a schematic top view and fig. 5B is a schematic cross-sectional view, a patterned photoresist layer 50 is formed on the substrate 30. The photoresist layer 50 includes a process window 501 exposing the substrate 30, a first photoresist region 502 and a second photoresist region 503. The photoresist thickness of the second photoresist region 503 is smaller than that of the first photoresist region 502, and the second photoresist region 503 is connected to the process window 501.
In the present embodiment, the second photoresist region 503 extends along a predetermined direction (e.g., the X direction in fig. 5A), and the process window 501 is located on the path of the second photoresist region 503. That is, in the present embodiment, the second photoresist regions 503 are located at two sides of the process window 501 in a predetermined direction (e.g., X direction in fig. 5A), and in other embodiments of the invention, the second photoresist regions 503 may be located at one side of the process window 50.
Referring to step S41, etching is performed by using the photoresist layer 50 as a mask to form a groove 31 on the substrate 30 corresponding to the process window 501 and the second photoresist region 502, wherein the depth of the groove 31 corresponding to the process window 501 is greater than the depth of the groove 31 corresponding to the second photoresist region 502.
Specifically, referring to fig. 5C, which is a schematic cross-sectional view, the photoresist layer 50 is used as a mask for etching. Since the substrate 30 at the process window 501 is exposed, the substrate 30 is directly etched. During the etching process, the photoresist in the first photoresist region 502 and the second photoresist region 503 is also consumed. When the photoresist in the second photoresist region 503 is completely consumed, the substrate 30 has been etched to a certain depth. Referring to fig. 5D, which is a schematic cross-sectional view, when the etching is continued, in the area corresponding to the second photoresist region 503, since the photoresist layer is completely consumed, the substrate 30 in the area corresponding to the second photoresist region 503 will be etched, and at the same time, the substrate 30 corresponding to the process window 501 will be continuously etched.
After the step is completed, a trench 31 is formed on the substrate, a first region 31A of the trench 31 is formed in a region corresponding to the second photoresist region 503, and a second region 31B of the trench 31 is formed in a region corresponding to the process window 501. After the trench 31 is formed, the remaining photoresist layer is removed. Wherein the first region 31A extends along a preset direction, and the second region 31B is disposed on a path of the first region 31A.
Further, referring to fig. 5E, which is a schematic cross-sectional view, a conductive layer 32 is formed in the trench 31 formed by the manufacturing method of the second embodiment, and although the depth of the conductive layer 32 is different, the width of the conductive layer 32 is equal in the first region 31A and the second region 31B of the trench 31.
In the present embodiment, the trenches 31 with different depths are formed by using different thicknesses of the photoresist layer, and the depths of different regions of the trenches 31 can be controlled by controlling the thickness of the photoresist layer, so that the controllability of the trench depth is better than that of the first embodiment.
The invention also provides a semiconductor device. Referring to fig. 3L, in one embodiment, the semiconductor device includes a substrate 30, a conductive layer 32, and a conductive interconnect layer 33.
The substrate 30 may be a semiconductor substrate having devices fabricated therein. The substrate 30 includes an array region and a peripheral circuit region, and in this embodiment, the structure of the semiconductor device of the present invention is described by taking the peripheral circuit region as an example. The substrate 30 has a trench 31, and the trench 31 has a first region 31A and a second region 31B. Wherein the depth of the second region 31B is greater than the depth of the first region 31A. The grooves 31 extend along a predetermined direction (for example, an X direction shown in fig. 3L), and the first regions 31A and the second regions 31B are arranged along the predetermined direction (for example, the X direction shown in fig. 3L).
The conductive layer 32 is formed in the trench 31 of the substrate 30. The thickness of the conductive layer 32 formed in the second region 31B of the trench 31 is larger than the thickness of the conductive layer 32 formed in the first region 31A of the trench 31. Specifically, the upper surface of the conductive layer 32 formed in the trench 31 is flush with the lower surface of the trench 31 corresponding to the first region 31A and the second region 31B, and the depths of the lower surfaces are different, so that the thickness of the conductive layer formed in the second region 31B of the trench is greater than the thickness of the conductive layer formed in the first region 31A of the trench.
Further, in an embodiment of the present invention, a first region 31A of the trench 31 extends along a predetermined direction (for example, an X direction shown in fig. 3L), and a second region 31B of the trench 31 is disposed on a path of the first region 31A. That is, the first region 31A is disposed on both sides of the second region 31B in a predetermined direction (for example, an X direction shown in fig. 3L), and in other embodiments of the present invention, the first region 31A may be disposed on one side of the second region 31B.
Further, different methods for forming the trench 31 may cause different widths of different regions of the conductive layer 32. Specifically, as shown in fig. 3H, the conductive layer 32 extends along a predetermined direction (for example, X direction), and if the trenches 31 having different depths are formed by using a plasma etching process, the width of the conductive layer formed in the second region 31B of the trench 31 is greater than the width of the conductive layer formed in the first region 31A of the trench in a direction (for example, Y direction) perpendicular to the predetermined direction. In another embodiment of the present invention, as shown in fig. 5E, the trenches 31 with different depths are formed by using different photoresist thicknesses, and the width of the conductive layer formed in the second region 31B of the trench 31 is the same as the width of the conductive layer formed in the first region 31A of the trench in a direction (e.g., Y direction) perpendicular to the predetermined direction.
A conductive interconnect layer 33 is disposed on the substrate 30, the conductive interconnect layer 33 includes conductive pillars 331, and the conductive pillars 331 correspond to the second regions 31B of the trenches 31 and are electrically connected to the conductive layer 32.
In this embodiment, the conductive interconnection layer 33 further includes a dielectric layer 332 disposed on the substrate 30, and the conductive pillar 331 penetrates through the dielectric layer 332 and is electrically connected to the conductive layer 32 at a position corresponding to the second region 31B of the trench 31. The dielectric layer 332 is an insulating layer, which may be a multi-layer structure, for example, the dielectric layer 332 includes a nitride layer, such as a silicon nitride layer, disposed on the substrate 30, an oxide layer, such as a silicon oxide layer, disposed on the nitride layer, and the like.
Fig. 6 is a scanning electron microscope image of the semiconductor device of the present invention, please refer to fig. 6, it can be clearly observed on the scanning electron microscope image of the semiconductor device of the present invention that the depth of the lower surface of the conductive layer in the region corresponding to the conductive pillar is greater than the depth of the lower surface of the other region of the conductive layer, so that even if the conductive layer is partially removed when the via hole is formed, the remaining thickness can also meet the requirement of electromigration time, thereby greatly improving the reliability of the semiconductor device.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A method for manufacturing a semiconductor device, comprising the steps of:
providing a substrate;
forming a groove in the substrate, wherein the groove is provided with a first area and a second area which are mutually communicated, and the depth of the second area is greater than that of the first area;
forming a conductive layer in the groove, wherein the thickness of the conductive layer formed in the second area is larger than that of the conductive layer formed in the first area;
forming a conductive interconnect layer on the substrate, the conductive interconnect layer including conductive pillars in contact with the conductive layer at the second region.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a trench in the substrate further comprises:
forming a patterned photoresist layer on the substrate, wherein the photoresist layer is provided with a process window, the process window comprises a first window exposing the first area and a second window exposing the second area, and the width of the second window is greater than that of the first window;
and etching the substrate by using plasma by taking the photoresist layer as a mask to form the groove.
3. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the conductive layer is copper metal, and a material of the conductive pillar is tungsten metal.
4. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a trench in the substrate further comprises:
a patterned photoresist layer on the substrate, the photoresist layer including a process window exposing the substrate, a first photoresist region and a second photoresist region, the photoresist thickness of the second photoresist region being less than that of the first photoresist region, and the second photoresist region being connected to the process window;
and etching by taking the photoresist layer as a mask, and forming a groove on the substrate corresponding to the process window and the second photoresist region, wherein the depth of the groove corresponding to the process window is greater than that of the groove corresponding to the second photoresist region.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the first region extends in a predetermined direction, and the second region is provided on a path of the first region.
6. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a conductive interconnection layer on the substrate further comprises:
forming a dielectric layer on the substrate;
imaging the dielectric layer, and forming a via hole in the dielectric layer corresponding to the second area, wherein the via hole exposes the conductive layer;
and forming a conductive column in the via hole, wherein the conductive column is in contact with the conductive layer.
7. A semiconductor device, comprising:
the device comprises a substrate and a first electrode, wherein the substrate is provided with a groove, the groove is provided with a first area and a second area, and the depth of the second area is greater than that of the first area;
the conducting layer is formed in the groove of the substrate, and the thickness of the conducting layer formed in the second area is larger than that of the conducting layer formed in the first area;
a conductive interconnect layer disposed on the substrate, the conductive interconnect layer including conductive pillars in contact with the conductive layer at the second region.
8. The semiconductor device according to claim 7, wherein the first region extends in a predetermined direction, and the second region is provided in a path of the first region.
9. The semiconductor device according to claim 7, wherein the conductive layer extends in a predetermined direction, and a width of the conductive layer formed in the second region is larger than a width of the conductive layer formed in the first region in a vertical predetermined direction.
10. The semiconductor device of claim 7, wherein the conductive interconnect layer comprises a dielectric layer disposed on the substrate, and wherein the conductive pillars penetrate the dielectric layer at locations corresponding to the second regions.
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