JPH0224407B2 - - Google Patents

Description

[Detailed description of the invention] (Field to which the invention belongs) The present invention relates to analog delay circuits.

(Prior Art) Conventionally used analog delay circuits include charge coupled devices (CCDs).
There are LC circuits using coils and capacitors, and RC active circuits consisting of resistors, capacitors, and operational amplifiers.

However, CCDs require a fairly complex pre-filter to remove aliasing distortion, and are therefore far from being pure analog circuits. It has drawbacks such as the peripheral circuitry required for conversion to be off-chip. or,
It is difficult to make the LC circuit smaller and lower in price by making the L itself on-chip. But L is R,
simulated by C and op amp, R
On-chip implementation is possible by configuring the circuit with a switch capacitor circuit. but
As a delay circuit using an RC circuit, including the case where it is replaced with an LC circuit, a low-pass type as shown in Figure 3 is used.
It was common to use a CR circuit (retarded phase circuit).

Assuming that the time constant of the CR circuit is τ=CR, the angular frequency is ω, and the phase angle is θ, the transmission characteristic of such a delay circuit is as follows:F(ωτ)=A(ωτ)exp{ −jθ(ωτ)} ...(1) (where A is the amplitude and θ is the phase angle), and in this case, the amplitude characteristic G
(ωτ) is: G(ωτ) = 20log ₁₀ A(ωτ) [dB] ...(2) The phase angle error characteristic δ(ωτ), which indicates the degree of deviation from the ideal delay circuit characteristics, is: δ(ωτ) = {1-θ(ωτ)/ωτ}×100[%]...
…(3) is given by.

The amplitude characteristic G(ωτ) and the phase angle error characteristic δ(ωτ) change as the phase angle ωτ increases compared to the characteristics of the ideal delay circuit, as shown by curves A and B in FIG. 4, respectively. The amount of delay is insufficient and ωτ becomes
It can be seen that there is a significant deviation of about 0.2 rad.

This corresponds to the low-pass type shown in Figure 3 above.
When attempting to obtain a desired amount of delay by cascading CR circuits in multiple stages, the frequency band used becomes extremely narrow, which poses a serious problem in practice.

(Objective of the Invention) An object of the present invention is to solve the above-mentioned drawbacks of the conventional delay circuit, and to provide a delay circuit that closely approximates ideal delay characteristics.

(Summary of the invention) In order to achieve the above-mentioned object, the present invention has the following configuration.

That is, a plurality of high-pass CR circuits and a coefficient multiplication circuit are combined, and the necessary plurality of signals from the input and output terminals of each circuit are synthesized by an adder/subtractor circuit to obtain delay characteristics that approximate ideal characteristics. .

(Example) The present invention will be described in detail below based on an illustrated example.

FIG. 1 is a circuit diagram showing an embodiment of a delay circuit according to the present invention.

In rare drawings, 1-1, 1-2, 1-3,...
1-n is a high-pass type CR circuit (phase advancing circuit), which is connected in n stages in series, with 1/2, 1/2,
Coefficient multiplier circuits 2-1, 2-2, ..., 2-m with coefficients of 1/3, ..., 1/n (however, m = n-1)
is inserted, and the output of each stage of the n-stage high-pass type CR circuit and the input to the first-stage high-pass type CR circuit are synthesized by an adder/subtractor circuit 3.

Now, the high-pass CR circuit 1-1, 1-2,
When 1-3, ..., 1-n all have the same time constant τ, the respective transfer functions g are expressed as g=jωτ/(1+jωτ) ...(4), and by transforming this equation, jωτ= g/(1-g)...(5) is obtained.

On the other hand, as is well known, the ideal transfer function of a constant delay circuit is expressed as exp(-jωτ), so from this equation and the above equation (5), exp(-jωτ)=exp{-g/(1-g)} ...If the relational expression (6) is established and expanded, we get exp{-g/(1-g)}=1-g-g ²
/2-g ³ /6+...+g ⁿ /n! (or -g ⁿ /n!)...
(7) becomes.

On the other hand, the addition/subtraction circuit 3 of the circuit shown in FIG.
First, if the input signal ₀ to the first-stage high-pass CR circuit 1-1 is 1, the output signal of the first-stage high-pass CR circuit 1-1 is calculated. ₁ is g, the output signal ₂ of the second-stage high-pass CR circuit 1-2 is g ² /2, the output signal ₃ of the third-stage high-pass CR circuit 1-3 is g ³ /6, ..., the output signal n of the n-th stage high-pass CR circuit 1-n is g ⁿ /n! It is expressed as

So each of these output signals ₁ , ₂ , ₃ ,...
n and the input signal ₀ by the addition/subtraction circuit.
By combining the terms in equation (7) by adding or subtracting them depending on the sign, it is possible to derive the signal necessary to obtain the ideal delay characteristic. In this case, high-pass type
It is easy to understand that by increasing the number of CR circuit stages n, the ideal characteristics can be more closely approximated.

FIG. 2 is a circuit diagram showing another specific embodiment of the present invention, in which three stages of high-pass CR circuits are used.

In this embodiment, 3
The high-pass CR circuits 4, 5, and 6 of the stages and the coefficient multiplier circuits 7, 8 with coefficients of 1/2 and 1/3 inserted between these stages are all connected in series, and Input signals and output signals to the first-stage high-pass CR circuit, output signals from the second-stage high-pass CR circuit, and output signals from the third-stage high-pass CR circuit. Each signal is synthesized by an addition/subtraction circuit 9.

At this time, the addition/subtraction circuit 9 corresponds to the equation (7).
In this case, the output signal of each high-pass type CR circuit is subtracted from the input signal to the first-stage high-pass type CR circuit.

If the transfer function of the circuit configured in this manner is determined, 1-g-g ² /2-g ³ /6≈exp(-jωτ), and a signal that approximately approximates the ideal characteristics can be derived.

Amplitude characteristic G of the delay circuit configured as above
(ωτ) and the phase angle error characteristic δ(ωτ) obtained in the manner described above result in curves B shown in FIGS. 4a and 4b.

Comparing the phase angle error characteristic curves A and B, respectively, of the delay circuit with a low-pass type CR circuit alone and the delay circuit according to the present invention in FIG. Reduce the time constant of type CR circuit to 1/10
It will be understood that not only does this exhibit better transmission characteristics than a circuit in which 10 stages are connected in cascade via a buffer, but the number of elements making up the circuit is about 1/3.

This shows that extremely highly accurate delay characteristics can be obtained with a small number of circuit elements.

Incidentally, the coefficient multiplication circuits 7 and 8 and the addition/subtraction circuit 9
Needless to say, it is necessary to provide a buffer function for both.

In this way, the present invention adds or subtracts necessary multiple signals from each stage of a circuit that combines multiple stages of high-pass type CR circuits and coefficient multiplication circuits using an adder/subtractor circuit to obtain ideal transfer characteristics. This is what I did.

Note that the present invention can combine the multi-stage high-pass CR circuit and the coefficient multiplication circuit in any order as long as the necessary signals as described above, that is, the signals corresponding to each term in equation (7) can be extracted. It is obvious that it does not matter.

Furthermore, in the delay circuit according to the present invention, the values of C and R used are the same, which is advantageous when implemented as a MOS/IC. Moreover, if all resistive elements are replaced with a switched capacitor circuit, all other capacitors, operational amplifiers, etc. can be made into MOS/IC, so not only can the entire circuit be made on-chip, but the clock frequency applied to the analog switch of the switched capacitor circuit can also be changed. The resistance value can be varied by selection, which is extremely effective in making the delay time variable.

(Effects of the Invention) Since the present invention is configured as explained below, an analog delay circuit that has a wide usable frequency bandwidth and can obtain desired delay characteristics with extremely high precision is realized in an extremely small and inexpensive manner using a small number of circuit elements. Since it can be realized in a number of ways, it is extremely effective when applied to transmission circuits that process analog signals.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the delay circuit of the present invention, FIG. 2 is a circuit diagram showing another specific embodiment of the present invention, and FIG. 3 is a low-frequency circuit diagram showing the components of a conventional delay circuit. The circuit diagrams of the pass-through CR circuit, Figures 4a and 4b, show the amplitude characteristics and phase error characteristics of the delay circuit, respectively, for the characteristics of the conventional low-pass CR circuit (curve A) and the characteristics of the delay circuit of the present invention (curve A). It is a figure showing B). 1-1, 1-2, 1-3, ..., 1-n, 4,
5, 6...High-pass CR circuit, 2-1, 2-2,
......, 2-m, 7, 8... Coefficient multiplication circuit, 3, 9
...Addition/subtraction circuit.

Claims (1)

[Claims] 1. A coefficient multiplication circuit is arranged between required stages of a plurality of high-pass CR circuits, and an input signal to the first stage CR circuit and an input signal from each of the CR circuits or the coefficient multiplication circuit are provided. 1. A delay circuit constructed of a high-pass CR circuit, characterized in that the output signal is supplied to an adder/subtracter circuit, and the adder/subtracter circuit derives a composite signal of the signals. 2. Using the transfer function g of the high-pass CR circuit, the transfer function exp(-jωτ) of the ideal delay circuit is expressed as τ, where both the time constants of the ideal delay circuit and the high-pass CR circuit are τ. exp(−jωτ)=exp{−g/(1−g)}=1−g−g ² /2−g ³ /6+……+g ⁿ /n! (or-
g ⁿ /n! ) (where n is the number of stages of the high-pass type CR circuit) Based on this formula, each term is generated by the combination of the high-pass type CR circuit and the coefficient multiplication circuit, and this is calculated by the addition/subtraction described above. The present invention is characterized in that the circuit is configured to obtain a signal that approximates the ideal transfer function expressed by the above equation by performing addition or subtraction in accordance with the sign of each term in the above equation. A delay circuit composed of a high-pass CR circuit.