JPH022429A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To easily execute a test by a previously prepared test pattern even when the combination of units is changed by the specification of a user by constituting a semiconductor integrated circuit so that plural circuit units are mutually connected without connecting them through an internal bus. CONSTITUTION:An output signal S1 from an execution part B2 of a 1st circuit unit B is inputted to a 2nd execution part C2 through a selector C3 and outputted to an internal bus A through a 2nd register C1. In the case of executing a function test prior to the shipment of a product, the signal S1 outputted from the execution part B2 to the circuit unit C is stored in a register B1 through a signal line B3 and read out through an internal bus A, so that the function of the circuit unit B can be independently tested. In the 2nd circuit unit C, a signal S4 is inputted to the execution part C2 instead of the signal S1 inputted directly from the circuit unit B and the output is read out through the register C1, so that the text can be independently executed.

Description

[Detailed description of the invention] [Table of contents] [Overview] [Industrial application field] [Prior art] [Problem to be solved by the invention] [Means for solving the problem] [Operation] [Example] (a) Configuration of the first embodiment (Fig. 4) (b) Operation of the first embodiment (Fig. 5) (C) Second embodiment (Fig. 6) (d) Third embodiment (Fig. 7) Figure) (e) Other embodiments [Effects of the invention] [Summary] Regarding a semiconductor integrated circuit that is composed of a plurality of circuit units and in which these circuit units exchange signals with each other without going through an internal bus, its functional test is performed. connected to an internal bus, having a first register and a first production part;
A first circuit unit that outputs a signal to another circuit unit without going through an internal bus, a second register connected to the internal bus, and a second actual operation section, the first circuit unit and a second circuit unit that inputs a signal from the first circuit unit to the first register without going through an internal bus. The second circuit unit has one signal line, and the second circuit unit selects the input signal from the first circuit unit and the signal of the second register based on the selection signal and sends it to the second production section. It is configured to have a selector for outputting and a second signal line for transmitting a signal selected by the selector to a second register.

[Industrial Field of Application] The present invention relates to a semiconductor integrated circuit that is constituted by a plurality of circuit units, and these circuit units directly exchange signals with each other without going through an internal bus.

In recent years, with semiconductor integrated circuits such as single-chip microcomputers that integrate many functions into a single semiconductor chip, in order to supply semiconductor integrated circuits with the specifications desired by customers in a short period of time, we have developed circuits that realize each function. are designed in advance as a common unit, and according to the customer's specifications,
These unitized peripheral circuits are combined and integrated into a single chip.

In order to discover manufacturing defects in this semiconductor integrated circuit, a test is performed to see if the semiconductor integrated circuit actually operates according to specifications.In this test, a predetermined input pattern that changes over time is input to the input pin of the semiconductor integrated circuit. The quality of the semiconductor integrated circuit is determined based on whether the signal appearing on the output pin is as expected. In other words, a test pattern consisting of a pattern input to the input pin and an expected output pattern appearing on the output pin is prepared, and an operation test is performed using this pattern. However, in order to realize all operating conditions and confirm normal operation, It is necessary to create a wide variety of complex test patterns for each product.

[Prior Art] FIG. 8 shows a single-chip microcomputer as an example of a semiconductor integrated circuit. This microcomputer is configured by combining a cput and a unitized peripheral circuit 2.3. and peripheral circuit 2.3
is connected to the internal bus 4. Further, a boat circuit 5 is provided for inputting/outputting signals with the outside, and is also connected to the internal bus 4. Data is exchanged between the CPUI and peripheral circuits 2.3 via an internal bus 4.

That is, in order to transfer data from the CPU to the peripheral circuit 2.3, the CPU puts a data signal on the internal bus 4,
When the peripheral circuit 2.3 issues a write instruction, the peripheral circuit 2.3 takes in the data. Conversely, to transfer data from the peripheral circuit 2.3 to the CPUI, the peripheral circuit 2.3 reads the data when the CPU issues a read instruction. Put the data signal on internal bus 4,
The peripheral circuit 2 and the peripheral circuit 3 from which the CPUI takes in the data are connected by a signal line 6, and some control signals etc. are directly transmitted from the peripheral circuit 2 to the peripheral circuit 3 without going through the internal bus 4. Sent.

The details of the conventional structure of such a semiconductor integrated circuit are shown in FIG. 9. The internal bus 4 includes an address bus 4a for transferring address signals, a control bus 4b for transferring control signals, and a data bus 4C for transferring data signals. The 0 peripheral circuits 2.3 each include an address bus 4a and a control bus 4.
It is composed of address decoders 2a and 3a for decoding signals of b, registers 2b and 3b for exchanging data with a data bus 4C, and an actual operation section 2C13C for performing various processes. If all signals were sent and received between the peripheral circuits 2 and 3 via the data bus 4C, the rate at which the CPU can use the data bus 4C would be low, resulting in a decrease in processing speed. A signal line 6 is provided for directly outputting some of the control signals from the peripheral circuit 2 to the peripheral circuit 3, and is directly connected to the actual operating section 2c of the peripheral circuit 2 and the actual operating section 3C of the peripheral circuit 3.

When designing a semiconductor integrated circuit with new specifications, select the peripheral circuit that the user desires (here, peripheral circuit 2.3) and C
Combine with PU1. The designer only needs to newly create the layout of the CPU 1 and the peripheral circuits 2 and 3, and the connecting portion between the peripheral circuits 2 and 3.

[Problems to be Solved by the Invention] However, even if this method of making peripheral circuits into a common unit for multiple types is adopted, peripheral circuits 2.3
If there is a path for directly exchanging signals between devices without going through an internal bus, it is necessary to create a new test pattern for each user's function.

This is because the peripheral circuits 2 and 3 are related to each other to achieve a single IN function, so the input cover pattern for testing and the output This is because it was necessary to create a pattern of expected values.

Furthermore, since a functional test only determines the relationship between the input and output to the IC chip, even if it is determined to be defective, it is difficult to determine whether the peripheral circuit 2.3 has a defect in either or both of the active parts 2c and 3c. It was difficult to identify whether there was a defect in the joint between 2 and 3. For this reason, a lot of effort was spent on failure analysis.

Therefore, in the past, I
Even if the C-chip itself could be manufactured in a short period of time, testing it required a lot of effort, which hindered shortening of delivery times.

Therefore, even if the combinations and specifications of peripheral circuits are changing, the present invention makes most of the test patterns common, and #l
An object of the present invention is to provide a semiconductor integrated circuit that can reduce the labor required for performance testing.

[Means to solve the problem] FIG. 1 is a diagram showing the principle of the present invention (claim 1).

an internal bus (A) and a first bus connected to the internal bus (A).
register (B1), and a first production unit (B2) that is connected to the first register (81) and executes a predetermined function, A first circuit unit (B) that outputs a signal to the circuit unit without going through the internal bus (A), a second register (C1) connected to the internal bus (A), and a second register (C1). It has a second production unit (C2) that is connected to the circuit unit and executes a predetermined function, and transmits the signal from the first circuit unit (C1) to the second production unit (C2).
A semiconductor comprising a second circuit unit (C) that receives signals from C2) without going through the internal bus (A), and an input/output circuit (D) that is connected to the internal bus (A) and inputs and outputs signals to and from the outside. In the integrated circuit, the first circuit unit (8) has a first signal line (B3) that transmits a signal output from the first production section (B2) to the first register 1B1). , second
The circuit unit (C) receives the signal input from the first circuit unit (B) without going through the internal bus (A) and the signal from the second register (CI), and receives the signal from the second register (C1). The second production unit (C2) is selected based on the selection signal of
The second signal M (C4) transmits the signal selected by the selector (C2) to the second register (ci).

FIG. 2 is a diagram showing the principle of the present invention (claim 2).

The first circuit unit (B) in the semiconductor integrated circuit according to the second aspect of the invention transmits the signal output from the first production section (B2) and the signal from the first register (B1) to the first register (B1). A second circuit that selects based on a selection signal from B1) and outputs it to the second circuit unit (C) without going through the internal bus (A).
It further has a selector (B4).

FIG. 3 is a diagram showing the principle of the present invention (Claim 3).

A semiconductor integrated circuit according to a third aspect of the present invention includes a third register (E2) connected to the internal bus (A);
) is connected to the third production unit (E
2) and the internal bus (A) from the first circuit unit (B).
The signal input without going through the third register (E2
) based on the selection signal from the third register (E2) and outputs the selected signal to the third production section (E2); ) and a third signal line (C4) that transmits the signal selected by the third register (E2) to the third register (E2). a fourth selector ([5) that selects the signal based on the selection signal from the third register ([1)] and outputs the selected signal to the second circuit unit (C) without going through the internal bus (A); , the signal output from the third production unit (E2) is transferred to the third register (E2).
The apparatus further includes a third circuit unit (D) having a fourth signal 1 (C6) transmitted to the fourth signal 1 (C6).

[Function] According to the present invention (see Claim 1, FIG. 1), during normal operation used by a customer, the output signal S1 of the first actual operation section (B1) is
is input to the second production unit (C3) via the selector (C3), and its output is output to the internal bus (A) via the second register (C1). On the other hand, when performing a functional test before shipping the product, the signal S1 that is directly output from the first production section (82) to the second circuit unit (C) is sent to the first signal line (83) via the first signal line (83). 1 register (81),
By reading it out via the internal bus (C), the functionality of the first circuit unit (B) is tested independently. In the second circuit unit (C), the selector (C3) sends the signal S4 to the second actual unit (C2) instead of the signal S1 that is directly input from the first circuit unit (B) to the second actual unit (C2). Moving part (C3
). The signal S4 is a signal input from the outside via the internal bus (A) using a signal corresponding to the signal S1 as a test pattern. The function of the second working part (C3) can be independently checked by reading out its output signal S3 via the second register (C1). In addition, the signal S1 is sent to the second controller via the selector (C3) without going through the second actual operation unit (C2).
The connection between the two circuits (B) and (C) can also be confirmed by reading directly into the register (C1). In addition, the selector (C
The switching in 3) is performed by the signal S5. The first register (
B1), and the internal bus (
A), since it is possible to input and output signals to the outside via the input/output circuit (D), the i-function of the first circuit unit (B) and the second circuit unit (C) can be changed as described above. It is possible to independently test the operation of both of them, including their coupling paths.

According to the present invention (see Claim 2 and FIG. 2), in the first circuit unit FB), the signal stored in the first register (81) is transferred to the second selector (B4). It can be output to the circuit unit [C].

According to the present invention (Claim 3, see FIG. 3), in the third circuit unit (E), the signals input to the third actual operation section (E2) are transmitted from the third operation section (E2). The output signal is also the third
The third circuit unit [E] can be tested for operation independently from the other circuit units.

[Embodiments] (a) Structure of First Embodiment FIG. 4 is a block diagram of the first embodiment of the present invention. In this embodiment, a single-chip microcomputer will be explained as an example of a semiconductor integrated circuit. Components that are the same as those of the conventional device shown in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

In this embodiment, CPU peripheral circuit (circuit unit) 2.
The peripheral circuits 2 and 3 in which 3 is unitized are each composed of address decoders 2a, 3a, registers 2b', 3b', and production parts 2c, 3C, as in the conventional case. The registers 2b' and 3b' are constructed with a larger number of bits than before for testing purposes. register 2b
The diagonally shaded parts in ' and 3b' are the added parts. The actual operating section 2c of the peripheral circuit 2 and the actual operating section 3c of the peripheral circuit 3 are connected by a signal line 6, and signals can also be transmitted via the internal bus 4. Examples of the peripheral circuit 2 that outputs signals to other peripheral circuits include a timer/counter, a time base timer for time management, and a remote control control circuit. As the peripheral circuit 3 that inputs signals from other peripheral circuits, for example,
Serial boat, timer/counter, V F D (V
acuulIFluorescenceDisplay
) controllers, etc.

Address decoders 2a, 3a of peripheral circuit 2.3 are connected to address bus 4a and control bus 4b. By decoding the signal on the address bus 4a, it is learned that the peripheral circuit 2.3 to which it belongs has been selected. Furthermore, by decoding the signal on the control bus 4b, the read command (-register of the peripheral circuit 2.3) is known. 2b'', 3b' to the data bus 4c) or write instruction (
= an instruction for the registers 2b' and 3b' of the peripheral circuit 2.3 to read data from the data bus 4c), and outputs a read control signal or a write control signal to the registers 2b' and 3b'. From register 2b'3b' to production unit 2c,
A control signal is output to CP 3c, and a status signal is output from the actual operating units 2c and 3c to register 2b''3c.CP
When the UI operates the peripheral circuit 2.3, the production section 2
After writing the control 61+ signal to registers 2b' and 3b' to registers 2b' and 3b' through the data bus 4c and causing the production units 2c and 3c to execute a predetermined function, the state B stored in registers 2b' and 3b' is written. The exchange of data or control signal No. 1 between the peripheral circuits 2 and 3 that read signals via the data bus 4c is a signal that connects the actual operating section 2c of the peripheral circuit 2 and the operating section 3c of the peripheral circuit 3. It is configured to be performed directly via the line 6 without going through the data bus 4c.

In this embodiment, the peripheral circuits 2 and 3 each have a selector 2d.
, 3d are provided. The selector 2d of the peripheral circuit 2 receives a signal P1 which is directly output from the actual operation unit 2c to the peripheral circuit 3.
Then, the signal P2 output from the register 2b' is selected by the selection signal P3 from the register 2b' and outputted as the signal P4. For example, if the selection signal P3=0, the signal P1 is outputted as the output signal P4, and the selection Signal P3: 0 peripheral circuit 3 outputs signal P2 as output signal P4 if it is 1
The selector 3d selects the signal Q1 directly input from the peripheral circuit 2 to the production unit 3c and the signal Q2 output from the register 3b' using the selection signal Q3 from the register 3b' and outputs the selected signal Q4 as the signal Q4. , selection signal Q3=O
If so, the signal Ql is output as the output signal Q4, and if the selection signal Q3=1, the signal Q2 is output as the output signal Q4.

Further, in this embodiment, a signal 412e for transmitting the output signal P4 of the selector 2b' to the register 2b' is provided, and the configuration is such that the signal P4 can be read out at any time via the data bus 4C. Similarly, a signal line 3e is provided for transmitting the output signal Q4 of the selector 3b' to the register 3b', and the configuration is such that the signal Q4 can be read out at any time via the data bus 4C.

(b) Operation of the first embodiment In this embodiment, multiple peripheral circuits that exchange signals without going through a data bus can be individually operated and tested. 9 During normal operation and during a functional test The operation will be explained below.

(During normal operation) The contacts of the selectors 2d and 3d are in the state shown, and operate in exactly the same manner as in FIG. 9. At this time, register 2b',
The shaded area 3b' is not used.

(During the Ill performance test) - First, in order to start up the peripheral circuit 2, the CPU
outputs the address signal of the peripheral circuit 2 to the address bus 4a and issues a write command to the control bus 4b. These are decoded by the address decoder 2a, and the register 2b' stores the data transferred from the CPU 1 to the data bus 4C. As this data is taken in (arrow a), "0" is output as the selection signal P3 together with a start command for the actual operation section 2c.

■ When the data is loaded into the register 2b', the start command in the data is output to the production unit 2C (arrow b), and the production unit 2c is permitted to operate and starts operating6. In this case, the production unit 2C starts time counting.

At the same time, the selection signal P3 (=O) is output to the selector 2d (arrow c). Since the a selection signal P3 is O, the selector 2d selects the signal P1 from the production section 2c and outputs it as the output signal P4. (arrow d).

■ When the production section 2C executes a predetermined i-function and outputs the result of the execution as a signal P1, the signal is outputted from the selector 2d as a signal P4, and is outputted to the register 2b' via the signal line 2e (arrow e). )6 For example, in the case of a timer, an overflow signal is output to register 2b'.

After that, if the CPUI reads the contents of the register 2b' (arrow f), the execution result can be known. In this way, it is confirmed that the actual operating section 2C normally outputs the signal P1 for each input.

Pa　a　　　゛　.

■ First, in order to start up the peripheral circuit 3, the CPU 1 outputs the address signal of the peripheral circuit 3 to the address bus 4a, and issues a write command to the control bus 4b.These are decoded by the address decoder 3a, and the register 3
b' takes in data transferred from the CPUI to the data bus 4c (arrow g), and outputs "1" as this data as the selection signal Q3 together with a startup command for the production unit 3c.

(2) When the data is taken into the register 3b', a start command in the data is output to the production unit 3c (arrow h), and the production unit 3c is permitted to operate and starts operating. At the same time, the selection signal Q3 (=1) is output to the selector 3d (arrow 1). Since the 0 selection signal Q3 is 1, the selector 3d selects the signal Q2 from the register 3b' and outputs it as the output signal Q4. The signal Q2 outputted to the section 3c (arrow j) is a signal corresponding to the output P1 of the actual operation section 2c given from the outside.

■ When the production unit 3c executes a predetermined function, the execution result is outputted to the register 3b' as a status signal (arrow k). After that, C and P Ul are sent to the register 3b'.
If you read the contents of '9 (arrow 1), you can know the execution result. In this way, by arbitrarily setting the signal Q2 from the outside and checking the output of the actual operating section 3C, the operation of the peripheral circuit 3 can be checked independently of the peripheral circuit 2.

In this way, the peripheral circuits 2.3 can be tested independently of each other, so if a test pattern is created for the peripheral circuits 2.3, even when combined, the 5th
Just connect the test patterns as shown in the figure. However, since the connecting portion between peripheral circuit 2 and peripheral circuit 3 is newly designed, a test pattern for this is created separately as shown in FIG. Note that this test pattern only tests the connection of the signal line 6, so it is extremely simple compared to the operation test pattern for peripheral circuits.

2 and 3, the CPU 1 sends the H selection signal P to the register 2b' of the peripheral circuit 2.
Write “1” as 3 and register 3b of peripheral port F43.
'0' is written as the selection signal Q3. Then, as shown by arrow m, a route is formed from register 2b' to selector 2d to signal line 6 to selector 3d to signal line 3e to register 3b'. The connection of the signal line 6 can be tested by cput putting a test pattern into the register 2b' and reading it from the register 3b'.

As described above, according to the first embodiment, most of the test patterns can be created by combining test patterns of peripheral circuits created in advance, and can be created extremely easily.

(C) Second Embodiment FIG. 6 is a block diagram of a second embodiment of the present invention. Fourth
Components that are the same as those in the first embodiment shown in the drawings are given the same reference numerals and explanations will be omitted.

The difference from the first embodiment is that a signal line 2e is provided in the peripheral circuit 2 to transmit the signal P1 outputted from the actual operation section 2c to the register 2b', and the selector is omitted; the other configurations are the same. be.

The operation test of the peripheral circuit 3 is the same as in the first embodiment, but the operation test of the peripheral circuit 2 and the connection test between the peripheral circuits 2 and 3 are different.

. In this embodiment, the output signal of the active part 2C is a signal! ! Since the signal is outputted to the register 2b' by 2e, a route as shown by arrow n is always formed. Therefore, as in the first embodiment, the output of the operating section 2C can be read out by the register 2b', and the peripheral circuit 2 can be tested independently of the other peripheral circuits.

In this embodiment, the peripheral port Fi@2 is not provided with a selector, so the data stored in the register 2b'' cannot be directly sent to the peripheral circuit 3 via the signal line 6. After confirming that it works reliably, the production section 2
The operation of C is externally controlled to output a scheduled signal P1 to the signal line 6, and this scheduled signal is stored in the register 3b' of the peripheral circuit 3 to perform the test.
Since the signal P1 outputted from C as the signal a6 can be seen through the register 2b', the connection test can be performed reliably.

In this way, in the case of the second embodiment as well, most of the test patterns for each peripheral circuit created in advance can be combined, and the test patterns can be created extremely easily.

(d) Third Embodiment FIG. 7 is a block diagram of a third embodiment of the present invention. Fourth
Components that are the same as those in the first embodiment shown in the drawings are given the same reference numerals and explanations will be omitted.

In this embodiment, a peripheral circuit 7 of a different type from the peripheral circuit 2.3 is provided. This peripheral circuit 7 receives signals directly from other peripheral circuits without going through the internal bus 4, and outputs signals directly to other peripheral circuits. That is, peripheral circuit 2 and peripheral circuit 7 are connected by signal line 8, and peripheral circuit 7 and peripheral circuit 3 are connected by signal line.

Peripheral circuit 7, like peripheral circuit 2.3, includes an address decoder 7a, a register 7b, and an actual operation section 7c. Further, the peripheral circuit 7 has a selector 7d on the input side of the actual operation section 7c.
, has a selector 7f on the output side.

The selector 7d has a similar configuration to the selector 3d of the peripheral circuit 3. That is, the selector 7d selects the signal R1 directly input from the peripheral circuit 2 to the actual operation section 7c and the register 7b.
9, which selects the signal R2 output from the register 7b, selects it by the selection signal R3, and outputs it as the signal R4.
If the selection signal R3=0, the signal R1 is used as the output signal R4.
If the selection signal R3=1, the signal R2 is output as the output signal R4. The output signal R4 of the selector 7d is transmitted to the register 7b via the signal line 7e.

The selector 7 has the same configuration as the selector 2d of the peripheral circuit 2. That is, the selector 7f outputs the signal S1 directly output from the production unit 7C to the peripheral circuit 3, and the register 7b.
For example, the signal S2 output from the register 7b is selected by the selection signal S3 from the register 7b and output as the signal S4.
If the selection signal 53=0, the signal S1 is used as the output signal S4.
If the selection signal 53=1, the signal S2 is output as the output signal S4. The output signal S4 of the selector 7f is transmitted to the register 7b via the signal line 7g.

, 7: Peripheral circuit 7
In order to perform an operation test independently of other peripheral circuits, set the selection signal R3 to the selector 7d to "1" and set the register 7
A route (arrow 0) is formed to route the data signal stored in the data signal stored in the selector 7d to the output signal R4 of the operating section 7C. Further, the selection signal S3 to the selector 7r is set to "0" to form a route (arrow p) for the output signal S1 of the actual operation section 7c to reach the register 7b via the selector 7f and the signal line 7g. As a result, input signals and output signals to the actual operating section 7C can be set by storing them in the register 7b using the CPU, and operation tests can be performed independently of the peripheral circuits of the circuit. Therefore, it is sufficient to simply connect the test pattern of peripheral circuit 7 with the test pattern of peripheral circuit 2.3.

2 7 CPUI sends 0 selection signal P to register 2b' of peripheral circuit 2.
"1" is written as the selection signal R3, and "0" is written in the register 7b of the peripheral circuit 7 as the selection signal R3.

Then, as shown by arrow q, a route is formed from register 2b' - selector 2d -> signal line 8 -> selector 7d -> signal line 7e -> register 7b.

The CPUI puts the test pattern into register 2b''.

By reading it from the register 7b, the connection of the signal line 8 can be tested.

The CPU of 7 3 writes "1" to the register 7b of the peripheral circuit 7 as the selection signal S3, and writes raJ to the register 3b' of the peripheral circuit 3 as the selection signal Q3.

Then, as shown by arrow r, a route is formed from register 7b to selector 7f to signal line 9 to selector 3d to signal line 3e to register 3b'.

CPUI puts test pattern into register 7b.

By reading it from register 3b', signal line 9
connection can be tested.

In this way, in the case of the second embodiment as well, most of the test patterns for each peripheral circuit created in advance can be combined, and the test patterns can be created extremely easily.

(e) Other embodiments The present invention is not limited to the above embodiments, and various modifications are possible9.
For example, although the above embodiment is a single-chip microcomputer having a CPU as a semiconductor device, the CPU
It can also be applied to semiconductor integrated circuits that do not have U inside. This semiconductor integrated circuit is composed of a circuit unit and a boat circuit. Furthermore, the semiconductor or sM circuit may have a circuit unit that does not directly exchange signals with other circuit units.

[Effects of the Invention] As described above, according to the present invention, signals that are directly output from a first circuit unit to another circuit unit without going through an internal bus can also be internally output from another circuit unit to a second circuit unit. Even signals that are input directly without going through the bus can be input and output from the outside via the first and second registers, so each circuit unit can be tested independently. . Even if the combination of peripheral circuits changes depending on the customer's specifications, testing can be easily performed using a common test pattern prepared in advance. Therefore, not only the peripheral circuits can be made into a common unit, but also most of the test patterns can be made common regardless of the product type, so that semiconductor integrated circuits with various specifications can be supplied in a shorter period of time.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of claim 1 of the present invention, Fig. 2 is an explanatory diagram of the principle of claim 2 of the present invention, and Fig. 3 is an explanatory diagram of the principle of claim 2 of the present invention.
4 is a block diagram of the first embodiment of the present invention, FIG. 5 is an explanatory diagram of the test pattern of the first embodiment of the present invention, and FIG. 6 is a diagram of the second embodiment of the present invention. FIG. 7 is a block diagram of a third embodiment of the present invention, FIG. 8 is a block diagram showing a single-chip microcomputer, and FIG. 9 is a block diagram showing details of a conventional semiconductor integrated circuit. 2d, 3d, 7d, 7f...Selector, ': 2e, 3
e, 7e, 7g...Signal line, 4...Internal bus, 4a...Address bus, 4b...Control bus, 4c...Data bus 5...Boat circuit, 6.8.9 ···Signal line. In the figure, 1...CPU, 2.3.7...Peripheral circuit, 2a, 3a, 7a...Address decoder, 2b, 2b
', 3b, 3b', 7b... register, 2c, 3c
, 7cm・-actual part,

Claims (1)

[Claims] 1. An internal bus (A), and a first register (B1) connected to the internal bus (A).
), and a first production section (B2) connected to the first register (B1) and performing a predetermined function, the first production section (B2) is connected to another circuit unit. a first circuit unit (B) that outputs a signal to the internal bus (A) without going through the internal bus (A); and a second register (C1) connected to the internal bus (A).
) and a second production unit (C2) that is connected to the second register (C1) and executes a predetermined function, the signal from the first circuit unit (B) is a second circuit unit (C) that receives signals from the production section (C2) of the second circuit without going through the internal bus (A); and an input/output circuit (C) that is connected to the internal bus (A) and exchanges signals with the outside. D) In the semiconductor integrated circuit comprising: 1 signal line (B3)
The second circuit unit (C) has a connection from the first circuit unit (B) to the internal bus (A).
The signal input without going through the second register (C1
) is selected based on the selection signal to select the signal from the second
a selector (C3) that outputs the signal selected by the selector (C2) to the production section (C2) of the second
A semiconductor integrated circuit comprising a second signal line (C4) for transmitting data to a register (C1). 2. The semiconductor integrated circuit according to claim 1, wherein the first
The circuit unit (B) selects the signal output from the first production section (B2) and the signal from the first register (B1) based on a selection signal, and outputs the signal to the second circuit. A semiconductor integrated circuit comprising a second selector (B4) that outputs an output to the unit (C) without going through the internal bus (A). 3. The semiconductor integrated circuit according to claim 1 or 2, further comprising: a third register (E1) connected to the internal bus (A);
), a third production unit (E2) connected to the third register (E1) and performing a predetermined function, and a third production unit (E2) that is connected to the third register (E1) and performs a predetermined function;
The signal input without going through the third register (E1
) is selected based on the selection signal to select the signal from the third
a third selector (E3) that outputs the signal to the production unit (E2); and a third signal line (E3) that transmits the signal selected by the third selector (E3) to the third register (E1). E
4), and selecting the signal output from the third production section (E2) and the signal from the third register (E1) based on a selection signal to select the signal output from the second circuit unit (C). a fourth selector (E5) that outputs a signal to the third register (E1) without going through the internal bus (A); 4 signal line (E6)
A semiconductor integrated circuit further comprising a third circuit unit (D).