JPH02242336A - Program control method and processor executing the same - Google Patents

Abstract

PURPOSE:To improve the transfer efficiency, and also, to reduce a program area of a system memory by counting the number of fundamental parameters and the number of times of execution to the fundamental parameter. CONSTITUTION:In the case of processing continuously plural parameters (XS0, YS0), (XE0, YE0), (XS1, YS1), (XE1, YE1),... with respect to one command, a seg ment generating command is only one, and by this one command, the parameters (XS0, YS0), (XE0, YE0), (XS1, YS1), (XE1, YE1),... are all processed. Therefore, in the command, the number of fundamental parameters BP and the number of times of repetition NP of the fundamental parameter are contained. Accord ingly, it will suffice that the command is fetched and decoded only once against the repeated fetch of the parameter. In such a way, the transfer efficiency in the case of processing continuously plural parameters with respect to one command is improved.

Description

[Detailed Description of the Invention] [Summary] A programmed control method used for graphic processing, etc., in particular,
Regarding the improvement of the programmed control method when transferring parameters repeatedly, we have developed a programmed control method that improves transfer efficiency and reduces the program area of system memory when processing multiple parameters in succession for one command. For the purpose of providing a control method, when multiple parameters are continuously processed for the same command, the number of basic parameters required for one execution of the command and the number of consecutive executions of the basic parameters, or Include the total number of parameters,
Processing of the command involves fetching and decoding the command, fetching only the necessary basic parameters out of multiple parameters as a result of this decoding, executing the command on the fetched parameters, and repeating this execution for the number of consecutive executions. or until the total number of parameters is reached.

[Industrial application field]

The present invention relates to a programmed control system used in graphical processing, and more particularly to an improvement in a programmed control system when parameters are transferred repeatedly.

[Conventional technology]

Generally, there are two methods for fetching commands: a method in which the command itself becomes a bus master and is fetched from the system memory, and a method in which the command is written from an external bus master such as a CPU.

In an image processing apparatus that displays graphics and the like on a CRT, the same command is frequently executed repeatedly.

For example, the starting point (XS., Ys.) and the ending point (Xta,
Line segment connecting Yto), starting point CXs+, ¥s
+) and the end point (X□, Y,), the starting point (X
sz, Ysg) and the end point (Xgz, Ysg), the contents of the program area of the system memory are divided into lines as shown in Figure 8. It consists of a continuous set of a minute generation command and start point/end point parameters.

The processing procedure for executing this is as shown in FIG. 9, where each start point/end point parameter (XS□, Ysi), (X□)

YEi) (i = 0, 1, 2, ...) requires four states: command fetch, command decode, parameter fetch, and execution; therefore, command-parameter, command-parameter, command-
It is necessary to fetch commands such as parameters, etc., resulting in problems such as a decrease in transfer efficiency and an increase in the program area of the system memory.

Therefore, an object of the present invention is to provide a programmed control method that improves transfer efficiency and reduces the program area of system memory when processing multiple parameters for one command in succession. .

[Means to solve the problem]

Means for solving the above problems are shown in FIGS. 1 to 3. In FIG. 1, multiple parameters (Xso,
Yso), (XE(1,Yio), CXs+, Ys
+), (Xz+, Yi+), . . . are sequentially processed. In this case, the line segment generation command is 1
and this one command sets the parameters (X, ., Y, .), (Xto , Yio), (
x, , y□), (XEI, Yt+), . . . are all processed. For this reason, the command is configured as shown in FIG.
(n in the illustrated example) is included. In FIG. 2, the OP code indicates the operand of the command, the mode indicates the execution mode of the command, and the register address indicates the address of the register when the command accesses the register.

The contents of the system memory shown in FIG. 1 are processed according to the processing procedure shown in FIG. That is, for the first start point/end point parameters (X, .+Y, .), (xi., Yio),
It is performed in four states: command fetch, command decode, parameter, and execution, but the next start point/end point parameters CXs+, Ys+), (Xi+, Yt+)
, . . ., the two states of command fetch and command decode are not performed, but only the two states of fetching the start point/end point parameter and its execution.

Therefore, the microprocessor for executing the above processing procedure is provided with a counter for counting the number of basic parameters and a counter for counting the number of times the basic parameters are executed.

[For production]

According to the above-described means, only one command fetch and decode is required for repeated parameter fetches.

〔Example〕

FIG. 4 is a block circuit diagram showing an example in which the present invention is applied to an image processing device. In FIG. 4, reference numeral 1 denotes an image processing processor, which rewrites the contents of the image memory 3 based on the contents of the system memo +72. The contents of the image memory 3 are displayed on the CRT 4.

FIG. 5 is a detailed block circuit diagram of the image processing processor of FIG. 4. In FIG. 5, the image processing processor 1 includes a command fetch control unit 11 that fetches commands and parameters, a command decode/execution unit 12 that decodes and executes commands, an external input/output interface 13 with the system memory 2, and an image memory. 3 and an external input/output interface 14. The command fetch control unit 11 includes a command fetch control circuit If, a command register 112, a mode decoder 113, and a parameter transfer counter 114.

A signal WRCMD is input and output between the command fetch control unit II and the command decode/execution unit 12.

RPRA, PEND, and EMPT have the following functions.

WRCMD: Command transfer command signal WRPRA
: Parameter transfer command signal PEND : Parameter transfer end signal EMPT : Parameter receivable signal Also, signal 1? from parameter transfer counter 114 to command fetch control circuit 111? END is an execution repetition end signal.

For example, the processing procedure shown in FIG. 3 is performed as follows. First, from the command fetch control circuit 111
When the RCMD signal is sent out, the command is taken in from the system memory 2 via the external interface 13 to the command decode/execution unit 12, and the command is decoded. At the same time, the command is taken into the command register 112, and the commands BP and NP taken into the command register 112 are respectively set in the parameter transfer counter 114. Further, the operating gin code section MD is decoded by the mode decoder 113 and a count mode is set. When the decoding is completed, next, the command decode/execution unit I2 sends an EMPT signal to the command fetch control circuit 111, and in response, the command fetch control circuit 111 sends a WRPRA signal, and sets the parameters (Xxo, Yso), (X!O.

YEO) is transferred to the command decode/execution unit 12 and taken in. At this time, the number of parameters to be transferred is monitored by the command fetch control circuit 111, and each time a parameter is transferred, a count signal CNT is sent to the parameter transfer counter 114, and the number of parameters (in the example of FIG. 3, 2) is monitored. Count. When the number of parameters reaches the basic number of parameters (BP), the parameter transfer counter 114 sends a PEND signal to the command fetch control circuit 111 and command decode/execution unit 12. As a result, the command decode/execution unit 12 executes the line segment generation command for the parameters (Xso, Yio) and (XEIl, Yto). Note that the number of executions is counted by the parameter transfer counter 114.

When the execution is finished, the command decoding/execution unit 12 then executes E
The MPT signal is sent to the command fetch control circuit 111, and in response, the command fetch control circuit 111 outputs the WR
Send the PRA signal and set the parameter (Xs'.

Y, 1), (XEI, YE+) are command decode/
It will be transferred to the execution unit 12 and taken in. At this time, the number of parameters transferred is monitored by the command fetch control circuit 111, and each time a parameter is transferred, a count signal CNT is sent to the parameter transfer counter 114 to count the number of parameters. When the number of parameters reaches the basic parameter number (BP), the parameter transfer counter 114 sends the PEND signal to the command fetch control circuit 111 and command decode/execution unit 12 again. As a result, the command decode/execution unit 12 executes the line segment generation command for the parameters (Xs+, Ys+) and (X□, Y□).

The above-mentioned two states of parameter fetch and execution are repeatedly performed, and when this has been performed for the number of repetitions (NP) or a predetermined number of parameters, the parameter transfer counter 114 sends a REND signal to the command fetch control circuit 111. Execution of the series of line segment generation commands ends.

FIG. 6 is a detailed block circuit diagram of the parameter transfer counter 114 of FIG. That is, 1141 is a basic parameter counter, which is a down counter in which the number of basic parameters is set and which decrements by 1 each time a parameter count signal CNT is received.

A repetition number counter 1142 counts the number of repetitions for each basic parameter or the number of transfer parameters. This switching is performed by a switching circuit 1143 controlled by mode decoder 113.

That is, in the former case, the basic parameter counter 1
The repetition number counter 1142 is set to 1 each time a borrow signal is generated when the counter value of 141 becomes "111".
On the other hand, in the latter case, the repetition number counter 1142 is counted up every time the parameter count signal CNT is generated.
is incremented by 1 count.

1144 is a repetition number register. This register 11
The number of repetitions (NP) is set in 44, but NP may be set as is by the shifter 1145, or NP/8 may be set.

Reference numeral 1146 denotes a coincidence determination circuit for controlling coincidence between the value of the repetition number counter 1142 and the value of the repetition number register 1144, and when these values match, the REN
Two signals, a D signal and a PEND signal, are sent out. In addition, 1
147 is a switching circuit that turns on and off the CNT signal; 114;
8 is an OR circuit.

The operation of the circuit shown in FIG. 6 will be explained in accordance with modes (1) to (V) shown below.

In the case of mode I shown in FIG. 7A, in which parameters are transferred (number of execution units per parameter) x (number of repetitions), the mode decoder 113 switches the switching circuit 1143 to the borrow signal side of the basic parameter counter 1141, and , shifter 1145 is set to 0 bit shift, and switching circuit 1
Turn on 147. In mode I, the number of basic parameters (for example, 32 bits) that constitute one execution unit is m
(BP=m-1), and the number of repetitions is n (NP
= n-1), and therefore mXn parameter transfers are performed. That is, basic parameter counter 1
The BP field of the command is set in 141, and the NP field of the command is shifted by 0 bits by a shifter and set in the repetition number register 1142.

When the parameter count signal CNT is input, the basic parameter counter 1141 is counted down by 1, and when the basic parameter counter 1141 reaches 111'', the PEND signal is sent out by the borrow signal.As a result, the repetition counter 1142 is counted up by 1, The BP field of the command is reset in the basic parameter counter 1141.The above operation is repeated until the output value of the repetition counter 1142 matches the value of the repetition number register 1144.As a result, when a match is detected, the REND signal is output. The parameter transfer ends.

In the case of mode H in which the parameter transfer specified by the number of repetitions shown in FIG.
5 to 0 bit shift and turn on the switching circuit 1147. In mode (2), one execution unit is n pieces because it is used for a data transfer command to the image memory 3. However, since this command transfers data as a command parameter, the number of data that can be transferred at one time is the number of parameter buffers in the command decoding/execution unit 12. Therefore, the number of buffers, for example 5, is set as the number of basic parameters. The number of repetitions is defined by the number of parameters n. Therefore, n parameter transfers are performed. That is, since the BP field of the command is "000", the basic parameter counter 1141 is set to the number of buffers "100" (=5-1), and the command NP field is shifted by 0 bits by the shifter 1145 and stored in the repetition number register 1144. Set. When the parameter count signal CNT is input, the basic parameter counter 1141 is counted down by one, and the repetition number counter 1142 is counted up by one. As a result,
When the basic parameter counter 1141 reaches "111", a PEND signal is sent. Basic parameter counter 11
41 is reset to "100'". The above operation is repeated until the output value of the repetition number counter 1142 matches the value of the repetition number register 1144. If a match is found, R
At the same time as the END signal is asserted, the PEND signal is sent out even if the value of the basic parameter counter 1141 is not "111#", and the REND signal is sent out to end the parameter transfer.

In the case of mode (2) shown in FIG. 7C, it is almost the same as mode (2) shown in FIG. 7B, that is, the number of parameters transferred at the first time is m, and thereafter it is the same as mode (2). This mode (■) is used for polyline (continuous line), trapezoid, etc. commands.

Taking a polyline as an example, two parameters are required to draw the first line, and subsequent lines can be drawn with one parameter.

This is because it is necessary to distinguish between the first line and subsequent lines, and it is necessary to specify the number of parameters only for the first parameter transfer.

In the case of mode (2) shown in FIG. 7D, the registers of the command decode/execution unit 12 are set, and the number of parameters specified by the number of repetitions BP is transferred. Since the data is not transferred to the buffer of the command decoding/execution unit 12, the transfer is performed continuously until all parameters are transferred. That is, the mode decoder 113
143 to the parameter count signal CNT side of the command fetch control circuit 111, and shifter 1145 to O
bit shift and turn off the switching circuit 1147.

In mode (2), there is no one execution unit, that is, the number of repetitions of basic parameters is only n (NP=n-1), and therefore n parameter transfers are performed. That is, the basic parameter counter 1141 is set to a BP field (the value is arbitrary). The NP field of the command is shifted by 0 bits by the shifter and stored in the repetition number register 1.
144.

When the parameter count signal CNT is input, the repetition number counter 1142 is counted up by 1, but the switching circuit 1
147 is off, the basic parameter counter 114
1 is ignored. The above operation is repeated by the number counter 114.
Repeat until the output value of 2 matches the repetition number register 1144. When a match is detected, it sends a REND signal,
Parameter transfer ends.

In the case of FIG. 7E, one parameter of the command is 4 bits, and the number of repetitions is specified by the number of parameters. In this case, in order to write to the buffer of the command decode/execution unit 12, it is necessary to send out a PRNO signal for each number of buffers. Therefore, the mode decoder 113 switches the switching circuit 1143 to the borrow signal side of the basic parameter counter 1141, sets the shifter 1145 to 3-bit shift (÷8), and turns on the switching circuit 1147. Therefore, the basic parameter counter 1141 is set to the number of execution section buffers "100m", and the number of command N
The P field is shifted by 3 bits (÷8
) and set in the repetition number register 1144. When parameter count signal CINT is input, basic parameter 1
141 is counted down by 1, and the repetition number counter 11
42 is counted up by one. As a result, when the basic parameter counter 1141 becomes "111", a PEND signal is sent out.

Then, the basic parameter counter 1141 is reset to the number of execution unit buffers, 100. The above operation is repeated and the output value of the number counter 1142 is stored in the number of repetitions register 114.
Repeat until it matches 4. REND when a match is found
The basic parameter counter 114 simultaneously sends the signal.
Even if the value of 1 is not "Ill", a PEND signal is sent, and a REND signal is sent, and the parameter transfer ends.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to repeatedly specify parameters for all commands.
n-1 when the same command is executed n times consecutively
This eliminates the need to transfer commands twice, increasing command transfer efficiency and reducing the program area in the system memory. This makes it possible to reduce the bus monopoly rate, thereby increasing the efficiency of the entire system.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the storage contents of the system memory to explain the basic principle of the present invention. FIG. 2 is a field configuration diagram of commands according to the present invention. FIG. 3 is a diagram showing the processing procedure of the microprocessor according to the present invention. 4 is a block circuit diagram showing an image processing device to which the present invention is applied; FIG. 5 is a detailed block circuit diagram of the image processing processor of FIG. 4; FIG. 6 is a parameter transfer counter of FIG. 3. A detailed block circuit diagram of FIGS. 7A to 7E are diagrams showing the contents of the system memory for explaining the operation of FIG. 6, FIG. 8 is a diagram showing the contents of the conventional system memory, and FIG. 1 is a diagram showing a processing procedure of a conventional microprocessor. 11... Command fetch control unit, 12... Command decode/execution unit, 13, 14.
...External interface, III...Command fetch control circuit, 112...Command register, 113...Mode register, 114...Parameter transfer counter, 1141...
Basic parameter counter, 1142...Repetition number counter, 1144...Repetition number register.

Claims (1)

[Claims] 1. In a programmed control method for continuously processing a plurality of parameters for the same command, the command includes a number of basic parameters (BP) necessary for one execution of the command, and The processing of the command includes a step of fetching and decoding the command, and as a result of the decoding, fetching only the necessary basic parameter from among the plurality of parameters and performing the processing of the command. A programmed control method comprising the steps of: executing the command on the fetched parameters; and repeating the execution of the command the number of consecutive executions. 2. A microprocessor for executing the programmed control method according to claim 1, wherein a command fetch section of the microprocessor includes a command register (112) for storing the command; and a command register (112) for storing the command; Number of basic parameters (B
a basic parameter counting means (1141) for counting the number of fetched parameters based on P); and the number of consecutive executions (NP) from the command register.
11. A processor comprising an execution number counting means (1142) for counting the number of executions of the command based on the number of executions of the command. 3. In a programmed control method for continuously processing multiple parameters for the same command, the command includes the basic number of parameters (BP) required for one execution of the command and the number of parameters required for continuous execution of the command. a number of parameters (NP), and the processing of the command includes a step of fetching and decoding the command; as a result of the decoding, only the necessary basic parameters are fetched from among the plurality of parameters, and the fetched parameters are A programmed control method comprising the steps of: executing the command for a given number of parameters; and repeating the execution of the command until the number of consecutive parameters has been processed. 4. A microprocessor for executing the programmed control method according to claim 3, wherein a command fetch section of the microprocessor comprises a command register (112) for storing the command; and a command register (112) for storing the command; Number of basic parameters (B
a basic parameter counting means (1141) for counting the number of parameters fetched based on the number of parameters fetched based on the number of parameters fetched from the command register (1141);
NP) for counting the number of executions of the command.