JPH0224023B2 - - Google Patents
Info
- Publication number
- JPH0224023B2 JPH0224023B2 JP59077710A JP7771084A JPH0224023B2 JP H0224023 B2 JPH0224023 B2 JP H0224023B2 JP 59077710 A JP59077710 A JP 59077710A JP 7771084 A JP7771084 A JP 7771084A JP H0224023 B2 JPH0224023 B2 JP H0224023B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- field effect
- type
- effect transistor
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 17
- 238000010438 heat treatment Methods 0.000 claims description 14
- 239000007772 electrode material Substances 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 238000004544 sputter deposition Methods 0.000 claims description 7
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000007731 hot pressing Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 239000000843 powder Substances 0.000 claims description 2
- 239000010408 film Substances 0.000 claims 7
- 239000010409 thin film Substances 0.000 claims 2
- 238000005468 ion implantation Methods 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 4
- 229910001425 magnesium ion Inorganic materials 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010494 dissociation reaction Methods 0.000 description 2
- 230000005593 dissociations Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- 241000282326 Felis catus Species 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/082—Ion implantation FETs/COMs
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/088—J-Fet, i.e. junction field effect transistor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
（発明の技術分野）
本発明は、GaAsを用いて構成されるpn接合ゲ
ート構造の電界効果トランジスタ（Ｊ−FET）
及びその製造方法に関する。Detailed Description of the Invention (Technical Field of the Invention) The present invention relates to a field effect transistor (J-FET) with a pn junction gate structure constructed using GaAs.
and its manufacturing method.
（発明の技術的背景とその問題点）
従来より、GaAs結晶基板を用いたＪ−FETが
知られている。その代表的な製造方法は次の通り
である。まず、半絶縁性GaAs基板にイオン注入
法によりｎ型活性層を形成する。次に基板表面を
絶縁膜で覆い、これをエツチングしてゲート部分
に開口を持つマスクを形成する。そして、Znな
どのアクセプタ不純物を含む金属蒸気中において
高温熱処理することにより、Znをｎ型活性層に
拡散してpn接合を形成し、その後ｐ型層にゲー
ト電極を形成する。(Technical background of the invention and its problems) J-FETs using GaAs crystal substrates have been known. A typical manufacturing method thereof is as follows. First, an n-type active layer is formed on a semi-insulating GaAs substrate by ion implantation. Next, the surface of the substrate is covered with an insulating film, and this is etched to form a mask having an opening in the gate area. Then, by performing high-temperature heat treatment in metal vapor containing acceptor impurities such as Zn, Zn is diffused into the n-type active layer to form a p-n junction, and then a gate electrode is formed in the p-type layer.
この方法においては、Znを高温で拡散する際
にGaAs基板中のAsの解離を抑制するために、例
えば金属蒸気中にAsを含ませることが必要であ
る。このためpn接合の深さの制御がむずかしい。
特に、接合深さの制御性として0.1μｍ程度の高精
度が要求されるエンハンスメント型Ｊ−FETは、
この方法では再現性よく作ることが困難である。 In this method, it is necessary to include As in the metal vapor, for example, in order to suppress the dissociation of As in the GaAs substrate when Zn is diffused at high temperatures. This makes it difficult to control the depth of the pn junction.
In particular, enhancement type J-FETs require high accuracy of around 0.1 μm for controllability of junction depth.
With this method, it is difficult to produce with good reproducibility.
GaAs基板中のAsの解離を防止するため、Zn
をイオン注入し、その後熱処理することにより
pn接合を形成することも試みられている。しか
しこの方法でも、熱処理工程でZnの再拡散が生
じるため、制御性よく浅いpn接合を形成するこ
とは難しい。 To prevent the dissociation of As in the GaAs substrate, Zn
By ion-implanting and then heat-treating
Attempts have also been made to form p-n junctions. However, even with this method, Zn re-diffusion occurs during the heat treatment process, making it difficult to form a shallow p-n junction with good control.
またいずれの方法でも、ゲート抵抗を小さくす
るためにｐ型層に金属膜によるゲート電極を形成
することが必要である。従来はこのゲート電極を
フオトリソグラフイにより形成しているが、この
場合マスクあわせの余裕を必要とするため、第１
図のような構造となる。１１が半絶縁性GaAs基
板、１２がｎ型活性層、１３がｐ型層、１４が絶
縁膜、１５がゲート電極である。図のようにゲー
ト電極１５は絶縁膜１４上に一部重なつた状態に
なる。このためゲートに不要な寄生容量が入り、
Ｊ−FETの高速動作を妨げる原因となる。 In either method, it is necessary to form a gate electrode made of a metal film on the p-type layer in order to reduce gate resistance. Conventionally, this gate electrode is formed by photolithography, but in this case, a margin for mask alignment is required, so the first
The structure will be as shown in the figure. 11 is a semi-insulating GaAs substrate, 12 is an n-type active layer, 13 is a p-type layer, 14 is an insulating film, and 15 is a gate electrode. As shown in the figure, the gate electrode 15 partially overlaps the insulating film 14. This causes unnecessary parasitic capacitance to enter the gate.
This causes interference with high-speed operation of the J-FET.
（発明の目的）
本発明は上記した問題を解決し、簡単な工程で
優れた素子特性を得ることを可能としたGaAsを
用いたＪ−FET及びその製造方法を提供するこ
とを目的とする。(Objective of the Invention) An object of the present invention is to provide a J-FET using GaAs and a method for manufacturing the same, which solves the above-mentioned problems and makes it possible to obtain excellent device characteristics through simple steps.
（発明の概要）
本発明にかかるＪ−FETは、ｎ型活性層が形
成されたGaAs基板に族元素を含むＷ，Taまた
はMoのナイトライドからなるゲート電極が形成
され、このゲート電極直下にゲート電極に自己整
合されてｐ型層が形成された構造を有する。(Summary of the Invention) In the J-FET according to the present invention, a gate electrode made of W, Ta, or Mo nitride containing group elements is formed on a GaAs substrate on which an n-type active layer is formed, and the gate electrode is formed directly under this gate electrode. It has a structure in which a p-type layer is formed in self-alignment with the gate electrode.
本発明の方法は、ｎ型活性層が形成された
GaAs基板にｐ型不純物としての族元素を含む
Ｗ，TaまたはMoのナイトライドからなるゲート
電極材料膜を形成し、このゲート電極材料膜をパ
ターニングしてゲート電極を形成した後、熱処理
をしてゲート電極中の族元素を基板に拡散させ
てｐ型層を形成する。 In the method of the present invention, an n-type active layer is formed.
A gate electrode material film made of W, Ta, or Mo nitride containing group elements as p-type impurities is formed on a GaAs substrate, and after patterning this gate electrode material film to form a gate electrode, heat treatment is performed. The group element in the gate electrode is diffused into the substrate to form a p-type layer.
（発明の効果）
本発明によるＪ−FETは、ゲート領域のｐ型
層とゲート電極とが自己整合された構造を有する
ため、ゲート抵抗が十分に小さく、且つ不要な寄
生容量が入らないため、優れた素子特性を示す。(Effects of the Invention) Since the J-FET according to the present invention has a structure in which the p-type layer in the gate region and the gate electrode are self-aligned, the gate resistance is sufficiently small and no unnecessary parasitic capacitance is introduced. Shows excellent device characteristics.
また本発明の方法によれば、パターニングされ
たゲート電極を固相拡散源としてｐ型層を形成す
るから、ｐ型層形成とゲート電極形成を別々の工
程で行なう従来の方法に比べて、工程が簡単であ
り、シヨツトキー・ゲート型FETと同程度の工
程数でＪ−FETを作ることができる。また固相
拡散を利用するから、浅いpn接合を制御性よく
形成することができる。またゲート領域のｐ型層
とゲート電極が自己整合されるため、ゲート抵抗
の低減、寄生容量の低減が図られ、優れた素子特
性が得られる。 Furthermore, according to the method of the present invention, since a p-type layer is formed using a patterned gate electrode as a solid-phase diffusion source, the process is faster than the conventional method in which p-type layer formation and gate electrode formation are performed in separate steps. is simple, and a J-FET can be manufactured with the same number of steps as a Schottky gate type FET. Furthermore, since solid-phase diffusion is used, shallow p-n junctions can be formed with good controllability. Furthermore, since the p-type layer in the gate region and the gate electrode are self-aligned, gate resistance and parasitic capacitance are reduced, and excellent device characteristics are obtained.
（発明の実施例）
本発明の実施例を第２図を参照して説明する。
Crドープの半絶縁性GaAs基板２１にSiをイオン
注入してｎ型活性層２２を形成する。イオン注入
条件は、例えば加速エネルギー100KeV，ドーズ
量３×1012／cm2とし、その後、As雰囲気中で850
℃、15分のキヤツプレスアニールを施す。この後
ｎ型活性層２２の表面にゲート電極材料膜として
Znを５％含むタングステン・ナイトライド
（WN）膜２３を約2000Å形成する（ａ）。この
WN膜２３の形成は、WNとZnの粉末混合物をホ
ツトプレスして得られたターゲツトを用いたRF
スパツタリングによる。この後、WN膜２４上全
面にCVD法によりSiO2膜２４を堆積し、次いで
ホトリソグラフイによりゲート領域にレジストマ
スクを形成する（ｂ）。そしてプラズマエツチン
グによりSiO2膜２４およびWN膜２３をエツチン
グした後、Siをイオン注入してソース、ドレイン
領域にイオン注入層２６，２７を形成する（ｃ）。
この時のイオン注入条件は、例えば加速エネルギ
ー150KeV、ドーズ量５×1013／cm2とする。この
後SiO2膜２４およびレジストマスク２５を除去
し、基板全面にPSG膜２８を堆積して約800℃、
約30分の熱処理を施す。これによりゲート電極と
してパターニングされたWN膜２３中のZnが基
板に拡散されてｐ型層２９が形成され、同時にソ
ース、ドレイン領域に注入されたSiイオンが活性
化されてn+層２６′，２７′が形成される（ｄ）
この後、PSG膜２８にコンタクトホールを開け、
ソース、ドレイン領域にAuGe／Niからなるオー
ミツク電極３０，３１を形成する（ｅ）。(Embodiment of the invention) An embodiment of the invention will be described with reference to FIG.
An n-type active layer 22 is formed by ion-implanting Si into a Cr-doped semi-insulating GaAs substrate 21 . The ion implantation conditions are, for example, an acceleration energy of 100 KeV and a dose of 3×10 12 /cm 2 , and then an ion implantation process of 850
℃, 15 minutes cat press annealing. After this, a gate electrode material film is formed on the surface of the n-type active layer 22.
A tungsten nitride (WN) film 23 containing 5% Zn is formed to a thickness of about 2000 Å (a). this
The WN film 23 was formed by RF using a target obtained by hot pressing a powder mixture of WN and Zn.
By sputtering. Thereafter, a SiO 2 film 24 is deposited on the entire surface of the WN film 24 by CVD, and then a resist mask is formed in the gate region by photolithography (b). After etching the SiO 2 film 24 and WN film 23 by plasma etching, Si ions are implanted to form ion implantation layers 26 and 27 in the source and drain regions (c).
The ion implantation conditions at this time are, for example, an acceleration energy of 150 KeV and a dose of 5×10 13 /cm 2 . After that, the SiO 2 film 24 and the resist mask 25 are removed, and a PSG film 28 is deposited on the entire surface of the substrate, and heated at about 800°C.
Heat treatment for about 30 minutes. As a result, Zn in the WN film 23 patterned as a gate electrode is diffused into the substrate to form a p-type layer 29, and at the same time, Si ions implanted into the source and drain regions are activated to form an n + layer 26', 27' is formed (d)
After this, a contact hole is opened in the PSG film 28,
Ohmic electrodes 30 and 31 made of AuGe/Ni are formed in the source and drain regions (e).
このようにして、非常に簡単な工程で自己整合
型のＪ−FETが得られる。このＪ−FETは、ゲ
ート領域のｐ型層とゲータ電極が自己整合されて
形成されているため、ｐ型層が浅くてもゲート抵
抗は十分小さく、また不要な寄生容量が入らない
ため優れた素子特性が得られる。 In this way, a self-aligned J-FET can be obtained through a very simple process. Since this J-FET is formed by self-aligning the p-type layer in the gate region and the gate electrode, the gate resistance is sufficiently small even if the p-type layer is shallow, and there is no unnecessary parasitic capacitance, making it an excellent product. Device characteristics can be obtained.
前述の熱処理工程は不純物の活性化とゲート電
極からのZnの拡散のために行なうものであるか
ら、最低限600℃以上を必要とする。熱処理温度
の上限はゲート電極材料の融点やｎ型活性層の不
純物再拡散等を考慮して決められる。好ましい熱
処理温度範囲は600〜800℃である。この熱処理温
度と時間を制御することによつて、ゲート領域の
pn接合深さを高精度に制御することができる。
本実施例では、しきい値＋0.08Vのエンハンスメ
ント型Ｊ−FETを得ることができた。また本実
施例の場合、ゲート抵抗は殆どWN膜で決まり、
20μｍ×1.5μｍのゲート寸法で34Ωであつた。 The above-mentioned heat treatment process is performed to activate impurities and diffuse Zn from the gate electrode, so it requires a minimum temperature of 600°C or higher. The upper limit of the heat treatment temperature is determined in consideration of the melting point of the gate electrode material, the re-diffusion of impurities in the n-type active layer, and the like. The preferred heat treatment temperature range is 600-800°C. By controlling the temperature and time of this heat treatment, it is possible to
The p-n junction depth can be controlled with high precision.
In this example, an enhancement type J-FET with a threshold value of +0.08V could be obtained. In addition, in the case of this example, the gate resistance is mostly determined by the WN film,
The gate size was 20 μm x 1.5 μm and the resistance was 34 Ω.
上記実施例では、ゲート電極材料膜としてZn
を含むWN膜を用いたが、WNの他にMo，Taな
どの高融点金属ナイトライドを用いることができ
る。またｐ型不純物としてZnの他にBe，Mgなど
の族元素を用いることができる。 In the above example, Zn was used as the gate electrode material film.
Although a WN film containing WN was used, high melting point metal nitrides such as Mo and Ta can be used in addition to WN. In addition to Zn, group elements such as Be and Mg can be used as p-type impurities.
また上記実施例では、ｐ型不純物を含むターゲ
ツトを作つてこれをスパツタリングしたが、高融
点金属ナイトライドからなるターゲツトと族元
素からなるターゲツトを別々に一つのスパツタ装
置内に用意し、これらのターゲツトからの同時ス
パツタリングによりゲート電極材料膜を形成して
もよい。 Furthermore, in the above embodiment, a target containing a p-type impurity was prepared and sputtered. However, a target made of a high melting point metal nitride and a target made of a group element were prepared separately in one sputtering device, and these targets were sputtered. The gate electrode material film may be formed by simultaneous sputtering.
またターゲツトに予めｐ型不純物を含ませてお
く上記実施例では、ターゲツトの組成が得られる
Ｊ−FETの特性に大きく影響する。例えば、タ
ーゲツト中のｐ型不純物の分布の不均一性は得ら
れるＪ−FETの特性のばらつきの原因となる。
特にエンハンスメント型Ｊ−FETを作る場合は、
ターゲツト中のｐ型不純物量の不均一性がしきい
値制御上大きな問題となる。 Furthermore, in the above embodiment in which the target is pre-contained with p-type impurities, the composition of the target greatly influences the characteristics of the resulting J-FET. For example, non-uniformity in the distribution of p-type impurities in the target causes variations in the characteristics of the resulting J-FET.
Especially when making an enhancement type J-FET,
Non-uniformity in the amount of p-type impurities in the target poses a major problem in threshold control.
この点を解決するには、スパツタリングにより
Ｗ膜等を被着した後、イオン注入によりこれにｐ
型不純物をドープする方法が有効である。この方
法を用いた実施例を簡単に説明する。先の実施例
と同様に半絶縁性GaAs基板にｎ型活性層を形成
した後、その表面に純粋なＷ膜をスパツタリング
により2000Å堆積した。次いでMgイオンを加速
エネルギー150KeV、ドーズ量５×1014／cm2の条
件でイオン注入した。この条件ではMgイオンは
WN膜を突抜けることなく、全てWN膜中に止ま
つている。Mgイオンを選んだ理由は、Znよりも
質量が小さく、通常のイオン注入装置（最大加速
エネルギー200KeV）でWN膜中に深く注入する
ことができるからである。同様の理由でこのイオ
ン注入を利用する場合に、族元素としてBeを
用いることも有用である。WN膜中に注入された
Mgイオンは熱処理によりｎ型活性層に拡散さ
れ、先の実施例と同様のＪ−FETが得られた。
Mgの拡散速度はZnのそれより大きく、先の実施
例に比べて1/2程度の短い熱処理時間で先の実施
例のＪ−FETと同程度のしきい値が得られた。
この方法では、Ｊ−FETの特性の再現性が極め
て良好であつた。これは、イオン注入による不純
物量の制御が正確に行われるためと考えられる。 To solve this problem, after depositing a W film etc. by sputtering, ion implantation is applied to this film.
A method of doping with type impurities is effective. An example using this method will be briefly described. After forming an n-type active layer on a semi-insulating GaAs substrate as in the previous example, a pure W film of 2000 Å was deposited on its surface by sputtering. Next, Mg ions were implanted at an acceleration energy of 150 KeV and a dose of 5×10 14 /cm 2 . Under this condition, Mg ions are
All of it remains within the WN membrane without penetrating through it. Mg ions were chosen because they have a smaller mass than Zn and can be deeply implanted into the WN film using a normal ion implanter (maximum acceleration energy 200 KeV). When using this ion implantation for the same reason, it is also useful to use Be as a group element. Injected into WN membrane
Mg ions were diffused into the n-type active layer by heat treatment, and a J-FET similar to the previous example was obtained.
The diffusion rate of Mg is higher than that of Zn, and a threshold comparable to that of the J-FET of the previous example was obtained with a heat treatment time that was about half as short as that of the previous example.
With this method, the reproducibility of the J-FET characteristics was extremely good. This is considered to be because the amount of impurities is accurately controlled by ion implantation.
以上の説明では、専ら半絶縁性GaAs基板を用
いたが、本発明は、ｐ型GaAs基板を用いてＪ−
FETを作る場合にも有効である。 In the above explanation, only a semi-insulating GaAs substrate was used, but in the present invention, a p-type GaAs substrate is used.
It is also effective when making FETs.
第１図は従来のGaAsを用いたＪ−FETのゲー
ト電極構造を示す図、第２図は本発明の一実施例
のＪ−FETの製造工程を説明するための図であ
る。
２１……半絶縁性GaAs基板、２２……ｎ型活
性層、２３……Zn含有WN膜（ゲート電極材料
膜）、２４……SiO2膜、２５……レジストマス
ク、２６，２７……Siイオン注入層、２６′，２
７′……高濃度ｎ型層（ソース、ドレイン領域）、
２８……PSG膜、２９……ｐ型層（ゲート領
域）。
FIG. 1 is a diagram showing the gate electrode structure of a conventional J-FET using GaAs, and FIG. 2 is a diagram for explaining the manufacturing process of a J-FET according to an embodiment of the present invention. 21... Semi-insulating GaAs substrate, 22... N-type active layer, 23... Zn-containing WN film (gate electrode material film), 24... SiO 2 film, 25... Resist mask, 26, 27... Si Ion implantation layer, 26', 2
7'...high concentration n-type layer (source, drain region),
28...PSG film, 29...p-type layer (gate region).
Claims (1)
基板の活性層表面に互いに離間して設けられた高
濃度ｎ型のソース、ドレイン領域と、このソー
ス、ドレイン領域間の基板上に設けられた族元
素を含むＷ，TaまたはMoのナイトライドからな
るゲート電極と、このゲート電極直下の活性層内
にゲート電極と自己整合されて設けられたｐ型層
とを具備したことを特徴とするGaAs電界効果ト
ランジスタ。 ２ 前記ゲート電極は、族元素としてBe，Mg
またはZnを含むものである特許請求の範囲第１
項記載のGaAs電界効果トランジスタ。 ３ ｎ型活性層が形成されたGaAs基板に族元
素を含むＷ，TaまたはMoのナイトライドからな
るゲート電極材料膜を形成する工程と、このゲー
ト電極材料膜をパターニングしてゲート電極を形
成する工程と、この後熱処理して前記ゲート電極
中の族元素を基板に拡散させて前記ｎ型活性層
表面にｐ型層を形成する工程と、ソース、ドレイ
ン領域に高濃度ｎ型層を形成する工程とを備えた
ことを特徴とするGaAs電界効果トランジスタの
製造方法。 ４ 前記熱処理は、基板全面を絶縁膜で覆つた状
態で600〜800℃で行なう特許請求の範囲第３項記
載のGaAs電界効果トランジスタの製造方法。 ５ 前記ゲート電極材料膜は、族元素として
Be，MgまたはZnを含むものである特許請求の範
囲第３項記載のGaAs電界効果トランジスタの製
造方法。 ６ 前記ゲート電極材料膜を形成する工程は、ナ
イトライドと族元素の粉末混合物をホツトプレ
スして得られたターゲツトを用いてスパツタリン
グを行なうものである特許請求の範囲第３項記載
のGaAs電界効果トランジスタの製造方法。 ７ 前記ゲート電極材料膜を形成する工程は、ナ
イトライドからなるターゲツトと族元素からな
るターゲツトから同時にスパツタリングを行なう
ものである特許請求の範囲第３項記載のGaAs電
界効果トランジスタの製造方法。 ８ 前記ゲート電極材料膜を形成する工程は、ナ
イトライドからなる薄膜を被着する工程と、この
薄膜中に族元素をイオン注入する工程とからな
る特許請求の範囲第３項記載のGaAs電界効果ト
ランジスタの製造方法。 ９ 前記ソース、ドレインに高濃度ｎ型層を形成
する工程は、前記熱処理を行なう前に前記ゲート
電極をマスクとしてｎ型不純物をイオン注入し、
前記熱処理により注入不純物を活性化するもので
ある特許請求の範囲第３項記載のGaAs電界効果
トランジスタの製造方法。[Claims] 1. A GaAs substrate on which an n-type active layer is formed, highly doped n-type source and drain regions provided spaced apart from each other on the surface of the active layer of this substrate, and a structure between the source and drain regions. A gate electrode made of W, Ta, or Mo nitride containing a group element is provided on a substrate, and a p-type layer is provided in an active layer directly under the gate electrode in self-alignment with the gate electrode. A GaAs field effect transistor characterized by: 2 The gate electrode contains Be, Mg as group elements.
or the first claim that contains Zn
GaAs field effect transistor as described in . 3. Forming a gate electrode material film made of W, Ta, or Mo nitride containing group elements on the GaAs substrate on which the n-type active layer is formed, and patterning this gate electrode material film to form a gate electrode. a step of performing heat treatment to diffuse group elements in the gate electrode into the substrate to form a p-type layer on the surface of the n-type active layer; and forming a highly concentrated n-type layer in the source and drain regions. A method for manufacturing a GaAs field effect transistor, comprising the steps of: 4. The method of manufacturing a GaAs field effect transistor according to claim 3, wherein the heat treatment is performed at 600 to 800°C with the entire surface of the substrate covered with an insulating film. 5 The gate electrode material film contains as a group element
The method for manufacturing a GaAs field effect transistor according to claim 3, which contains Be, Mg or Zn. 6. The GaAs field effect transistor according to claim 3, wherein the step of forming the gate electrode material film is performed by sputtering using a target obtained by hot pressing a powder mixture of nitride and a group element. manufacturing method. 7. The method of manufacturing a GaAs field effect transistor according to claim 3, wherein in the step of forming the gate electrode material film, sputtering is performed simultaneously from a target made of nitride and a target made of a group element. 8. The GaAs field effect according to claim 3, wherein the step of forming the gate electrode material film comprises a step of depositing a thin film made of nitride, and a step of ion-implanting a group element into this thin film. Method of manufacturing transistors. 9. The step of forming a highly concentrated n-type layer in the source and drain includes ion-implanting n-type impurities using the gate electrode as a mask before performing the heat treatment,
4. The method of manufacturing a GaAs field effect transistor according to claim 3, wherein the heat treatment activates the implanted impurity.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59077710A JPS60220975A (en) | 1984-04-18 | 1984-04-18 | Gaas field-effect transistor and manufacture thereof |
| EP84309167A EP0158752B1 (en) | 1984-04-18 | 1984-12-31 | Method of producing a gaas jfet with self-aligned p-type gate |
| DE8484309167T DE3481466D1 (en) | 1984-04-18 | 1984-12-31 | METHOD FOR PRODUCING A GAAS JFET WITH SELF-ADJUSTED P-TYPE GATE. |
| US07/476,140 US5015596A (en) | 1984-04-18 | 1990-02-08 | Method of making a GaAs JFET with self-aligned p-type gate by outdiffusion of dopont from the metallic gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59077710A JPS60220975A (en) | 1984-04-18 | 1984-04-18 | Gaas field-effect transistor and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60220975A JPS60220975A (en) | 1985-11-05 |
| JPH0224023B2 true JPH0224023B2 (en) | 1990-05-28 |
Family
ID=13641444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59077710A Granted JPS60220975A (en) | 1984-04-18 | 1984-04-18 | Gaas field-effect transistor and manufacture thereof |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5015596A (en) |
| EP (1) | EP0158752B1 (en) |
| JP (1) | JPS60220975A (en) |
| DE (1) | DE3481466D1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5231474A (en) * | 1986-03-21 | 1993-07-27 | Advanced Power Technology, Inc. | Semiconductor device with doped electrical breakdown control region |
| JPS644079A (en) * | 1987-06-26 | 1989-01-09 | Yokogawa Electric Corp | Manufacture of junction type fet |
| JPS6468975A (en) * | 1987-09-09 | 1989-03-15 | Yokogawa Electric Corp | Manufacture of junction fet |
| JP3298313B2 (en) | 1994-06-10 | 2002-07-02 | ソニー株式会社 | Junction type field effect transistor and manufacturing method thereof |
| US5670393A (en) * | 1995-07-12 | 1997-09-23 | Lsi Logic Corporation | Method of making combined metal oxide semiconductor and junction field effect transistor device |
| JPH11274468A (en) * | 1998-03-25 | 1999-10-08 | Sony Corp | Ohmic electrode and its forming method, and laminate for forming ohmic electrode |
| US7217977B2 (en) * | 2004-04-19 | 2007-05-15 | Hrl Laboratories, Llc | Covert transformation of transistor properties as a circuit protection method |
| US6815816B1 (en) * | 2000-10-25 | 2004-11-09 | Hrl Laboratories, Llc | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering |
| US7049667B2 (en) | 2002-09-27 | 2006-05-23 | Hrl Laboratories, Llc | Conductive channel pseudo block process and circuit to inhibit reverse engineering |
| US6979606B2 (en) | 2002-11-22 | 2005-12-27 | Hrl Laboratories, Llc | Use of silicon block process step to camouflage a false transistor |
| AU2003293540A1 (en) | 2002-12-13 | 2004-07-09 | Raytheon Company | Integrated circuit modification using well implants |
| US7242063B1 (en) | 2004-06-29 | 2007-07-10 | Hrl Laboratories, Llc | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable |
| US7569873B2 (en) * | 2005-10-28 | 2009-08-04 | Dsm Solutions, Inc. | Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys |
| US8168487B2 (en) | 2006-09-28 | 2012-05-01 | Hrl Laboratories, Llc | Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer |
| US7772056B2 (en) * | 2007-06-18 | 2010-08-10 | University Of Utah Research Foundation | Transistors for replacing metal-oxide semiconductor field-effect transistors in nanoelectronics |
| US7648898B2 (en) * | 2008-02-19 | 2010-01-19 | Dsm Solutions, Inc. | Method to fabricate gate electrodes |
| RU2660296C1 (en) * | 2017-02-20 | 2018-07-05 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) | Method for making semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5315081A (en) * | 1976-07-27 | 1978-02-10 | Nec Corp | Junction type field effect transistor and its production |
| JPS5844771A (en) * | 1981-09-10 | 1983-03-15 | Mitsubishi Electric Corp | Junction type field effect transistor and manufacture thereof |
| JPS59213172A (en) * | 1983-05-19 | 1984-12-03 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL277812A (en) * | 1961-04-27 | |||
| US3601888A (en) * | 1969-04-25 | 1971-08-31 | Gen Electric | Semiconductor fabrication technique and devices formed thereby utilizing a doped metal conductor |
| US3768151A (en) * | 1970-11-03 | 1973-10-30 | Ibm | Method of forming ohmic contacts to semiconductors |
| JPS5413879A (en) * | 1977-07-01 | 1979-02-01 | Hitachi Ltd | Anti-vibration rubber equipped with vibration controller |
| JPS55153377A (en) * | 1979-05-18 | 1980-11-29 | Matsushita Electronics Corp | Production of semiconductor device |
| US4234357A (en) * | 1979-07-16 | 1980-11-18 | Trw Inc. | Process for manufacturing emitters by diffusion from polysilicon |
| US4380774A (en) * | 1980-12-19 | 1983-04-19 | The United States Of America As Represented By The Secretary Of The Navy | High-performance bipolar microwave transistor |
| JPS57178374A (en) * | 1981-04-27 | 1982-11-02 | Sumitomo Electric Ind Ltd | Junction type field-efect transistor and its manufacture |
| JPS57178376A (en) * | 1981-04-27 | 1982-11-02 | Sumitomo Electric Ind Ltd | Junction type field-effect transistor |
| US4433470A (en) * | 1981-05-19 | 1984-02-28 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for manufacturing semiconductor device utilizing selective etching and diffusion |
| US4452646A (en) * | 1981-09-28 | 1984-06-05 | Mcdonnell Douglas Corporation | Method of making planar III-V compound device by ion implantation |
| FR2517120A1 (en) * | 1981-11-26 | 1983-05-27 | Michel Salvi | METHOD FOR MANUFACTURING A DIFFUSION SEMICONDUCTOR COMPONENT WITH PRELIMINARY ION IMPLANTATION AND COMPONENT OBTAINED |
| US4495512A (en) * | 1982-06-07 | 1985-01-22 | International Business Machines Corporation | Self-aligned bipolar transistor with inverted polycide base contact |
| FR2549293B1 (en) * | 1983-07-13 | 1986-10-10 | Silicium Semiconducteur Ssc | HIGH FREQUENCY BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF |
| US4593457A (en) * | 1984-12-17 | 1986-06-10 | Motorola, Inc. | Method for making gallium arsenide NPN transistor with self-aligned base enhancement to emitter region and metal contact |
| US4843033A (en) * | 1985-09-27 | 1989-06-27 | Texas Instruments Incorporated | Method for outdiffusion of zinc into III-V substrates using zinc tungsten silicide as dopant source |
| US4912053A (en) * | 1988-02-01 | 1990-03-27 | Harris Corporation | Ion implanted JFET with self-aligned source and drain |
| IT1225623B (en) * | 1988-10-20 | 1990-11-22 | Sgs Thomson Microelectronics | FORMATION OF SELF-ALIGNED CONTACTS WITHOUT THE USE OF A RELATIVE MASK |
-
1984
- 1984-04-18 JP JP59077710A patent/JPS60220975A/en active Granted
- 1984-12-31 EP EP84309167A patent/EP0158752B1/en not_active Expired
- 1984-12-31 DE DE8484309167T patent/DE3481466D1/en not_active Expired - Lifetime
-
1990
- 1990-02-08 US US07/476,140 patent/US5015596A/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5315081A (en) * | 1976-07-27 | 1978-02-10 | Nec Corp | Junction type field effect transistor and its production |
| JPS5844771A (en) * | 1981-09-10 | 1983-03-15 | Mitsubishi Electric Corp | Junction type field effect transistor and manufacture thereof |
| JPS59213172A (en) * | 1983-05-19 | 1984-12-03 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60220975A (en) | 1985-11-05 |
| EP0158752A3 (en) | 1986-10-22 |
| EP0158752B1 (en) | 1990-02-28 |
| DE3481466D1 (en) | 1990-04-05 |
| EP0158752A2 (en) | 1985-10-23 |
| US5015596A (en) | 1991-05-14 |
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