JPH0224019B2 - - Google Patents

Info

Publication number
JPH0224019B2
JPH0224019B2 JP59242568A JP24256884A JPH0224019B2 JP H0224019 B2 JPH0224019 B2 JP H0224019B2 JP 59242568 A JP59242568 A JP 59242568A JP 24256884 A JP24256884 A JP 24256884A JP H0224019 B2 JPH0224019 B2 JP H0224019B2
Authority
JP
Japan
Prior art keywords
layer
metal
layers
organosilane
deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59242568A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60142545A (ja
Inventor
Shin Sachideu Haabansu
Sachideu Kurishunan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS60142545A publication Critical patent/JPS60142545A/ja
Publication of JPH0224019B2 publication Critical patent/JPH0224019B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P14/662
    • H10P14/6336
    • H10P14/683
    • H10P14/6922
    • H10W20/058
    • H10W20/4473
    • H10W70/69

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
JP59242568A 1983-12-27 1984-11-19 多層複合構造体 Granted JPS60142545A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US56556283A 1983-12-27 1983-12-27
US565562 1983-12-27

Publications (2)

Publication Number Publication Date
JPS60142545A JPS60142545A (ja) 1985-07-27
JPH0224019B2 true JPH0224019B2 (ref) 1990-05-28

Family

ID=24259173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59242568A Granted JPS60142545A (ja) 1983-12-27 1984-11-19 多層複合構造体

Country Status (3)

Country Link
EP (1) EP0150403B1 (ref)
JP (1) JPS60142545A (ref)
DE (1) DE3473198D1 (ref)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4519872A (en) * 1984-06-11 1985-05-28 International Business Machines Corporation Use of depolymerizable polymers in the fabrication of lift-off structure for multilevel metal processes
US4764644A (en) * 1985-09-30 1988-08-16 Microelectronics Center Of North Carolina Microelectronics apparatus
US4667404A (en) * 1985-09-30 1987-05-26 Microelectronics Center Of North Carolina Method of interconnecting wiring planes
DE3604917A1 (de) * 1986-02-17 1987-08-27 Messerschmitt Boelkow Blohm Verfahren zur herstellung eines integrierten verbandes in reihe geschalteter duennschicht-solarzellen
US5141817A (en) * 1989-06-13 1992-08-25 International Business Machines Corporation Dielectric structures having embedded gap filling RIE etch stop polymeric materials of high thermal stability
WO1991010261A1 (en) * 1990-01-04 1991-07-11 International Business Machines Corporation Semiconductor interconnect structure utilizing a polyimide insulator
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5550405A (en) * 1994-12-21 1996-08-27 Advanced Micro Devices, Incorporated Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS
JPH1013899A (ja) * 1996-06-21 1998-01-16 Nec Shizuoka Ltd 無線選択呼出受信機
JP3505520B2 (ja) 2001-05-11 2004-03-08 松下電器産業株式会社 層間絶縁膜
US7579232B1 (en) * 2008-07-11 2009-08-25 Sandisk 3D Llc Method of making a nonvolatile memory device including forming a pillar shaped semiconductor device and a shadow mask

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001870A (en) * 1972-08-18 1977-01-04 Hitachi, Ltd. Isolating protective film for semiconductor devices and method for making the same
US3985597A (en) * 1975-05-01 1976-10-12 International Business Machines Corporation Process for forming passivated metal interconnection system with a planar surface
US4367119A (en) * 1980-08-18 1983-01-04 International Business Machines Corporation Planar multi-level metal process with built-in etch stop
JPS57211239A (en) * 1981-06-22 1982-12-25 Nippon Telegr & Teleph Corp <Ntt> Formation of insulating film

Also Published As

Publication number Publication date
EP0150403B1 (en) 1988-08-03
EP0150403A1 (en) 1985-08-07
DE3473198D1 (en) 1988-09-08
JPS60142545A (ja) 1985-07-27

Similar Documents

Publication Publication Date Title
EP0046525B1 (en) Planar multi-level metal-insulator structure comprising a substrate, a conductive interconnection pattern and a superposed conductive structure and a method to form such a structure
JP3418458B2 (ja) 半導体装置の製造方法
US6831005B1 (en) Electron beam process during damascene processing
US4692205A (en) Silicon-containing polyimides as oxygen etch stop and dual dielectric coatings
US7012022B2 (en) Self-patterning of photo-active dielectric materials for interconnect isolation
US4451971A (en) Lift-off wafer processing
JPS6350860B2 (ref)
JPS613411A (ja) リフトオフ処理方法
JP2003504693A (ja) フォーミングガスプラズマを用いたフォトレジスト除去プロセス
US20070134917A1 (en) Partial-via-first dual-damascene process with tri-layer resist approach
CA2433153A1 (en) Method for eliminating reaction between photoresist and organosilicate glass
US4447824A (en) Planar multi-level metal process with built-in etch stop
US6097095A (en) Advanced fabrication method of integrated circuits with borderless vias and low dielectric-constant inter-metal dielectrics
US6489030B1 (en) Low dielectric constant films used as copper diffusion barrier
US5407529A (en) Method for manufacturing semiconductor device
US7022582B2 (en) Microelectronic process and structure
US6333258B1 (en) Method of manufacturing a semiconductor device
JPH0224019B2 (ref)
US6559045B2 (en) Fabrication of integrated circuits with borderless vias
US6524944B1 (en) Low k ILD process by removable ILD
US20030205815A1 (en) Fabrication method of integrated circuits with borderless vias and low dielectric constant inter-metal dielectrics
JP2849286B2 (ja) 半導体装置の製造方法
JPH0653134A (ja) 半導体装置の製造方法
JPH0677208A (ja) 半導体装置の製造方法
US20050158666A1 (en) Lateral etch inhibited multiple etch method for etching material etchable with oxygen containing plasma