JPH02239655A - Mos semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To eliminate the possibility of insufficiency of an operating margin and malfunctions by connecting second conductivity type wells to ground or power source pad via wirings for applying a well potential to the well. CONSTITUTION:P-type wells 2, 2b are provided in an N-type semiconductor substrate 1, and an N<+> type region 3 for forming an n-type MOS and a P<+> type well 4 for applying a well potential are formed in the wells. An n-type MOS 8 for an equalizer and n-type MOS except it are formed in the well 2, but a general n-type MOS is formed in the well 2b, but the n-type MOS for the equalizer is not formed. The region 4 of the well 2b and the region 3 of a source region of the MOS 9 are connected by a ground pad of a ground wiring 6, and the P<+> type region of the well 2 is connected directly to the wiring 6 via a ground wiring 5. Thus, an insufficiency of an operating margin and an erroneous operation of the equalizer are eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS type semiconductor integrated circuit device, and particularly to a MOS type semiconductor integrated circuit device having an equalization circuit.

[Prior Art] FIG. 3 shows a circuit diagram of an equalization circuit. An n-channel MOSFET for the equalization circuit is connected between the wires X and Y.
(hereinafter referred to as nMOs) 8 is connected, and the gate G of this transistor is biased as necessary. Short-circuit between Y. Such an equalization circuit is often used to short-circuit bit line pairs and data paths of a memory LSI to equalize the potential. FIG. 4 is a cross-sectional view of a conventional integrated circuit device having an nMOS equalization circuit. As shown in the figure, a P-well 2 is provided in an N-type semiconductor substrate 1, and in the P-well, N+ diffusion is used to form nMOS 8 for an equalization circuit and other nMOS 9. A layer 3 is also formed with a P+ diffusion layer 4 for providing a well potential. The source region of the nMOS 9 and the diffusion layer 21 are connected to the grounding pad 7 via the connection wiring 5.

[Problems to be Solved by the Invention] In the conventional integrated circuit device described above, the P-well containing the equalization circuit is
The potential changes depending on the operation of Os. The causes of this variation in well potential include power supply fluctuations due to internal circuit currents, and well current due to holes in electron-hole pairs due to ion impact generated during MOS operation. In general, MOSFET is a MOS FET in a substrate (well).
When the well voltage is changed, the threshold voltage changes. The situation is shown in Figure 5. The figure shows the measurement results, with the horizontal axis representing the substrate bias voltage and the vertical axis representing the threshold voltage. Therefore, the equalizing MOS consists of two N+ diffusion layers 3.
Since the one with the lower potential acts as a source, it is not possible to predetermine which region will be the source. Therefore, nMO for equalization circuit
In MOS, the source potential cannot be made to match the well potential as in general nMoS, and fluctuations in the well potential directly affect the source-to-well voltage, changing the threshold voltage of the MOS. Therefore, conventional equalization circuits may lack operating margin or malfunction. [Means for Solving the Problems] The MOS type semiconductor integrated circuit device of the present invention includes a MOS type semiconductor integrated circuit device having a first conductivity type channel used as an equalization circuit.
The device includes a second conductivity type well in which a FET is formed and a second conductivity type well in which an equalization circuit is not formed, and each of the second conductivity type wells has a well potential that applies a well potential to the well. Connected to a ground or power pad by a separate trace. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention. In this embodiment, P wells 2, 2 are provided in the N type semiconductor substrate l.
In these wells, there is an N+ region 3 for forming nMOs and a P+ region 3 for providing a well potential.
Region 4 is formed. In the P-well 2, an nMOS 8 for the equalization circuit and other nMOSs (not shown) are formed, but in the P-well 2b, only general nMOSs are formed. NMOS for the equalization circuit is not formed. P+ region 4 of P well 2b and N+ source region of nMOs9
The region 3 is connected to a grounding pad 7 by a grounding wiring 6, and the P+ region of the P well 2 is directly connected to the grounding wiring 5 by a different grounding wiring 5.

According to this embodiment, the P well 2 and the P well 2b are separated, and the ground wiring for providing a well potential is also separated by the ground pad 7, so that the MOS
P well 2 due to ion impact caused by operation.
Even if the potential of b changes, the P well 2 is hardly affected, and the nMOS 8 for the equalization circuit can operate stably. However, in this embodiment, since the P-well 2 includes nMOSs other than the nMOSs for the equalization circuit, the operation of these nMOSs causes the P-well 2 to
There is a possibility that the potential of However, since the general nMOS formed in the P-well 2 is only a part, even if the P-well 2 fluctuates due to these transistors, the fluctuation is smaller than if all the nMOS were accommodated in the P-well 2. small. Next, another embodiment of the present invention will be described with reference to FIG. The difference between this embodiment and the previous embodiment is that only nMOS 8 for the equalization circuit is formed in the P well 2a, and no other nMOS is formed (in the figure, only one nMOS 8 is formed). is only described, but in reality, it is assumed that multiple equalization circuits are formed). In this embodiment as well, the P+ region 4 provided in each well 2a, 2b is provided with a separate grounding wiring 4i5,
6 directly connected to ground pad 7. According to this embodiment, the potential of the P well 2a is
Since it is no longer affected by MOs, it becomes even more stable. In the above embodiments, the nMOS formed in the P-well has been described, but the present invention is not limited thereto, and can also be applied to the case where the pMOS is formed in the N-well. In that case, each well is connected to a power supply (VCC) pad by a power supply wiring.

[Effects of the Invention] As explained above, the present invention separates a well in which a MOSFET constituting an equalization circuit is formed from a well housing other circuit elements, and also provides wiring for supplying a well potential to each well. Since they are separated, the present invention can prevent the potential of the well containing the equalization circuit from being affected by fluctuations in the potential of other wells, thereby preventing the equalization circuit from lacking operating margin or malfunctioning. It will no longer occur.

[Brief explanation of drawings]

1 and 2 are cross-sectional views showing embodiments of the present invention, FIG. 3 is a circuit diagram of an equalization circuit, and FIG. 4 is a sectional view showing an embodiment of the present invention.
FIG. 5, a sectional view showing a conventional example, is a characteristic curve diagram of a MOSFET. 1... N-type semiconductor substrate, 2, 2a, 2b... P well, 3... N+ region, 4... P+ region, 5
, 6... Ground wiring, 7... Grounding pad, 8.
. . . nMOs for equalization circuits, 9 . . . General nMOSs not for equalization circuits.

Claims (1)

[Claims] In a MOS type semiconductor integrated circuit device comprising a second conductivity type well in which a MOSFET having a first conductivity type channel used as an equalization circuit is formed, and a second conductivity type well in which no equalization circuit is formed,
A MOS type semiconductor integrated circuit device, wherein each of the second conductivity type wells is connected to a grounding pad or a power supply pad by a separate wiring that applies a well potential to the well.