JPH02239631A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a parasitic capacity between a base and an emitter and a parasitic capacity between a base and a collector by depositing a metal electrode to an aperture and by forming a Schottky barrier/diode region with the metal electrode and a nonion implantation region on a semiconductor substrate. CONSTITUTION:An ion injection region 5 is formed by introducing impurity of the opposite conductivity type to a part of an exposed section of a semiconductor substrate 1. An area which is behind a conductive layer 2 and an insulating film 3 and whereto impurity is not introduced becomes a nonionic injection region 6. After an emitter diffusion region 7 and an inner base diffusion region 8 are formed by double-diffusion P-type and N-type impurity inside the conductive layer 2, impurity in the ion injection region 5 is diffused to form an outer base diffusion region 9 which is in contact with the inner base diffusion region 8. Metal is deposited on an aperture 4 to form a metal electrode 10. The electrode 10 and the nonionic injection region 6 on the substrate 1 form a Schottky barrier/diode region 11. Thereby, a fine base, an emitter and a Schottky barrier/ diode can be formed, and a base to emitter parasitic capacity and a base to collector parasitic capacity can be reduced.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method for manufacturing a poly-Si self-line transistor with SBD. A conductive layer containing impurities of one conductivity type and the opposite conductivity type and having an opening that exposes a part of the semiconductor substrate is formed on a semiconductor substrate of one conductivity type in order to form an emitter and an SBD. Then, ions of impurity of opposite conductivity type are implanted obliquely to the vertical direction of the opening. A step of forming an ion implantation region in a part of the exposed portion of the semiconductor substrate. The emitter diffusion region is formed by diffusing impurities of one conductivity type and the opposite conductivity type in the conductive layer. and forming an internal base extension ttk M region surrounding the emitter diffusion region. Diffusion of impurities in the ion implanted region. forming an external base diffusion region in contact with the internal base diffusion region;
depositing a metal electrode in the opening and connecting the Schottky barrier diode region formed by the metal electrode and the non-ion implanted region on the semiconductor substrate to the extrinsic base diffusion region. ．． [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a poly-Si self-line type transistor with a Schatky barrier diode. With the demand for faster computers. The development of transistors that can perform high-speed switching operations is desired. The present invention relates to a method for manufacturing high-speed transistors that meets this demand. [Conventional technology] Conventional high-speed bipolar transistors. Formed using a self-alignment process. So-called SST type transistors and ESPER type transistors are known. SST is Super Se
It is an abbreviation for lf-aligned technology.2For example. It is described in Japanese Patent Application Laid-Open No. 60-81862, and ESPER is. Emitter-bas
e Self-aligned with l'oly
-Silicon Electrodes and Re
It is an abbreviation for sisters.

Figure 12 shows an example of a conventional ESPER transistor. ESPER type transistors use polyester St doped with impurities at a high concentration, and use self-line technology to form fine bases and emitters, thereby reducing the parasitic capacitance between the base and emitter and the parasitic capacitance between base and collector. Reduce. Furthermore, with Selfa Line.
This aims to achieve higher speed by shortening the distance between the external base and emitter and reducing the parasitic base resistance on the base. on the other hand. Another type of bipolar transistor that meets the demand for higher speeds is a transistor with an SBD (Schittky barrier diode). Figure 13 shows an example of a conventional transistor with SBD.
Figure 14 is. This is a diagram showing the equivalent circuit. Transistor with SBD. As a means of speeding up. Insert an SBD (Schottky barrier diode) between the base and collector. With this SBD. The charge stored in the parasitic capacitance between the base and emitter is quickly released.
The aim is to shorten the time required for charging and discharging to achieve higher speeds. [Problems to be solved by the invention] Conventional SST-type transistors and ESPER-type transistors are not sufficient to meet current demands for higher speeds, and there is a problem in that even higher speeds are required. On the other hand, conventional transistors with SBD are not senoriferal line type transistors like SST type transistors and ESPER type transistors, so the base and emitter areas are large, and the distance between the external base and emitter is also large. It is. As a result, the base-collector capacitance and pace-emitter capacitance are large. Since the base resistance is also large, it is difficult to increase the speed beyond the current level. There was a problem.

The present invention solves the above problems. A method for manufacturing semiconductor devices that enables the formation of minute bases, emitters, and Schottky barrier diodes that exceed the limits of current photolithography technology, especially poly-Si self-line type transistors with Schottky barrier diodes. The purpose is to provide a manufacturing method for. [Means for Solving the Problems] In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention, particularly a method for manufacturing a poly-Si self-line transistor with a Schottky barrier diode, is provided.
Contains impurities of one conductivity type and the opposite conductivity type on a semiconductor substrate of one conductivity type. a step of forming a conductive layer having an opening that exposes a portion of the semiconductor substrate; A step of implanting impurity ions of an opposite conductivity type obliquely to the vertical direction of the opening to form an ion implantation region in a part of the exposed portion of the semiconductor substrate. -4t type and opposite conductivity type impurities in the conductive layer are diffused to form an emitter diffusion region. and forming an internal base diffusion region surrounding the emitter diffusion region, diffusing impurities in the ion implantation region to form an external base diffusion region in contact with the internal base diffusion region, and forming a metal electrode in the opening. and connecting the Schottky barrier diode region formed by the metal electrode and the non-ion implanted region on the semiconductor substrate to the extrinsic base diffusion region.

Figures 1(a) to (C) are. FIG. 2 is a diagram explaining the principle of the present invention.

In FIGS. 1(a) to (c), l is a semiconductor substrate and 2 is a conductive layer. 3 is an insulating film, and 4 is an opening. 5 is an ion-implanted region, and 6 is a non-ion-implanted region. 7 is an Emmink diffusion region, 8 is an internal base diffusion region, 9 is an external base diffusion region, 10 is a metal electrode, and 11 is a Schottky Harrier diode region. [Function] A transistor formation method using self-line technology using a voluminous Sj, such as a conventional SST type transistor or ESPER type transistor, reduces parasitic capacitance by forming a base and emitter minutely, and furthermore, S
It is possible to realize an even faster transistor that has both the advantages of higher speeds of ST type transistors and ESPER type transistors and the advantages of higher speeds of transistors with SBD. A method for manufacturing a semiconductor device according to the present invention. especially. The manufacturing method of the S1 self-line type transistor with Schottky barrier diode is as follows. This was done in order to make it possible to manufacture the high-speed transistor described above.

below. The principle of the present invention will be explained using FIGS. 1(a) to 1(c).

First, as shown in Figure 1(a). A conductive layer 2 made of poly-Si or the like is formed on a semiconductor substrate 1 of one conductivity type.
Insulating films 3 made of the following materials are sequentially laminated.

Next, after ion implantation of P-type impurities and N-type impurities having different diffusion coefficients into the conductive layer 2. The conductive layer 2 and the insulating film 3 are partially removed to form an opening 4. Part of the semiconductor substrate 1 is exposed.

Then, as shown in FIG. 1(b), an ion implantation region 5 is formed by introducing impurities of the opposite conductivity type into a part of the exposed portion of the semiconductor substrate 1 by an inclined angle ion implantation method. The portions where impurities were not introduced because they were in the shadow of the conductive layer 2 and the insulating film 3. This becomes a non-ion implanted region 6.

moreover. As shown in Figure 1(c). After doubly diffusing the P-type impurity and N-type impurity in the conductor tJii2 to form the emitter diffusion region 7 and the internal base diffusion region 8,
The impurity in the ion implantation region 5 is diffused to form an external base diffusion region 9 in contact with the internal base diffusion region 8.
A metal electrode 10 is formed by depositing metal in the opening 4, and the metal electrode 10 and the non-ion implanted region 6 on the semiconductor substrate 1 are connected to each other.
A Schottky barrier diode region 11 is formed. By doing as described above, the base 2 emifter and Schottky barrier diode are formed in the self-line, so there is no need to allow for a margin for alignment. It is possible to form minute base, emitter, and Schottky barrier diodes that exceed the limits of current photolithography technology. As a result, the parasitic capacitance between base and emitter and the parasitic capacitance between base and collector can be reduced.
Also, the area of the transistor including the Shigotkey barrier diode can be reduced. It is also possible to reduce the parasitic capacitance between the collector substrates. This makes it possible to speed up the transistor. moreover. By inserting a Schottky barrier diode between the base and collector, the charge accumulated in the base can be quickly discharged, reducing the time required for charging and discharging, making the transistor faster. .

〔Example〕

[Embodiment 1] Figures 2 to 8 are diagrams showing a first embodiment of the present invention. Below, Figures 2 to 8 are used. A first embodiment of the present invention will be explained. (Process 1. See Figure 2) P type S! After forming an N0 type buried diffusion region 102 by diffusing N type impurities such as As or sb on the substrate 101,
Grow an N-type epitaxial layer 103 that will become the collector region. Next, field oxide regions 104 are formed using the patterned SixN4 film as a mask. This field oxidation region 104 is . It can also be formed by forming a shallow trench in the N-type epitaxial layer 103 by anisotropic etching, and burying an insulating film inside the trench using a planarization technique.

Furthermore, an isolation region 105 is formed. For isolation, PN junction isolation may be used,
Dielectric isolation using a U-groove may also be used. In this example, after forming a U-groove by anisotropic etching of Si, the inner wall of the U-groove is thermally oxidized, and then U-groove isolation is used in which the inside of the U-groove is filled with bobbed Si.

and. After diffusing P as an N-type impurity into the collector extraction part. Anneal it. N-type buried diffusion region 1
An N-type diffusion region 106 reaching 0.02 is formed. (Process 2. See Figure 3) After growing poly Sll07 on the entire surface to a thickness of about 3,000 wafers, the poly Si is insulated in areas other than the area where the base is drawn out and becomes the electric scraper. As for this method. ■CVD on the entire surface
After growing the s+sN* film, the SiJ4 film is left in the base extraction electrode area by patterning, and the other parts are replaced with an oxide film by thermal oxidation.
There is a method to remove it by etching. Next, the polySL layer 10 on the right side of the base extraction electrode area
7, B゛ is accelerated as a P-type impurity with energy 2Q
KeV, dose 1. O x 10 l4cm
−” to accelerate the N-type impurity As with an energy of 60 K.
eV, dose 1. O X l O “cm-”
The ions are implanted in each case. And, C V DSi
Grow Om film 10B to a thickness of approximately 3000 nm. (Step 3, see Figure 4) Using the resist pattern as a mask, the C V ostoz film 108 and the poly-Si layer 107 are anisotropically etched,
An opening 109 reaching the N-type epitaxial layer 103 is formed. Next, a cvosto film 110 was grown on the entire surface to a thickness of approximately 2000 nm, and then anisotropic etching was performed. It remains only on the side surface of the opening 109.

(Step 4, see FIG. 5) A portion of the N-type epitaxial layer 103 exposed within the opening 109 is injected using the inclined angle ion implantation method. B0 is accelerated with an energy of 30 KeV and a dose of l. OXIO
Perform ion implantation using ISc Otori-3. The tilt angle θ of ion implantation is. Set between approximately 7° and approximately 70°. As a result, the N-type epitaxial layer 103 exposed in the opening 109 has a . An ion-implanted region where B is ion-implanted and a non-ion-implanted region are created. The tilt angle ion implantation in this process is. C V Dstoz film 1 shown in FIG.
You can also do this before forming 10. Also. Before performing tilt angle ion implantation. A thin oxide film is formed on the surface of the N-type epitaxial layer 103. There is no problem in adopting general methods such as ion implantation through this as necessary. Furthermore, this tilt angle ion implantation... This is because the ion implantation is performed only on a part of the N-type epitaxial layer 103 exposed in the opening 109, and the ion implantation region is used as a base contact, and the non-ion implantation region is used as an SBD. Also, to prevent the impurities in the ion-implanted region from spreading into the non-ion-implanted region during the subsequent heat treatment and to prevent the SBD formation region from disappearing. Poly-Si layer 107 and C V D
Opening 109 defined by SiOzll#l08
Due to variations in height. The slope angle θ of the ion implantation must be chosen so that the ion implantation region is not narrow enough to interfere with the base contact.

(Step 5, see Figure 6) Heat treatment. B as a P-type impurity and ^S as an N-type impurity in the polysilicon 07 are doubly diffused into the N-type collector region 103. What are B and As? Because of the difference in diffusion coefficient. First, B is the N1 type collector region 103
to form a P-type internal base region 111; ^3 is diffused to form an N-type emitter region 112.

on the other hand. High concentration of B introduced into the ion implantation region in Figure 5
Also diffuses into the N-type collector region 103 to form a P′-type external base region 113. A plan view of this state is shown in FIG.

(Step 6, see Figure 8) Open a window in the oxide film in a predetermined area. After depositing N on the entire surface, patterning is performed. An N base electrode 114/V emitter electrode 115 and an N collector electrode (not shown) are formed.

At this time, the 5N base electrode 114 and the N1 type collector region 1
03 to form SBD116.

[Embodiment 2] Figures 9 to 11 are diagrams showing a second embodiment of the present invention. In this example, in step 2 of Example 1 (FIG. 3), the entire 8-bore stli 1 0 7. B as a P-type impurity and As as an N-type impurity were implanted.Other than that, steps 1 to 4 were the same as in Example 1. The explanation will be omitted. (Step 5, see FIG. 9) A heat treatment is performed to double diffuse B as a P-type impurity and As as an N-type impurity in the poly-Si layer 207 into the N1-type collector region 203. Since B and As have different diffusion coefficients, B first diffuses into the N-type collector region 203 to form the P-type internal base region 211, and then As diffuses to form the N-type emitter region 212. Form. In the case of this embodiment, B as a P-type impurity and As as an N-type impurity are introduced into the entire poly-Si layer 207. A P-type internal base region 211 and an N-type emitter region 212 are formed around the N1-type collector region 203 directly below the opening 209 .

On the other hand, the highly concentrated B introduced into the ion implantation region also diffuses into the N1 type collector region 203 to form a P' type external base region 213. A plan view of this state is shown in FIG.

(Step 6, see Figure 11) After opening the oxide film in a predetermined area and depositing N on the entire surface. Perform buttering. An N base electrode 214, an N emitter electrode 215, and an N collector electrode (not shown) are formed. At this time, the N base electrode 214 and the N1 type collector region 2
03 to form SBD2 1 6.

Example 1 and Example 2 above are . Together, the so-called ES
This is an example in which the present invention is applied to a PER type transistor.
The present invention can also be applied to SST type transistors. [Effects of the Invention] The method of manufacturing a semiconductor device according to the present invention, particularly the method of manufacturing a poly-Si self-line transistor with a Schottky barrier diode, has the following advantages. It has the following effects. ■Base, emitter and SBD in Selfa line
Because it forms a fine base that exceeds the limits of current photolithography technology, there is no need to allow for a margin for alignment. Eminter and SBD can be formed.

■This result. Parasitic capacitance between base and emitter and parasitic capacitance between base and collector can be reduced.
In addition, the area of the transistor including the SBD can be reduced. Parasitic capacitance between collector substrates can also be reduced effortlessly.

This makes it possible to speed up transistors. ■Furthermore. By inserting an SBD between the base and collector, the charge accumulated in the base can be quickly discharged. The time required for charging and discharging is shortened2
Transistors can be made faster.

[Brief explanation of drawings]

Figure 1 is a diagram explaining the principle of the present invention. Figures 2 to 8 are diagrams showing each step of the first embodiment of the present invention. Figures 9 to 11 are the second embodiment of the present invention. Diagram showing each process. Figure 12 is a diagram showing a conventional ESPER type transistor. Figure 13 shows a conventional transistor with SBD.
It is a diagram showing an equivalent circuit of a transistor with group+iSBD. In FIGS. 1(a) to (c), 12 semiconductor substrate 2: conductive layer 3: insulating film 4; opening 5: ion implantation region 6: non-ion implantation region 7: emitter diffusion region 8: internal base diffusion region 9 ;External base diffusion region 10: metal electrode

Claims (1)

[Scope of Claims] A conductive layer (1) on a semiconductor substrate (1) of one conductivity type, containing impurities of one conductivity type and an opposite conductivity type, and having an opening (4) exposing a part of the semiconductor substrate (1). 2), and performing ion implantation of an impurity of an opposite conductivity type obliquely with respect to the vertical direction of the opening (4) to form an ion implantation region (5) in a part of the exposed portion of the semiconductor substrate (1). ) and diffusing impurities of one conductivity type and the opposite conductivity type in the conductive layer (2) to form an emitter diffusion region (7) and an internal base diffusion region (8) surrounding the emitter diffusion region (7). forming an external base diffusion region (9) in contact with the internal base diffusion region (8) by diffusing the impurity in the ion implantation region (5);
), and depositing a metal electrode (10) in the opening (4), which is formed by this metal electrode (10) and a non-ion implanted region (6) on the semiconductor substrate (1). A method of manufacturing a semiconductor device, comprising the step of connecting a Schottky barrier diode region (11) and an external base diffusion region (9).