JPH022391B2 - - Google Patents
Info
- Publication number
- JPH022391B2 JPH022391B2 JP56135051A JP13505181A JPH022391B2 JP H022391 B2 JPH022391 B2 JP H022391B2 JP 56135051 A JP56135051 A JP 56135051A JP 13505181 A JP13505181 A JP 13505181A JP H022391 B2 JPH022391 B2 JP H022391B2
- Authority
- JP
- Japan
- Prior art keywords
- mos
- switch circuits
- switch
- circuit
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004804 winding Methods 0.000 claims description 62
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 230000005284 excitation Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
Description
【発明の詳細な説明】
本発明は同一位相でスイツチングする複数のス
イツチング素子を直列に接続して耐圧を増すよう
にしたスイツチング電力変換回路の改良に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a switching power conversion circuit in which a plurality of switching elements that switch in the same phase are connected in series to increase withstand voltage.
従来のこの種のブリツジ形スイツチング電力増
幅回路を第１図に示す。図中、１は励振入力端
子、２は（＋）側の電源端子、３は（−）側の電
源端子、４は出力端子、Ｑ１１，Ｑ１２，Ｑ２
１，Ｑ２２，Ｑ３１，Ｑ３２，Ｑ４１，Ｑ４２は
ＮチヤネルパワーMOS−FET（スイツチング素
子）、Ｒ１〜Ｒ１６は抵抗、CDはコンデンサ、Ｔ
１は入力トランス、Ｔ２は出力トランスで、上記
MOS−FETQ１１とＱ１２，Ｑ２１とＱ２２，
Ｑ３１とＱ３２、及びＱ４１とＱ４２はそれぞれ
各々のソースとドレインとの間で直列に接続し、
第１、第２、第３及び第４のスイツチ回路を構成
している。励振入力端子１は入力トランスＴ１の
１次巻線に接続され、MOS−FET Ｑ１１〜Ｑ
４２のゲートソース間には入力トランスＴ１の２
次巻線がそれぞれ接続され、各スイツチ回路を構
成する２つのMOS−FETにはそれぞれ同相の電
圧が加えられ同一位相でスイツチングする如くな
つており、第１のスイツチ回路と第４のスイツチ
回路、及び第２のスイツチ回路と第３のスイツチ
回路は同じ位相でオン・オフし、第１（または第
４）のスイツチ回路と第２（または第３）のスイ
ツチ回路は逆位相でオン・オフする如くなつてい
る。電源端子２には第１のスイツチ回路のMOS
−FET Ｑ１１のドレインと第３のスイツチ回路
のMOS−FET Ｑ３１のドレインとが並列に接
続され、電源端子３には第２のスイツチ回路の
MOS−FET Ｑ２２のソースと第４のスイツチ
回路のMOS−FET Ｑ４２のソースとが並列に
接続されている。第１のスイツチ回路と第２のス
イツチ回路とはMOS−FET Ｑ１２のソースと
MOS−FET Ｑ２１のドレインとで直列に接続
し、また第３のスイツチ回路と第４のスイツチ回
路とはMOS−FET Ｑ３２のソースとMOS−
FET Ｑ４１のドレインとで直列に接続し、該２
つの接続点の間には出力トランスＴ２の１次巻線
が接続し、出力トランスＴ２の２次巻線は出力端
子４に接続している。コンデンサCDは電源イン
ピーダンスを小さくするためのもので、電源端子
２と３との間に接続されている。抵抗Ｒ１〜Ｒ１
６は容量性のゲートを漏れインダクタンスを含む
入力トランスＴ１により駆動する場合の駆動波形
を改善するためのもので、MOS−FET Ｑ１１
〜Ｑ４２にそれぞれ対応する入力トランスＴ１の
２次巻線に並列に抵抗Ｒ１〜Ｒ８が、また直列に
抵抗Ｒ９〜Ｒ１６がそれぞれ挿入されている。 A conventional bridge-type switching power amplifier circuit of this type is shown in FIG. In the figure, 1 is the excitation input terminal, 2 is the (+) side power supply terminal, 3 is the (-) side power supply terminal, 4 is the output terminal, Q11, Q12, Q2
1, Q22, Q31, Q32, Q41, Q42 are N-channel power MOS-FETs (switching elements), R1 to R16 are resistors, C D is a capacitor, T
1 is the input transformer, T2 is the output transformer, and the above
MOS-FETQ11 and Q12, Q21 and Q22,
Q31 and Q32 and Q41 and Q42 are connected in series between their respective sources and drains,
It constitutes first, second, third and fourth switch circuits. Excitation input terminal 1 is connected to the primary winding of input transformer T1, and MOS-FET Q11 to Q
2 of input transformer T1 between the gate and source of 42
The next windings are connected to each other, and voltages of the same phase are applied to the two MOS-FETs constituting each switch circuit so that they switch in the same phase, and the first switch circuit, the fourth switch circuit, The second switch circuit and the third switch circuit are turned on and off in the same phase, and the first (or fourth) switch circuit and the second (or third) switch circuit are turned on and off in opposite phases. It's becoming like that. The power supply terminal 2 is connected to the MOS of the first switch circuit.
The drain of -FET Q11 and the drain of MOS-FET Q31 of the third switch circuit are connected in parallel, and power supply terminal 3 is connected to the drain of MOS-FET Q31 of the third switch circuit.
The source of MOS-FET Q22 and the source of MOS-FET Q42 of the fourth switch circuit are connected in parallel. The first switch circuit and the second switch circuit are the source of MOS-FET Q12.
The third switch circuit and the fourth switch circuit are connected in series with the drain of MOS-FET Q21, and the source of MOS-FET Q32 and the MOS-
Connect in series with the drain of FET Q41, and
The primary winding of the output transformer T2 is connected between the two connection points, and the secondary winding of the output transformer T2 is connected to the output terminal 4. Capacitor C D is used to reduce power supply impedance and is connected between power supply terminals 2 and 3. Resistance R1~R1
6 is for improving the drive waveform when the capacitive gate is driven by the input transformer T1 including leakage inductance, and MOS-FET Q11
Resistors R1 to R8 are inserted in parallel to the secondary windings of input transformer T1 corresponding to Q42, respectively, and resistors R9 to R16 are inserted in series, respectively.
上記回路に入力として高周波の矩形波または正
弦波の信号を励振入力端子１より与えると、第１
及び第４のスイツチ回路と第２及び第３のスイツ
チ回路とが交互にオン・オフ動作を繰り返し、電
源端子２−３間の電源電圧を振幅とする矩形波の
電圧波形が出力トランスＴ２の１次巻線に発生
し、２次巻線より出力端子４に電力が出力され
る。 When a high frequency rectangular wave or sine wave signal is input to the above circuit from the excitation input terminal 1, the first
The fourth switch circuit and the second and third switch circuits alternately repeat on/off operations, and a rectangular voltage waveform whose amplitude is the power supply voltage between the power supply terminals 2 and 3 is output from the output transformer T2. Power is generated in the secondary winding, and power is output from the secondary winding to the output terminal 4.
しかしながら上記回路ではオフ状態のスイツチ
回路における２つのMOS−FETへの電圧配分が
該MOS−FETのスイツチングのタイミング及び
ドレイン−ソース間の静電容量によつて変わるた
め、一方のMOS−FETの電圧負担が大きくな
り、回路の耐圧が電圧の多くかかる方によつて制
限され、直列数倍より小さくなるという欠点があ
つた。 However, in the above circuit, the voltage distribution to the two MOS-FETs in the off-state switch circuit changes depending on the switching timing and drain-source capacitance of the MOS-FETs, so the voltage of one MOS-FET changes. This has the disadvantage that the burden increases, and the withstand voltage of the circuit is limited by the side to which more voltage is applied, making it smaller than the number of connections in series.
本発明は上記従来の欠点を除去するためになさ
れたもので、その要旨とするところは、４組のス
イツチ回路を有し、第１と第２のスイツチ回路
を、また第３と第４のスイツチ回路を直列接続
し、第１と第３のスイツチ回路を（＋）側電源端
子に、第２と第４のスイツチ回路を（−）側の電
源端子に接続してブリツジ回路を構成し、該スイ
ツチ回路同士の他の接続点の間に出力トランスの
１次巻線を接続し、該出力トランスの２次巻線よ
り出力を取り出すようにしたスイツチング電力変
換回路において、前記の各スイツチ回路が入力信
号に対して同一の位相でスイツチングするｎ個の
スイツチング素子を直列に接続して構成され互に
隣合つたスイツチ回路に対して入力信号が互に逆
位相をなして与えられることと、前記出力トラン
スに２（ｎ−１）個の補助巻線を設け、第１と第
３のスイツチ回路内部のスイツチング素子同士の
接続点の（＋）側電源端子からのそれぞれ等しい
順位の接続点の間に、また第２と第４のスイツチ
回路内部のスイツチング素子同士の接続点の
（−）側の電源端子からのそれぞれ等しい順位の
接続点の間に上記出力トランスに設けた補助巻線
を接続し、その巻数比が一次巻線を１に対し、各
スイツチ回路内に含まれるスイツチング素子の数
ｎと電源より前記補助巻線との接続点までに含ま
れるスイツチング素子の数ｍとの比ｍ／ｎで表わ
される値としたことにある。そしてその目的とす
るところはオフ時の各スイツチ回路内のスイツチ
ング素子にかかる電圧配分を強制的に均等化し、
スイツチ回路内のスイツチング素子１個当りの耐
圧の直列数倍の耐圧が正しく得られるスイツチン
グ電力変換回路を提供することにある。以下、図
面について詳細に説明する。 The present invention has been made to eliminate the above-mentioned conventional drawbacks, and its gist is that it has four sets of switch circuits, the first and second switch circuits, and the third and fourth switch circuits. The switch circuits are connected in series, the first and third switch circuits are connected to the (+) side power terminal, and the second and fourth switch circuits are connected to the (-) side power terminal to form a bridge circuit, In a switching power conversion circuit in which the primary winding of an output transformer is connected between the other connection points of the switch circuits, and the output is taken out from the secondary winding of the output transformer, each of the above-mentioned switch circuits The input signal is provided in opposite phases to mutually adjacent switch circuits, which are constructed by connecting n switching elements in series that switch in the same phase with respect to the input signal; The output transformer is provided with 2(n-1) auxiliary windings, and between the connection points of the same order from the (+) side power supply terminal of the connection points between the switching elements inside the first and third switch circuits. In addition, the auxiliary winding provided in the output transformer is connected between the connection points of the same order from the (-) side power supply terminal of the connection points between the switching elements inside the second and fourth switch circuits. , whose turns ratio is 1 for the primary winding, and the ratio m/ The reason is that the value is expressed as n. The purpose of this is to forcibly equalize the voltage distribution applied to the switching elements in each switch circuit when the switch is off.
It is an object of the present invention to provide a switching power conversion circuit which can correctly obtain a withstand voltage that is several times the withstand voltage in series as the withstand voltage per switching element in a switch circuit. The drawings will be described in detail below.
第２図は本発明の第１の実施例を示すスイツチ
ング電力増幅回路の回路図であつて、第１図と同
一構成部分は同一符号をもつて表わす。すなわち
１は励振入力端子、２及び３は（＋）側及び
（−）側の電源端子、４は出力端子、Ｑ１１，Ｑ
１２，Ｑ２１，Ｑ２２，Ｑ３１，Ｑ３２，Ｑ４
１，Ｑ４２はＮチヤネルパワーMOS−FET（ス
イツチング素子）、Ｒ１〜Ｒ１６は抵抗、CDはコ
ンデンサ、Ｔ１は入力トランス、Ｔ３は出力トラ
ンスで、同一位相でスイツチングするMOS−
FETQ１１とＱ１２，Ｑ２１とＱ２２，Ｑ３１と
Ｑ３２，Ｑ４１とＱ４２はそれぞれ第１、第２、
第３及び第４のスイツチ回路を構成している。出
力トランスＴ３は１次巻線Ｗ１、２次巻線Ｗ２及
び補助巻線Ｗ３，Ｗ４の４つの巻線を有し、補助
巻線Ｗ３，Ｗ４は１次巻線Ｗ１と同相の電圧を発
生する向きに巻かれており、１次巻線Ｗ１の巻数
と補助巻線Ｗ３の巻数と補助巻線Ｗ４の巻数の比
は２：１：１となつている。１次巻線Ｗ１は第１
図の回路と同様に第１と第２のスイツチ回路の接
続点と第３と第４のスイツチ回路の接続点との間
に接続されており、補助巻線Ｗ３は第２のスイツ
チ回路のMOS−FET Ｑ２１とＱ２２の接続点
と第４のスイツチ回路のMOS−FET Ｑ４１と
Ｑ４２の接続点との間に、また補助巻線Ｗ４は第
１のスイツチ回路のMOS−FET Ｑ１１とＱ１
２の接続点と第３のスイツチ回路のMOS−FET
Ｑ３１とＱ３２の接続点との間にそれぞれ接続さ
れている。また、２次巻線Ｗ２は出力端子４に接
続されている。その他の構成については第１図の
回路と同様である。 FIG. 2 is a circuit diagram of a switching power amplifier circuit showing a first embodiment of the present invention, and the same components as in FIG. 1 are denoted by the same symbols. In other words, 1 is the excitation input terminal, 2 and 3 are the (+) side and (-) side power supply terminals, 4 is the output terminal, Q11, Q
12, Q21, Q22, Q31, Q32, Q4
1. Q42 is an N-channel power MOS-FET (switching element), R1 to R16 are resistors, C D is a capacitor, T1 is an input transformer, and T3 is an output transformer, which are MOS-FETs that switch in the same phase.
FETQ11 and Q12, Q21 and Q22, Q31 and Q32, Q41 and Q42 are the first, second,
This constitutes third and fourth switch circuits. The output transformer T3 has four windings: a primary winding W1, a secondary winding W2, and auxiliary windings W3 and W4, and the auxiliary windings W3 and W4 generate a voltage that is in phase with the primary winding W1. The ratio of the number of turns of the primary winding W1, the number of turns of the auxiliary winding W3, and the number of turns of the auxiliary winding W4 is 2:1:1. The primary winding W1 is the first
Similar to the circuit shown in the figure, it is connected between the connection point of the first and second switch circuits and the connection point of the third and fourth switch circuits, and the auxiliary winding W3 is connected to the MOS of the second switch circuit. - The auxiliary winding W4 is connected between the connection point of FETs Q21 and Q22 and the connection point of MOS-FETs Q41 and Q42 of the fourth switch circuit, and the auxiliary winding W4 is connected to the connection point of MOS-FETs Q11 and Q1 of the first switch circuit.
2nd connection point and 3rd switch circuit MOS-FET
They are respectively connected between the connection points of Q31 and Q32. Further, the secondary winding W2 is connected to the output terminal 4. The rest of the configuration is the same as the circuit shown in FIG.
次に動作について述べる。なお、ここでMOS
−FETのオン抵抗は小さく、出力トランスＴ３
の巻線間の結合度は大きいものとする。上記回路
に入力として高周波の矩形波または正弦波の信号
を励振入力端子１より与えると、上記第１図の回
路と同様に第１及び第４のスイツチ回路と第２及
び第３のスイツチ回路が交互にオン・オフ動作を
繰り返し、電源端子２−３間の電源電圧を振幅
（peak to peakでは電源電圧の２倍）とする矩形
波の電圧波形が出力トランスＴ３の１次巻線Ｗ１
に発生し、２次巻線Ｗ２より出力端子４に電力が
出力される。 Next, we will discuss the operation. In addition, here MOS
-FET on-resistance is small, output transformer T3
It is assumed that the degree of coupling between the windings is large. When a high frequency rectangular wave or sine wave signal is inputted to the above circuit from the excitation input terminal 1, the first and fourth switch circuits and the second and third switch circuits are activated as in the circuit shown in FIG. The voltage waveform of the rectangular wave that alternately repeats on and off operations and whose amplitude is the power supply voltage between power supply terminals 2 and 3 (twice the power supply voltage from peak to peak) is the primary winding W1 of the output transformer T3.
occurs, and power is output from the secondary winding W2 to the output terminal 4.
一方、補助巻線Ｗ３，Ｗ４には１次巻線Ｗ１に
発生した電圧波形と周期、位相が同一で、振幅が
１／２、すなわち電源電圧の1/2（peak to peakで
は電源電圧と同一）の矩形波の電圧が誘起され
る。 On the other hand, the auxiliary windings W3 and W4 have the same cycle and phase as the voltage waveform generated in the primary winding W1, and the amplitude is 1/2, that is, 1/2 of the power supply voltage (peak to peak is the same as the power supply voltage). ) is induced.
第１及び第４のスイツチ回路がオンで、第２及
び第３のスイツチ回路がオフの状態において、
MOS−FET Ｑ２１とＱ２２の接続点は補助巻
線Ｗ３に誘起された電圧によつてMOS−FET
Ｑ４１とＱ４２の接続点より電源電圧の1/2だけ
強制的に高い電位となる。一方、MOS−FET
Ｑ４１とＱ４２の接続点はMOS−FET Ｑ４１
とＱ４２がオンのため電源端子３の電位に等し
い。従つてMOS−FET Ｑ２１とＱ２２はそれ
ぞれ電源電圧の1/2ずつを負担する。同様にMOS
−FET Ｑ３１とＱ３２の接続点は補助巻線Ｗ４
に誘起された電圧によつてMOS−FET Ｑ１１
とＱ１２の接続点より電源電圧の1/2だけ低い電
位となるが、MOS−FET Ｑ１１とＱ１２の接
続点の電位は電源端子２の電位に等しく、MOS
−FET Ｑ３１とＱ３２はそれぞれ電源電圧の1/
２ずつを負担する。 When the first and fourth switch circuits are on and the second and third switch circuits are off,
The connection point between MOS-FET Q21 and Q22 is connected to the MOS-FET by the voltage induced in the auxiliary winding W3.
The potential is forcibly higher than the connection point between Q41 and Q42 by 1/2 of the power supply voltage. On the other hand, MOS-FET
The connection point between Q41 and Q42 is MOS-FET Q41
Since Q42 is on, the potential is equal to the potential of power supply terminal 3. Therefore, MOS-FETs Q21 and Q22 each bear 1/2 of the power supply voltage. Similarly, MOS
-The connection point between FET Q31 and Q32 is auxiliary winding W4
MOS-FET Q11 due to the voltage induced in
The potential is 1/2 of the power supply voltage lower than the connection point between Q11 and Q12, but the potential at the connection point between MOS-FET Q11 and Q12 is equal to the potential of power supply terminal 2, and the MOS
-FET Q31 and Q32 are each 1/1/2 of the power supply voltage.
2 each.
また第２及び第３のスイツチ回路がオンで、第
１及び第４のスイツチ回路がオフの状態において
は、上記同様にMOS−FET Ｑ１１とＱ１２の
接続点及びＱ４１とＱ４２の接続点の電位は電源
電圧の1/2の電位となり、MOS−FET Ｑ１１と
Ｑ１２及びＱ４１とＱ４２はそれぞれ電源電圧の
１／２の電圧を負担する。 Furthermore, when the second and third switch circuits are on and the first and fourth switch circuits are off, the potential at the connection point between MOS-FETs Q11 and Q12 and the connection point between Q41 and Q42 is as same as above. The potential is 1/2 of the power supply voltage, and MOS-FETs Q11 and Q12 and Q41 and Q42 each bear a voltage that is 1/2 of the power supply voltage.
このように上記第１の実施例ではオフ時のスイ
ツチ回路内の２つのMOS−FETの接続点を補助
巻線Ｗ３，Ｗ４により強制的に電源電圧の1/2の
電位となるようになしたため、MOS−FETの静
電容量やスイツチングのタイミング等に拘らず、
オフ時のスイツチ回路内のMOS−FETへの電圧
配分を電源電圧の1/2にでき、常に耐圧をMOS−
FET1個の２倍にすることができる。 In this way, in the first embodiment, the connection point of the two MOS-FETs in the switch circuit when off is forced to have a potential of 1/2 of the power supply voltage by the auxiliary windings W3 and W4. , regardless of the capacitance of the MOS-FET or the timing of switching,
The voltage distribution to the MOS-FET in the switch circuit when off can be reduced to 1/2 of the power supply voltage, and the withstand voltage can always be maintained at MOS-FET.
It can be doubled as one FET.
また、出力トランスＴ３のそれぞれの巻線間は
直流的に絶縁されているため、AM送信機の被変
調電力増幅回路として用いた場合のように供給電
源電圧が変調信号に応じて瞬時に変化しても、こ
の出力トランスの補助巻線によるMOS−FETの
電圧均等化は有効に作用する。 In addition, since each winding of the output transformer T3 is DC-insulated, the supply voltage does not change instantaneously in response to the modulation signal, as in the case of using it as a modulated power amplifier circuit of an AM transmitter. However, the voltage equalization of the MOS-FET by the auxiliary winding of the output transformer works effectively.
第３図は本発明の第２の実施例のスイツチング
電力増幅回路を示すもので、この実施例は各スイ
ツチ回路内に３個のＮチヤネルパワーMOS−
FETを直列接続した場合の回路を示す。図中、
Ｑ１３，Ｑ２３，Ｑ３３，Ｑ４３はＮチヤネルパ
ワーMOS−FETで、MOS−FET Ｑ１３はＱ１
１及びＱ１２と直列に接続し、かつ同一位相でス
イツチングしMOS−FET Ｑ１１，Ｑ１２とと
もに第１のスイツチ回路を構成している。同様に
MOS−FET Ｑ２３，Ｑ３３，Ｑ４３はそれぞ
れＱ２１，Ｑ２２，Ｑ３１，Ｑ３２，Ｑ４１，Ｑ
４２と直列に接続し、かつ同一位相でスイツチン
グして第２、第３、第４のスイツチ回路を構成し
ている。出力トランスＴ４は１次巻線Ｗ１、２次
巻線Ｗ２及び補助巻線Ｗ３，Ｗ４，Ｗ５，Ｗ６の
６つの巻線を有し、補助巻線Ｗ３，Ｗ４，Ｗ５，
Ｗ６は１次巻線Ｗ１と同相の電圧を発生する向き
に巻かれており、１次巻線Ｗ１と補助巻線Ｗ３，
Ｗ４，Ｗ５，Ｗ６との巻数比はＷ４：Ｗ５：Ｗ
３：Ｗ６：Ｗ１＝１：１：２：２：３となつてい
る。また補助巻線Ｗ５はMOS−FET Ｑ２２と
Ｑ２３の接続点とＱ４２とＱ４３の接続点との間
に接続し、補助巻線Ｗ６はMOS−FETQ１２と
Ｑ１３の接続点とＱ３２とＱ３３の接続点との間
に接続している。このような回路構成となつてい
るため、オフ時の各スイツチ回路の各MOS−
FETには電源電圧の1/3の電圧が均等に配分さ
れ、耐圧をMOS−FET1個の３倍とすることが
できる。その他の構成、及び効果については第１
の実施例と同様である。 FIG. 3 shows a switching power amplifier circuit according to a second embodiment of the present invention, and this embodiment has three N-channel power MOS-
This shows a circuit when FETs are connected in series. In the figure,
Q13, Q23, Q33, Q43 are N-channel power MOS-FETs, and MOS-FET Q13 is Q1
It is connected in series with MOS-FETs Q11 and Q12, and switches in the same phase, thereby forming a first switch circuit together with MOS-FETs Q11 and Q12. similarly
MOS-FET Q23, Q33, Q43 are respectively Q21, Q22, Q31, Q32, Q41, Q
42 in series and switch in the same phase to form second, third, and fourth switch circuits. The output transformer T4 has six windings: a primary winding W1, a secondary winding W2, and auxiliary windings W3, W4, W5, W6.
W6 is wound in a direction that generates a voltage in phase with the primary winding W1, and the primary winding W1 and the auxiliary winding W3,
The turns ratio of W4, W5, and W6 is W4:W5:W
3:W6:W1=1:1:2:2:3. In addition, the auxiliary winding W5 is connected between the connection point of MOS-FETs Q22 and Q23 and the connection point of Q42 and Q43, and the auxiliary winding W6 is connected between the connection point of MOS-FETs Q12 and Q13 and the connection point of Q32 and Q33. connected between. Because of this circuit configuration, each MOS-
1/3 of the power supply voltage is evenly distributed to the FETs, and the withstand voltage can be three times that of a single MOS-FET. For other configurations and effects, see Part 1.
This is similar to the embodiment.
なお、補助巻線は出力側に電力を伝達するため
の巻線ではなく、１次巻線、２次巻線に比較して
細い線材を使用しても良く、また第３図の回路に
示す如く低抵抗ｒを直列に挿入しても良い。また
スイツチング波形の少しばかりの非対称性により
生じる直流分を吸収するため、第３図に示すよう
に１次巻線に直列にコンデンサCCを挿入しても
良く、この場合でも電圧配分の効果は変らない。 Note that the auxiliary winding is not a winding for transmitting power to the output side, and may be made of thinner wire than the primary and secondary windings, as shown in the circuit in Figure 3. A low resistance r may be inserted in series as shown in FIG. In addition, in order to absorb the DC component caused by the slight asymmetry of the switching waveform, a capacitor C C may be inserted in series with the primary winding as shown in Figure 3. Even in this case, the effect of voltage distribution is It doesn't change.
また１つのスイツチ回路内で直列接続する
MOS−FETの数は２個あるいは３個に限定され
ることなく所望の耐圧に応じて任意の数とするこ
とができる。スイツチング素子についても実施例
のＮチヤネルパワーMOS−FETに限定されるこ
となく、ＰチヤネルパワーMOS−FET、バイポ
ーラトランジスタ、SCR等のあらゆるスイツチ
ング素子を使用でき、この場合でも効果は同様で
ある。 Also, connect them in series within one switch circuit.
The number of MOS-FETs is not limited to two or three, but can be any number depending on the desired breakdown voltage. The switching element is not limited to the N-channel power MOS-FET of the embodiment, but any switching element such as a P-channel power MOS-FET, bipolar transistor, SCR, etc. can be used, and the same effect can be obtained in this case.
以上説明したように本発明によれば、４組のス
イツチ回路を有し、第１と第２のスイツチ回路
を、また第３と第４のスイツチ回路を直列接続
し、第１と第３のスイツチ回路を（＋）側電源端
子に、第２と第４のスイツチ回路を（−）側の電
源端子に接続してブリツジ回路を構成し、該スイ
ツチ回路同士の他の接続点の間に出力トランスの
１次巻線を接続し、該出力トランスの２次巻線よ
り出力を取り出すようにしたスイツチング電力変
換回路において、前記の各スイツチ回路が入力信
号に対して同一の位相でスイツチングするｎ個の
スイツチング素子を直列に接続して構成され互に
隣合つたスイツチ回路に対して入力信号が互に逆
位相をなして与えられることと、前記出力トラン
スに２（ｎ−１）個の補助巻線を設け、第１と第
３のスイツチ回路内部のスイツチング素子同士の
接続点の（＋）側電源端子からのそれぞれ等しい
順位の接続点の間に、また第２と第４のスイツチ
回路内部のスイツチング素子同士の接続点の
（−）側の電源端子からのそれぞれ等しい順位の
接続点の間に上記出力トランスに設けた補助巻線
を接続し、その巻数比が一次巻線を１に対し、各
スイツチ回路内に含まれるスイツチング素子の数
ｎと電源より前記補助巻線との接続点までに含ま
れるスイツチング素子の数ｍとの比ｍ／ｎで表わ
される値としたので、スイツチング素子の静電容
量やスイツチングのタイミングに拘らずオフ時の
スイツチ回路内の各スイツチング素子への電圧配
分を均等化でき、回路の耐圧をスイツチング素子
１つ当りの耐圧の直列数倍まで正確に増加させる
ことができる。また出力インピーダンスを低くし
なくても大電力化できるため、高出力ラジオ放送
機等の電力増幅器に利用できる等の利点がある。 As explained above, according to the present invention, there are four sets of switch circuits, the first and second switch circuits are connected in series, the third and fourth switch circuits are connected in series, and the first and third switch circuits are connected in series. A bridge circuit is constructed by connecting the switch circuit to the (+) side power supply terminal and the second and fourth switch circuits to the (-) side power supply terminal, and outputting between the other connection points between the switch circuits. In a switching power conversion circuit in which the primary winding of a transformer is connected and the output is taken out from the secondary winding of the output transformer, each of the above-mentioned switch circuits switches in the same phase with respect to the input signal. Input signals are provided in opposite phases to mutually adjacent switch circuits constructed by connecting switching elements in series, and the output transformer has 2(n-1) auxiliary windings. A line is provided between the connection points of the same order from the (+) side power supply terminal of the connection point between the switching elements inside the first and third switch circuits, and between the connection points inside the second and fourth switch circuits. The auxiliary winding provided in the output transformer is connected between the connection points of the equal order from the power supply terminal on the (-) side of the connection points between the switching elements, and the turns ratio is 1 for the primary winding. Since the value is expressed as the ratio m/n of the number n of switching elements included in each switch circuit to the number m of switching elements included from the power supply to the connection point with the auxiliary winding, the static It is possible to equalize the voltage distribution to each switching element in the switch circuit when off, regardless of capacitance or switching timing, and it is possible to accurately increase the circuit's withstand voltage to the number of times the withstand voltage of one switching element in series. can. Furthermore, since it is possible to increase the power without lowering the output impedance, it has the advantage that it can be used in power amplifiers such as high-output radio broadcasters.
図面は本発明の説明に供するもので、第１図は
従来のスイツチング電力増幅回路の回路図、第２
図は本発明のスイツチング電力変換回路の第１の
実施例を示すスイツチング電力増幅回路の回路
図、第３図は本発明の第２の実施例を示すスイツ
チング電力増幅回路の回路図である。
１……励振入力端子、２，３……電源端子、４
……出力端子、Ｑ１１，Ｑ１２，Ｑ１３，Ｑ２
１，Ｑ２２，Ｑ２３，Ｑ３１，Ｑ３２，Ｑ３３，
Ｑ４１，Ｑ４２，Ｑ４３……Ｎチヤネルパワー
MOS−FET、Ｔ１……入力トランス、Ｔ３，Ｔ
４……出力トランス、Ｗ１……１次巻線、Ｗ２…
…２次巻線、Ｗ３，Ｗ４，Ｗ５，Ｗ６……補助巻
線。
The drawings are for explaining the present invention, and FIG. 1 is a circuit diagram of a conventional switching power amplifier circuit, and FIG. 2 is a circuit diagram of a conventional switching power amplifier circuit.
FIG. 3 is a circuit diagram of a switching power amplifier circuit showing a first embodiment of the switching power conversion circuit of the present invention, and FIG. 3 is a circuit diagram of a switching power amplifier circuit showing a second embodiment of the present invention. 1...Excitation input terminal, 2, 3...Power terminal, 4
...Output terminal, Q11, Q12, Q13, Q2
1, Q22, Q23, Q31, Q32, Q33,
Q41, Q42, Q43...N channel power
MOS-FET, T1...Input transformer, T3, T
4... Output transformer, W1... Primary winding, W2...
...Secondary winding, W3, W4, W5, W6...Auxiliary winding.
Claims (1)
イツチ回路を、また第３と第４のスイツチ回路を
直列接続し、第１と第３のスイツチ回路を（＋）
側電源端子に、第２と第４のスイツチ回路を
（−）側の電源端子に接続してブリツジ回路を構
成し、該スイツチ回路同士の他の接続点の間に出
力トランスの１次巻線を接続し、該出力トランス
の２次巻線より出力を取り出すようにしたスイツ
チング電力変換回路において、前記の各スイツチ
回路が入力信号に対して同一の位相でスイツチン
グするｎ個のスイツチング素子を直列に接続して
構成され互に隣合つたスイツチ回路に対して入力
信号が互に逆位相をなして与えられることと、前
記出力トランスに２（ｎ−１）個の補助巻線を設
け、第１と第３のスイツチ回路内部のスイツチン
グ素子同士の接続点の（＋）側電源端子からのそ
れぞれ等しい順位の接続点の間に、また第２と第
４のスイツチ回路内部のスイツチング素子同士の
接続点の（−）側の電源端子からのそれぞれ等し
い順位の接続点の間に上記出力トランスに設けた
補助巻線を接続し、その巻数比が一次巻線を１に
対し、各スイツチ回路内に含まれるスイツチング
素子の数ｎと電源より前記補助巻線との接続点ま
でに含まれるスイツチング素子の数ｍとの比ｍ／
ｎであることとを特徴とするスイツチング電力変
換回路。1 It has 4 sets of switch circuits, the first and second switch circuits are connected in series, the third and fourth switch circuits are connected in series, and the first and third switch circuits are connected in series (+).
The second and fourth switch circuits are connected to the (-) side power supply terminal to form a bridge circuit, and the primary winding of the output transformer is connected between the other connection points of the switch circuits. In a switching power conversion circuit, in which the output transformer is connected to the output transformer and the output is taken out from the secondary winding of the output transformer, each of the switching circuits has n switching elements in series that switch in the same phase with respect to the input signal. Input signals are provided in opposite phases to mutually adjacent switch circuits connected to each other, and the output transformer is provided with 2(n-1) auxiliary windings, and the first and between the connection points of the same order from the (+) side power supply terminal of the connection points between the switching elements inside the third switch circuit, and between the connection points between the switching elements inside the second and fourth switch circuits. The auxiliary winding provided in the output transformer is connected between the connection points of the same order from the power supply terminal on the (-) side of The ratio m/
A switching power conversion circuit characterized in that n.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56135051A JPS5836179A (en) | 1981-08-28 | 1981-08-28 | Switching power converter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56135051A JPS5836179A (en) | 1981-08-28 | 1981-08-28 | Switching power converter circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5836179A JPS5836179A (en) | 1983-03-03 |
| JPH022391B2 true JPH022391B2 (en) | 1990-01-17 |
Family
ID=15142772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56135051A Granted JPS5836179A (en) | 1981-08-28 | 1981-08-28 | Switching power converter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5836179A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0006513D0 (en) * | 2000-03-18 | 2000-05-10 | Alstom | Improvements relating to converters |
| JP5820241B2 (en) | 2011-11-02 | 2015-11-24 | 浜松ホトニクス株式会社 | Capacitive load drive circuit |
-
1981
- 1981-08-28 JP JP56135051A patent/JPS5836179A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5836179A (en) | 1983-03-03 |
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