JPH02237369A - Picture data processor - Google Patents

Abstract

PURPOSE:To minimize the hardware of an arithmetic means by using a common arithmetic means to apply DCT(discrete cosine transmission) or an inverse DCT to a picture data based on a control data read from a designated area of a control data storage means. CONSTITUTION:A readout area is designated in response to a desired conversion to a control data storage means 6 in which a control data required for the DCT and a control data required for the inverse DCT transformation are stored in different areas. Then the DCT or the inverse DCT is executed to the picture data stored in a picture data storage means 12 by using an arithmetic means of the hardware in common to each transformation based on the readout control data. Thus, the hardware of the arithmetic means is minimized and advantageous economically.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application of "Industry" 2] The present invention relates to an image data processing device used for compression processing of image data.

[Prior Art] Recently, image data compression processing using Discrete Cosine Transformation (hereinafter abbreviated as DCT) has been used in fields such as videophones.

Here, DCT is one of orthogonal transformations, and Karnen
Along with the Lewe transformation, this is said to be the transformation method with the highest degree of energy concentration.

Now, the signal f (j) (j=0, ],... N-1)
The result of one-dimensional DCT of F (u)(u-0,1,・
... N-1) is defined by the following formula.

u=Os 1 , -N − 1 However, when u=0, c(u)=1. /v' When 10,000 U≠O
c (u) = 1 Also, the inverse transformation is f(j)-ΣC(u)P(u)cos[(2j+J)
uπ/2N: 1j=0, 1, . . . , N+].

In other words, DCT divides a certain waveform into frequency components,
It is expressed by the same number of cosine waves as the number of input samples. And each waveform is F (0): DC F (1): cos [(2j+1) π/2N]F
(2): Expressed as cos [(2j+1)2π/2N]. Here, when N=8, the result is as shown in FIG.

By applying such orthogonal transformation to an image, energy is concentrated, and by encoding only the components with a large amount of energy, image data can be compressed.

By the way, if you try to calculate such a DCT using the definition formula, the calculation time will be enormous, so it will take a considerable amount of time to process on a general-purpose microprocessor.
Not realistic.

Therefore, in order to efficiently execute the DCT operation, reference document IEEETI? ANSACTION ON COMM
UNICATIONS VOL. COM-25, No.
II, NOVEMBER 1977 (Adapti
veCoding of' Monochrome a
nd Color Image, WEN-HSIUN
G CHEN, C. IIARRISON SMITI
The DCT flow graph disclosed in ``+'' is considered. FIG. 10 shows an example of such a DCT flow graph, and here, an 8th order DCT flow graph is shown. In the case of DCT, calculation processing using such a graph is performed from left to right,
In the case of inverse DCT, calculations are performed from right to left.

However, conventionally, using such a flow graph, D
For executing CT or inverse DCT, independent hardware is prepared for the DCT and inverse DCT calculation means, or the main calculation part is common, and the control circuit of such calculation means is used for DCT and inverse DCT.
There are some that switch to a dedicated circuit depending on the situation.

[Problem to be solved by the invention] However, these conventional methods are
Although there are differences in the degree of calculation, each method requires a dedicated circuit, so the hardware for the calculation means is large-scale and expensive, which is disadvantageous economically.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an economically advantageous image data processing device that can execute DCT and inverse DCT using arithmetic means made of common hardware. target

[Means for Solving the Problems] The present invention has a control data storage means in which control data necessary for DCT transformation and control data necessary for inverse DCT transformation are stored in different areas, and a desired By specifying a readout area according to the conversion to be performed, DCT transformation or inverse DCT transformation is performed on the image data stored in the image data storage means based on the control data read from the designated area of the control data storage means. is executed by a hardware calculation means common to each conversion.

[Effect] As a result, D
Since each of the CT transformation and the inverse DCT transformation can be executed individually, the hardware of the calculation means can be minimized, making it extremely economically advantageous.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration of the main circuit of the same embodiment. In the figure, 1 is an external interface circuit, and this external interface circuit 1 has a command register that is addressed by a control signal CP (10:12) from a CPU (not shown), and has internal operation/external operation, DCT/inverse DCT.
CT, READ/WR I TE, Y/B-Y-R-Y
At the same time, the flag EXEC is set to control the entire system. Also, 2
It has a function of outputting the NBUSY signal to the outside during dimensional DCT calculation or quantization. 2 is a timing generator, and this timing generator 2 generates a basic timing clock for operating the system.

3 is a 10-bit synchronous counter, and this counter 3 specifies the clock P3 from the timing generator 2 as a count 1-t, and an address of a sequencer memory 6, which will be described later. Here, the synchronous counter 3 is constructed as shown in FIG.

31 is an OR circuit, and one input terminal of this OR circuit 31 is connected to a sequence memory 6 via an inverter 32, which will be described later.
The end mark signal LNEND written together with the DCT conversion control program is applied to the other input terminal, and the count contents CT (0) to CT of the counter 8, which will be described later, are input to the other input terminal.
The output of the NAND circuit 33 to which (3) is input is given. The output of this OR circuit 31 is connected to one input terminal of an AND circuit 34. available. The other input terminal of this AND circuit 34 receives a flag EX from the external interface 1.
EC output is given. The output of the AND circuit 34 is applied to the D terminal of the flip-flop 35.

The output from the Q terminal of the flip-flop 35 is applied to the D terminal of the flip-flop 36, one input terminal of the NOR circuit 37, and one input terminal of the AND circuit 38.
The output from the Q terminal is given to one input terminal of the NAND circuit 39. Further, the output from the Q terminal of the flip-flop 36 is applied to the other input terminal of the NOR circuit 37, and the output from the Q terminal is applied to the other input terminal of the Nantes circuit 39. From the NOR circuit 37, the busy signal NBU
SY is output. Further, the other input terminal of the AND circuit 38 is connected to the clock P from the timing generator 2.
3 is given, and this clock P3 is outputted to the counter 40. Furthermore, the output of the NAND circuit 39 is given to one input terminal of the NAND circuit 41.

The write enable signal WE is applied to the other input terminal of the NAND circuit 4, and the NWE signal is output from its output terminal. The counter 40 consists of three 4-bit binary counters 401, 402, and 403, and is used to count the clock P3 given by the AND circuit 38 and read out the data in the sequence memory 6.
) to IA(9) are output. Note that the reset signal RESET is applied to the inverter 4.
CLR terminal of flip-flop 35.36 through 2,
Binary counters 401 and 40 forming the counter 40
The end mark signal LNEND is applied to the CLR terminals of the pinary counters 401, 402, and 40B via the inverter 32. Further, the timing signal A R C K is applied to the CK terminals of flip-flops 35 and 36.

Returning to FIG. 1, 4, 5, and 11 are 2 tol multiplexers, of which multiplexer 4 has a width of 1 bit, and multiplexers 5 and ]1 both have a width of 10 bits. These multiplexers 4, 5, 1] are connected to the A side input when the control signal CPU from the CPU is at rLJ level.
” level, B side human power is selected. In this case, the multiplexer 4 receives the write enable signal NCWE from the timing generator 2 or the CPU, and the multiplexer 5 receives the address signal IA (0:9) from the synchronous counter 3 or the address signal CP from the CPU.
(0:9), multiplexer] 1 is address conversion circuit 1
0 output or an address signal (0:9) from the CPU via the converter 23 is selected.

Reference numeral 6 denotes a sequence memory, and this memory 6 stores various control data required for DCT or inverse DCT calculations provided from an external interface circuit as a program for each step, and also writes an end mark signal LNEND at a predetermined step. It's included. in this case,
The control data required for DCT and inverse DCT are stored in different areas; here, the DCT program is stored in the lower area, and the inverse DCT program is stored in the upper area.
It is designed to specify and read one of the programs. Here, the sequence memory 6 includes 4 rewritable
It consists of 0 bits x 2K RAM and supports up to 10 bits of control signals required for DCT or inverse DCT calculations.
It is possible to run programs with up to 24 steps. FIG. 4 shows a configuration diagram of the sequence memory 6, in which 3 bits are the read address AR (0:2) of the A area of the dual port memory 12, and 3 bits are the read address AR (0:2) of the A area of the dual port memory 12.
The write address AW (0:2) of the A area of the same memory 12 and the 3 bits are read address BR (0:2
) 3 bits 1. are the write 1 address BW (0:2) of the B area of the same memory 12, 5 bits are the control SA (0:4) of the shifter 17, and 1 bit 1. is the control 1 address of the adder/subtractor 1. Roll ASA, 2 bit 1 flip flop 13
, ]4 latch mode AM (0:1), 5 bits as control 1/roll SB of shifter 18 (0:4), 1 bit as control ASB of adder/subtractor 20, 2 bits as latch mode of flip-flops 15 and 16 BM(0:
1), 1 bit as through/loop switching AT of calculation system A
L, 1 bit 1. through/loop switching BT of calculation system B
L, 1 bit is cross/parallel switching CP, 1 bit is sequencer ent mark LNEND, 2 bits is quantized data AN of calculation system A (0: 1), 2 bits is quantized data BN of calculation system B (0: 1.), ] bit 1 is used for quantization controller 1 roll COMP.

Various control signals of the sequence memory 6 are an inverted signal N of the clock P3 from the timing generator 2.
After being temporarily latched by the flip-flop 7 at the rising edge of P3, it is output.

Here, the end mark signal LNEND latched by the flip-flop 7 is applied to the counter 8 via the inverter 24. In this case, the counter 8 is a 4-bit one that counts the falling edge of the end mark signal LNEND, and performs primary row operations from 0 to 711 on 8x8 sub-block image data from 8 to FH. The second-order column operation is performed using Also, read address AR (0:2) stored in flip-flop 7
, write address AW (0 2 2) are given to the address conversion circuit 9, and read address BR (0:2) and write address BW (0:2) are given to the address conversion circuit 10, respectively. The address conversion circuit 9 reads the read address AR from the flip]2 flop 7 (0:2)
, lie 1 address AW (0:2) and counter 8
The address conversion circuit 10 outputs the address signal A (0:9) of the A area of the dual port memory 12 from the count value of , and the address conversion circuit 10 outputs the address signal A (0:9) of the A area of the dual port memory 12, and the write address BW (0:2) from the flip-flop 7. 2) and the count value of counter 8, dual port 1/memory 1
Address signal B (0:9) of area B of 2 is output.

The dual port memory 12 stores image data and is composed of 16 bits x 1024 words.

2 simultaneously according to address signals A (0:9) and B (0:9) from address conversion circuits 9 and 10.
data MA (0:15), MB (0:15
) can be written and read.

In addition, this dual port memory 12 is used not only to store input data when performing DCT or inverse DCT and output data that is the result of the calculation, but also as a work memory to temporarily store data in the middle of calculation. It will be done.

Next, FIG. 2 shows the circuit configuration of the arithmetic unit of the same embodiment. In this case, the arithmetic unit has two arithmetic systems A and B.

1.3 and 14 are a group of 16-bit flip-flops, and the first data MA (0:
15) Latch. Also, 15 and 16 are also 16 bit 1.
The second data MB (0:15) from the dual port memory 12 is latched by a group of flip-flops. Here, the operation timing of the flip-flop groups 13 and 16 is determined by the timing signal ARCKSBRCK.
The operation timing of flip-flop groups 4 and 15 is determined by timing signals ARPCK and BRPCK.

The data latched in the flip-flop group 13 is applied to the shifter 17 and also to the ten terminals of the adder/subtractor 20 via the gate Gl, and the data latched in the flip-flop group 16 is applied to the shifter 18 and the gate G2. The signal is applied to the 10 terminal of the adder/subtractor 19 via the .

Furthermore, the data latched in the flip-flop group 14 is applied to the 10 terminal of the adder/subtractor 9 via the gate G7.
The data latched in the flip-flop group 15 is
・Given to the 10 terminal of one adder/subtractor via G8.

Here, the shifter] 7 is constructed as shown in FIG. 5] is a barrel shifter, and this λ barrel shifter 51 can shift 16-bit 1 data up and down by 8 bits in units of 1 bit, and the amount of shift here is controlled by the output of the multiplexer 52. And normal DC
In the T operation, if the quantization control 1 roll COMP is at the rLJ level, the multiplexer 52 outputs the shifter control 1 roll SA (0
:4) Thus controlled, quantization control 1 roll COM
In the case of P or rHJ level, the output of the table 54 is controlled by waiting for the AND circuit to reach rHJ level. Here, the table 54 has quantized data AN
(0:1), the shift amount shown in FIG. 6(a) corresponds to the counter l value CT of the force counter 8 (0:2), as shown in FIG. 6(b). The table shown in C) is configured to enable power-of-2 quantization in pixel units of 8×8 sub-blocks. here,
Figure 6(b) shows the luminance signal Y1. Figure 6(C) shows the color difference signal B-.
A table of Y and RY is shown. Also, both quantized data AN (0) and AN (1.) are "]",
Based on the output of the NAND circuit 55, the output from the barrel shifter 5 is clipped by a clip circuit 56. This means that a 16-bit shift converts harmonic component data to 0.
This is because the purpose is to Of course, the other shifter 18 is also similar to the lid 17.

Returning to FIG. 2, the output from shifter 17 is output from adder/subtractor 19.
The output from the shifter]8 is given to the terminal of the adder/subtractor 20 and written to the dual port 1 memory 12 via gate 1 and G3. dual port 1 memory] 2. The adders and subtracters 19 and 20 are composed of 4-bit full adders x 4 and an EXOR group, and are designed to perform two's complement arithmetic. And one of these adders/subtractors, 20
The results of the calculations are latched in flip-flops 21 and 22, respectively, and then written to the dual port 1 memory 12 through gates G5 and G6, respectively. Here, the operation timing of the flip-flops 21 and 22 is determined by the timing signal ALCK.

Next, the operation of the embodiment configured as described above will be explained.

In this case, when the control signal CPU from the CPU is at the rLJ level, both the multiplexers 4 and 5 select the A manual side. In addition, the sequence memory 6 already has a DCT program in the lower area and a reverse DCT program in the upper area.
Each CT program has been loaded, and from this state, the area designation signal DC of external interface 1 is now
DCT of lower area of sequence memory 6 by T I
Assume that a program has been specified.

First, in FIG. 3, the flip-flops 35 and 36 and the counter 40 are cleared by the reset 1 signal RESET. After that, the 8-bit image data is expanded to signed 16-bit data and transferred from the CPU to the DB (0:7
) to the dual port memory 12. Then, when all 16 bits x 64 pieces of data of the 8 x 8 sub-blocks have been written, the flag EXEC is set in the external interface 1 [FIG. 7(b)]. Then,
Since the output of the AND circuit 34 becomes rHJ level, [7th]
Timing signal A R shown in Figure (10) and Figure 7 (C)
Q of flip-flops 35 and 36 at the rising edge of CK
The outputs of the terminals become rHJ level [Fig. 7(d) (
e)] The clock P3 shown in FIG. 7(a) is supplied to the counter 40 via the AND circuit 38 [FIG. 7(f)]
. At the same time, the output of the NOR circuit 37 becomes rLJ level, and a busy signal NBUSY is output to the CPU [FIG. 7(l)].

Also, since the output of the NAND circuit 39 is at the rHJ level, the write enable signal shown in FIG.
- Output as enable signal NWE [Figure 7 (m
)]. In this state, control data is read out from the output of the counter 40 or given to the sequence memory 6 as the address No. 1 IA (0+9) from the synchronous counter 3, and DCT conversion is performed [Fig. 7 (g)] . here,
ill read out in the third step of the sequence memory 6
When the end mark signal LNEND is written in the control data as shown in FIG. 7(h), the counter 40 is loaded with O at the rising edge of the next applied clock P3 and is reset. End mark signal LN
At the falling edge of END, the count contents of counter 8 CT (0
: 3) begins to count up [Figure 7 (
1)]. In this case, the count content CT (
0.3), the 8×8 DCT transform advances to the second row. By repeating the same operation,
It reaches the final stage of 2D (No. 8 rl) and CT (0:
3) When it reaches 15, r of end mark signal LNEND
Due to the HJ level, the output of the OR circuit 31 becomes the rLJ level, and the next applied timing signal ARCK causes the output of the Q terminal of the flip-flop 35 to become the rLJ level, so the clock P3 applied to the counter 40 through the AND circuit 38 is stopped. , data reading from the sequence memory 6 is also stopped. Also, with a delay of one timing due to the flip-flop 36, the lie 1/enable number NWE is
will also be suspended.

Next, the calculation timing in the calculation section will be explained.

First, the address signal IA (0:9) from the synchronous counter 3 to the sequence memory 6 shown in FIG. 8(C) is set to 0, 1, 2 by the clock P3 from the timing generator 2 shown in FIG. 8(a). . . , the sequence data is read out from the sequence memory 6 [FIG. 8(c+)], and is latched into the flip-flop 7 by the falling signal NP3 of the clock signal P3 [FIG. 8(c+)].
e)]. This state is maintained for one cycle of operations.

Here, the first half of one cycle is a read section of the dual port 1 memory 12 as shown in FIG.
:2), BR (0:2) are given to the address conversion circuit 9,]0, and the dual baud is output as the first and second address signals A (0:9) and B (0:9).
1.Given to memory 12.

As a result, data MA(0:
1.5), MB (0: 1.5) are read at the same time, and the timing signal ARCK.1.5) shown in FIG. 8(g) is generated.
．． At the timing of BRCK, flip-flop 13,]
6 is latched, and then predetermined calculations are executed in the adders/subtracters 19 and 20 [FIG. 8(i)].

Here, if the cross-parallel switching CP from flip-flop 7 is at the HJ level, gates GL and G2 are closed, gates 1-G7 and G8 are open, and flip-flop 13 is closed.
The data latched into the adder/subtractor via the shifter 17]
It is applied to the + terminal of the adder/subtractor 20 via the gate GL, and is applied to the + terminal of the flip-flop 1.
The data latched in the gate 6 is applied to the terminal of the adder/subtractor 20 via the shifter 18, and the data latched in the gate 1-02
When the cross-parallel switching CP is at the rLJ level, gates G1 and G2 are opened, gates 1-G7 and G8 are closed, and latched in the flip-flop 13. The data latched to the flip-flop 14 is applied to the adder/subtractor 19 through the shifter 17, the data latched to the flip-flop 14 is applied to the adder/subtractor 19, and the data latched to the flip-flop 16 is applied to the shifter 18. The data which is applied to the 10 terminal of the adder/subtractor 20 through the adder/subtractor 20 and latched by the flip-flop 5 is now applied to the 10 terminal of the adder/subtractor 20, and a predetermined operation is executed. Then, when the calculations in each adder/subtractor 19 and 20 are executed, the second half of the lie 1 section shown in FIG. is latched in the flip-flops 21 and 22, and the lie 1 enable signal NWE shown in FIG. 8(j) is generated.
It is written to the address addressed by AW (0:2) and BW (0:2) of dual port 1 memory]2 at the rising timing of . In addition, when the through loop switching becomes ATL, BTL or rHJ level, game 1/G3
, in the case of through mode where G4 is opened, the lid 17,
The result shifted by 18 is directly transferred to the dual port 1.
The data is now written to the memory 12.

In the above explanation, the DCT program in the lower area of the sequence memory 6 is designated by the area designation signal DCTI from the external interface, and the DCT operation is executed for this program. Reverse D of upper area of 6
Even when a CT program is specified, each circuit is operated according to the control data of the program in the same manner as described above.
An inverse DCT operation is now performed.

[Effects of the Invention] The present invention has a control data storage means that stores control data necessary for DCT transformation and control data necessary for inverse DCT transformation in different areas, and stores a desired transformation in the storage means. By specifying a readout area according to the specified area of the control data storage means, DCT transformation or inverse DCT transformation is performed on the image data stored in the image data storage means based on the control data read out from the specified area of the control data storage means. As a result, the DCT transformation and inverse DCT transformation can be executed by the calculation means made of the same hardware, and as a result, the hardware of the calculation means can be reduced. It can be extremely advantageous economically as it can be minimized and the price can be reduced.

[Brief explanation of drawings]

FIGS. 1 and 2 are block diagrams showing the circuit configuration of an embodiment of the present invention, FIG. 3 is a block diagram showing the circuit configuration of a numerical counter used in the embodiment, and FIG. FIG. 5 is a block diagram showing the circuit configuration of the shifter used in the same embodiment, FIG. 6 is a diagram for explaining the shifter, and FIGS. 7 and 8 are the same embodiment. Figure 9 is a time chart for explaining DCT.
FIG. 10 is a diagram showing an example of a DCT flow graph used for DCT calculation. 1... External interface, 2... Timing generator, 3... Synchronous counter, 4, 5,
]1...Multiplexer, 6...Sequence memory, 7...Flip-flop, 8...Counter, 9,
]0... Address conversion circuit, ]2... Dual port 1 memory, 13-]6, 2], 22... flip-flop, ]7, 18... shifter, 19, 2o... addition/subtraction vessel. Applicant's agent Patent attorney Takehiko Suzuru

Claims (1)

[Claims] control data storage means that stores control data necessary for discrete cosine transformation and control data necessary for inverse discrete cosine transformation in different areas; image data storage means that stores image data; readout area designation means for designating a readout area of the storage means; and discrete cosine processing for the image data in the image data storage means based on control data read out from the area of the control data storage means specified by the designation means. 1. An image data processing device comprising: arithmetic means common to each transform that executes a transform or an inverse discrete cosine transform.