JP2002159006A - Calculation assisting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a calculation assisting circuit which can be manufactured at a low cost in a short manufacturing time and can be appropriately reduced in circuit scale and improved in computing speed. SOLUTION: An image processing system performs the compression or decompression of image data by the encoding method using the DCT with software and hardware and is constituted by connecting a CPU 40, an external image memory 44, and a calculation assisting circuit 50 to each other through a bus. The calculation assisting circuit 50 is provided with an internal arithmetic circuit 52 and buffers 54-58 which are accessible from both the CPU 40 and circuit 52. Upon receiving an instruction to perform a YUV conversion, an RGB conversion, a quantization calculation, or an inverse quantization calculation, the internal arithmetic circuit 52 reads data from the buffers 54-58, performs calculation including a common calculation which is commonly performed in the above-mentioned calculations based on the plurality of read data, and writes the results of the calculation in the buffers 54-58.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for assisting processing of a CPU for compressing or decompressing image data by software, and is particularly advantageous in terms of cost and production time, and furthermore, the circuit size can be reduced. And an arithmetic auxiliary circuit suitable for improving the arithmetic speed.

[0002]

2. Description of the Related Art When an image is digitized and stored in a storage medium such as a CD-ROM or a hard disk, the amount of data is enormous. Among various compression coding methods, a coding method using DCT (Discrete Cosine Transform), which performs compression while paying attention to the property that the spatial frequency of an image is concentrated on a low frequency, is relatively frequently used. A typical example is JPEG (Joint Photographic Exp
erts Group) and MPEG (Moving Picture Experts Gro
This method is adopted in an encoding method which is an international standard such as up).

[0003] In the coding method based on DCT, compression and decompression of image data are performed, for example, as shown in FIG. FIG. 7 is a diagram illustrating a process of compressing and decompressing image data by an encoding method using DCT.

First, when compressing image data, as shown on the left side of FIG. 7, a YUV conversion unit 10 for performing YUV conversion on image data composed of RGB data,
A thinning unit 12 that thins out data from the transforming unit 10, a DCT unit 14 that performs DCT on data from the thinning unit 12, and a quantization that performs a quantization operation on data from the DCT unit 14. The operation unit 16 and the quantization operation unit 1
6 includes a zigzag scan unit 18 that performs a zigzag scan on the data from the data unit 6 and a variable length encoding unit 20 that performs a variable length (Huffman) encoding on the data from the zigzag scan unit 18. The image data is compressed through the respective processes of.

Next, when decompressing image data, as shown on the right side of FIG. 7, a variable length decoding unit 22 for performing variable length decoding on the compressed image data and a variable length decoding unit 22
Inverse zigzag scan unit 24 that performs an inverse zigzag scan on data from the first unit, and an inverse quantization operation unit 2 that performs an inverse quantization operation on the data from the inverse zigzag scan unit 24
6 and IDC for the data from the inverse quantization operation unit 26
An IDCT unit 28 that performs T (Inverse Discrete Cosine Transorm), an interpolation unit 30 that performs interpolation on data from the IDCT unit 28, and an interpolation unit 30
Conversion unit 3 that performs RGB conversion on data from
And decompresses the compressed image data through each processing by these processing units 22 to 32.

[0006] The zigzag scan is a horizontal direction 8
This is a process in which image data of pixels and image data of 8 pixels in the vertical direction (hereinafter, abbreviated as 8 × 8 pixels) are subjected to a quantization operation and rearranged in ascending order of frequency components in the horizontal and vertical directions. . Inverse zigzag scan
This is the reverse process.

Conventionally, as a method of compressing or decompressing image data by such processing, a first method in which all of the above processing is performed by software, a second method in which all of the processing is performed by hardware, There is a third method in which part of the processing is performed by software and the remaining part is performed by hardware.

However, in the first method, since the processing is performed in units of 8 × 8 pixel image data, the image data is frequently rearranged. Therefore, address calculation,
It is necessary to perform random memory access, etc.,
Computation processing takes time. For example, when a relatively inexpensive memory device such as a DRAM is used, it is difficult to perform high-speed random access. Therefore, when data is read from the memory device and operated by the CPU, the processing time for the read becomes long. , Will have a big impact on overall performance.

The second method is very effective when a high processing speed is required.
The flexibility of the system is inferior, and the production of appropriate hardware is disadvantageous in terms of time and cost, and it is extremely difficult to incorporate it into a low-cost product with a fast development cycle.

[0010] On the other hand, the third method is based on the second method.
Since this method can solve the problems of the two methods to some extent, it is a method frequently used in recent designs.

[0011]

However, in the above-mentioned third method, it is not determined which of the processing for compressing or decompressing image data is performed by software and which is performed by hardware. Surprisingly difficult. If much of the processing is shifted to hardware, the speed can be increased, but it is not only disadvantageous in terms of cost and manufacturing time, but also the circuit must be provided according to the number of processing, and the circuit scale increases There is a problem. Conversely, if much of the processing is shifted to software, it is advantageous in terms of cost and manufacturing time, and although the circuit size can be reduced, there is a problem that the processing time increases.

Further, when processing is transferred from software to hardware, software processing is performed by RA
The data is transferred from the M or the like to the memory on the hardware side, and when the transfer is completed, a start instruction indicating that the hardware processing is started is output to the hardware side. Since the processing is started after waiting for the start command, the hardware is on standby until the transfer by the software processing is completely completed. Therefore, the waiting time has been a bottleneck in improving the overall operation speed.

The present invention has been made in view of such unresolved problems of the prior art, and has been realized in terms of cost and manufacturing time while realizing high-speed processing by hardware. It is an object of the present invention to provide an arithmetic auxiliary circuit which is advantageous and suitable for reducing the circuit scale and improving the arithmetic speed.

[0014]

According to another aspect of the present invention, there is provided an arithmetic assisting circuit for assisting arithmetic operation of an external arithmetic means, comprising: an internal arithmetic means; Storage means accessible by both the external operation means and the internal operation means, wherein the internal operation means reads data from the storage means and, based on the read data, a plurality of common operations, An operation including a common operation common to the respective operation methods is performed by one of the operation methods designated, and the operation result is written in the storage means.

With such a configuration, one of a plurality of arithmetic methods is designated by the external arithmetic means,
When the data is written to the storage means, the data is read from the storage means by the internal calculation means, and based on the read data, a calculation including a common calculation common to each calculation method is performed by a specified calculation method. , And the operation result is written to the storage means.

Further, according to a second aspect of the present invention, there is provided a circuit for assisting an operation of an external operation means, wherein the internal operation means and both the external operation means and the internal operation means have access. Possible storage means, wherein the internal calculation means reads data from the storage means, performs a predetermined calculation based on the read data, and writes the calculation result to the storage means, The reading, the arithmetic operation, and the writing are performed in parallel with the writing operation to the storage unit by the external arithmetic unit while referring to a writing state by the external arithmetic unit.

With such a configuration, when data is written to the storage means by the external calculation means, the data is read from the storage means by the internal calculation means, and a predetermined calculation is performed based on the read data. Then, the operation result is written into the storage means. At this time, reading, calculation, and writing are performed in parallel with the writing operation to the storage unit by the external arithmetic unit while referring to the writing state by the external arithmetic unit.

Further, an arithmetic assisting circuit according to a third aspect of the present invention is a circuit for assisting the arithmetic operation of the external arithmetic means, wherein the internal arithmetic means and both the external arithmetic means and the internal arithmetic means have access. A plurality of possible storage means, wherein the internal calculation means reads data from each of the storage means, and designates, based on the plurality of read data, a plurality of calculation methods in which a part of the calculation is common. The operation including the common operation common to each of the operation methods is performed by any one of the methods, and when the operation result is one, the operation result is written to any of the plurality of storage units, and the operation result is stored. When there are a plurality of data, the respective calculation results are written in different storage means.

With such a configuration, one of a plurality of arithmetic methods is designated by the external arithmetic means,
When data is written to each storage means, the data is read from each storage means by the internal calculation means, and a common calculation common to each calculation method is performed based on the plurality of read data by a designated calculation method. An operation including is performed. As a result, when there is one operation result, the operation result is written to any of the plurality of storage units, and when there is more than one operation result, each operation result is written to a different storage unit. .

The arithmetic assisting circuit according to claim 4 of the present invention is a circuit for assisting the arithmetic operation of the external arithmetic means, wherein the internal arithmetic means and both the external arithmetic means and the internal arithmetic means have access. A plurality of possible storage means, wherein the internal calculation means reads data from each of the storage means, performs a predetermined calculation based on the read plurality of data, and when the calculation result is one, The calculation result is written to any of the plurality of storage means, and when the calculation result is a plurality, each calculation result is written to a different storage means. The reading, the calculation, and the writing are performed in parallel with the writing operation to the memory while referring to the writing state by the external calculation means.

With such a configuration, when data is written into each storage means by the external arithmetic means, the data is read from each storage means by the internal arithmetic means, and based on the plurality of read data, A predetermined operation is performed. As a result, when there is one operation result, the operation result is written to any of the plurality of storage units, and when there is more than one operation result, each operation result is written to a different storage unit. . At this time, reading, calculation, and writing are performed in parallel with the writing operation to the storage unit by the external arithmetic unit while referring to the writing state by the external arithmetic unit.

According to a fifth aspect of the present invention, there is provided the arithmetic assisting circuit according to any one of the first and third aspects, wherein the internal arithmetic means is connected to the storage means by the external arithmetic means. In parallel with the writing operation of the above, the reading,
The calculation and the writing are performed.

With such a configuration, reading, calculation, and writing are performed by the internal arithmetic means in parallel with the writing operation to the storage means by the external arithmetic means while referring to the writing situation by the external arithmetic means. Done.

The arithmetic assisting circuit according to the present invention may further comprise an image data compressing process for compressing image data by performing a dye conversion, a discrete cosine transform, a quantization operation, and a zigzag scan, or vice versa. A circuit for assisting the processing of an external arithmetic means for performing image data decompression processing for decompressing compressed image data via the internal arithmetic means,
A first storage unit, a second storage unit, and a third storage unit accessible by both the external operation unit and the internal operation unit;
Wherein the internal calculation means reads data from the first to third storage means, and based on the plurality of read data, a plurality of calculation methods in which a part of the calculation is common. Performing an operation including a common operation common to each of the operation methods, and if the operation result is one, the operation result is stored in one of the first to third storage units. When there are a plurality of calculation results, the respective calculation results are written to different storage means.

With such a configuration, one of a plurality of arithmetic methods is designated by the external arithmetic means,
When data is written to the first to third storage means,
The internal operation means reads data from the first to third storage means, respectively, and performs an operation including a common operation common to each operation method by a designated operation method based on the plurality of read data. . As a result, when there is one operation result, the operation result is written to any of the plurality of storage units, and when there is more than one operation result, each operation result is written to a different storage unit. .

According to a seventh aspect of the present invention, in the arithmetic auxiliary circuit according to the sixth aspect, the internal arithmetic means performs the dye conversion as an instruction for specifying the arithmetic method. When a dye conversion command is given, data is read from each of the first to third storage units, and a first product-sum operation, a second product-sum operation, and a second product-sum operation are performed based on the read three data. 3, the first product-sum operation result is stored in the first storage means, the second product-sum operation result is stored in the second storage means, and the third product-sum operation result is stored. Is written into the third storage means, and the first to third multiply-accumulate operations multiply each of the read three data by a coefficient and add the respective multiplication results. It is.

With such a configuration, when a dye conversion command is given, data is read from the first to third storage means by the internal operation means, and the data is read out based on the three read data. The first product-sum operation, the second product-sum operation, and the third product-sum operation are performed. In the first to third product-sum operations, the read three data are multiplied by coefficients, and the results of the multiplication are added. Then, the first product-sum operation result is stored in the first storage means,
The second product-sum operation result is written to the second storage means, and the third product-sum operation result is written to the third storage means.

According to a further aspect of the present invention, in the arithmetic auxiliary circuit according to any one of the sixth and seventh aspects, the internal arithmetic means includes the instruction as an instruction for specifying the arithmetic method. When a quantization operation command indicating that a quantization operation is to be performed is given, data is read from the first to third storage units, and a predetermined calculation is performed based on the read three data. A part of the predetermined operation result is written into one of the first to third storage units, and the remaining part of the predetermined operation result is written into another storage unit. The predetermined operation is to multiply data obtained by combining data read from the first and second storage means with data read from the third storage means.

With such a configuration, when a quantization operation command is given, the first to third signals are output by the internal operation means.
Are read from the storage means, and a predetermined operation is performed based on the read three data. In the predetermined operation, data obtained by combining data read from the first and second storage units is multiplied by data read from the third storage unit. Then, a part of the predetermined operation result is written to one of the first to third storage units, and the remaining part of the predetermined operation result is written to the other storage units.

Here, the quantization operation is not limited to the quantization operation performed in the process of compressing image data, but also includes the inverse quantization operation performed in the process of decompressing image data.

Further, according to a ninth aspect of the present invention, in the arithmetic auxiliary circuit according to any one of the sixth to eighth aspects, the internal arithmetic means is connected to the storage means by the external arithmetic means. In parallel with the writing operation of the above, the reading,
The calculation and the writing are performed.

With such a configuration, reading, calculation and writing can be performed by the internal arithmetic means in parallel with the writing operation to the storage means by the external arithmetic means while referring to the writing situation by the external arithmetic means. Done.

Further, according to a tenth aspect of the present invention, in the arithmetic auxiliary circuit according to the ninth aspect,
The operation by the internal arithmetic means includes a read state for performing the read, an arithmetic state for performing the arithmetic, a write state for performing the write, and a standby state for performing the standby. When the external arithmetic means is accessing or starting to access the first to third storage means, the writing is performed after the access by the external arithmetic means is completed. In the waiting state,
When data to be read in the next reading state has not been written to the first to third storage means, the apparatus waits until the writing is completed.

With this configuration, in the write state, when the external arithmetic means is accessing or starting to access the first to third storage means, the external arithmetic means uses the external arithmetic means. Writing is performed after the access is completed. In the standby state, if data to be read in the next read state has not been written to the first to third storage means, it waits until the writing is completed.

Further, according to an eleventh aspect of the present invention, in the arithmetic auxiliary circuit according to any one of the sixth to tenth aspects, the internal arithmetic means outputs the arithmetic result based on the arithmetic result. Is written to any one of the addresses of the first to third storage means from which the read data is read.

With such a configuration, the calculation result is written by the internal calculation means to any of the addresses of the first to third storage means from which the data on which the calculation is based is read.

According to a twelfth aspect of the present invention, in the arithmetic auxiliary circuit according to any one of the sixth to eleventh aspects, the external arithmetic means is provided in the first to third storage means. Address conversion means for converting a read address or a write address when reading or writing the data, wherein the address conversion means indicates that the zigzag scan is to be performed as a command for specifying the operation method. Is given, the read address or write address of the external arithmetic means is converted according to a predetermined rule.

With such a configuration, when a zigzag scan instruction is given, the read address or write address of the external arithmetic means is converted by the address conversion means according to a predetermined rule.

Here, the zigzag scan is not limited to the zigzag scan performed in the process of compressing image data, but also includes the inverse zigzag scan performed in the process of decompressing image data.

Further, according to a thirteenth aspect of the present invention, in the arithmetic auxiliary circuit according to any one of the sixth to twelfth aspects, the data read from the first to third storage means are respectively stored. First to third reading-side holding means for holding, and first to third means for respectively holding calculation results to be written in the first to third storage means.
Writing-side holding means, coefficient holding means for holding the coefficients used in the calculation, and a first multiplier for multiplying any of the coefficient holding means by the data of the first reading-side holding means A second multiplier for multiplying any one of the coefficients of the coefficient holding means by the data of the second reading-side holding means; and any one of the coefficients of the coefficient holding means and the third reading-side holding A third multiplier for multiplying the data of the means, an adder for adding the operation results of the first to third multipliers, the first to third write-side holding means, and the adder; Path switching means for switching any one of the data paths connecting the first and second reading-side holding means, and combining the data of the first and second reading-side holding means to form the first reading-side holding means as data of the first reading-side holding means. First data output means for outputting to the first multiplier; And a second data output means for outputting the data of the serial third reading side holding means to said first multiplier as the coefficient of the coefficient holding means.

With such a configuration, the first to the third
When the data is read from the respective storage means, the first
The read data is held by the third reading-side holding means. Next, the first multiplier multiplies one of the coefficients of the coefficient holding means by the data of the first reading-side holding means, and the second multiplier multiplies one of the coefficients of the coefficient holding means by the second multiplier. Is multiplied by the data of the reading-side holding means, and any of the coefficients of the coefficient holding means is multiplied by the third multiplier by the data of the third reading-side holding means. Next, the operation results of the first to third multipliers are added by the adder, and the data path is switched to the data path connecting the first writing side holding means and the adder by the path switching means, The addition result of the adder is held in the first writing side holding means.

Multiplication and addition are performed in the same manner as described above, and the data path is switched by the path switching means to the data path connecting the second write-side holding means and the adder. The result is held in the second writing side holding means. Further, multiplication and addition are performed in the same manner, and the data path is switched by the path switching means to a data path connecting the third writing side holding means and the adder.
The addition result of the adder is held in the third writing side holding means.

Then, the data held by the first to third writing side holding means are written into the first to third storage means, respectively.

On the other hand, the first data output means
The data of the reading side holding means and the data of the second reading side holding means are combined to form the first reading side holding means as data of the first reading side holding means.
When the data of the third reading-side holding unit is output to the first multiplier as a coefficient of the coefficient holding unit by the second data output unit, the first multiplier The data read from the third storage means is multiplied by the data obtained by combining the data read from the first and second storage means.

As an operation of the invention of claim 13, as described above, the addition by the adder may be performed after the completion of the multiplication by the first to third multipliers. The present invention is not limited to this, and the multiplication by the first to third multipliers and the addition by the adder may be performed in parallel. For example, when calculating “11 × 14 + 15 × 13”, according to the former operation, “11 × 14 = 154” and “15”
The calculation result is obtained by calculating “154 + 195” after calculating “× 13 = 195”. According to the latter operation, “11 × 14 = 44 [11 × 4] +110”
[11 × 10] ”and“ 15 × 13 = 45 [15 ×
3] +150 [15 × 10] ”and then“ 44+
The calculation result is obtained by calculating “110 + 45 + 150”.

[0046]

Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1 to 6 are diagrams showing an embodiment of an arithmetic assist circuit according to the present invention.

In the present embodiment, the arithmetic assist circuit according to the present invention is implemented by software and hardware using a DCT.
This is applied to a case where image data is compressed or decompressed by an encoding method according to. Specifically, as shown in FIG. 1, when compressing image data, the YUV conversion unit 10, the quantization operation unit 16, and the zigzag scan unit 18 are realized by an operation auxiliary circuit 50 as hardware. Are realized by processing by the CPU 40 as software. When decompressing image data, the reverse zigzag scanning unit 24,
The inverse quantization operation unit 26 and the RGB conversion unit 32 are realized by the operation auxiliary circuit 50, and are realized by the other processing units 22, 28, and 30.

First, the configuration of an image processing system to which the present invention is applied will be described with reference to FIG. FIG. 1 is a block diagram illustrating a configuration of an image processing system to which the present invention has been applied.

In FIG. 1, a bus 49 has a CP for controlling arithmetic operations and the entire system based on a control program.
U40, an external image memory 44 for storing image data and calculation results required in the calculation process of the CPU 40,
An arithmetic assist circuit 50 for assisting the processing of U40 is connected. Here, the arithmetic auxiliary circuit 50 corresponds to the arithmetic auxiliary circuit according to the present invention.

The arithmetic assist circuit 50 includes an internal arithmetic circuit 52
And three buffers 54, 56, and 58 having a memory capacity capable of storing image data of 8 × 8 pixels and accessible by both the CPU 40 and the internal arithmetic circuit 52;
A register 60 for storing an instruction from U40 and a coefficient necessary for the operation of internal operation circuit 52, and an address converter for converting a read address or a write address when CPU 40 reads or writes from / to buffers 54 to 58. And a calculation trigger generation circuit 64 that generates a calculation trigger based on the write address while monitoring the write address of the CPU 40.

The register 60 temporarily stores the instruction given from the CPU 40 so that the internal arithmetic circuit 52 and the address converter 62 refer to the instruction from the CPU 40. The commands from the CPU 40 include a YUV conversion command indicating that the YUV conversion is performed, a quantization operation command indicating that the quantization operation is performed, a zigzag scan command indicating that the zigzag scan is performed, and an inverse zigzag scan. There is an inverse zigzag scan instruction indicating that the above operation is performed, an inverse quantization operation instruction indicating that the inverse quantization operation is performed, and an RGB conversion instruction indicating that the RGB conversion is performed. Among them, the zigzag scan instruction and the reverse zigzag scan instruction are referred to by the address converter 62, and the other instructions are referred to by the internal arithmetic circuit 52.

The register 60 includes the internal arithmetic circuit 5.
2 stores coefficients required when performing YUV conversion or RGB conversion. YUV conversion is based on the R
The dye data of the component, the G component, and the B component are respectively represented by R,
Assuming that G and B are used, and Y, U and V are the dye data of the Y component, U component and V component constituting the pixel, respectively, the following equations (1) to (3) are used. Also, RGB
The conversion is performed by the following equations (4) to (6). That is, in the following equation (1) to (3), the coefficient k _yr multiplying R, G, and _{B, k yg, k yb,} k ur, k ug, k ub,
k _vr , k _vg , and k _vb are represented by the following equations (4) to (6):
Coefficients k _ry , k _ru , k _rv , which multiply Y, U and V,
k _gy , k _gu , k _gv , k _by , k _bu , and k _bv are stored in the register 60. Each of these coefficients is composed of 8-bit data. When the CPU 40 outputs a YUV conversion command or an RGB conversion command,
May be stored, or may be stored in advance.

Y = _kyr × R + _kyg × G + _kyb × B (1) U = _kur × R + _kug × G + _kub × B (2) V = _kvr × R + _kvg × G + k _{vb × B ... (3) R} = k ry × Y + k ru × U + k rv × V ... (4) G = k gy × Y + k gu × U + k gv × V ... (5) B = k by × Y + k _bu × U + _kbv × V (6) Next, the configuration of the internal arithmetic circuit 52 will be described in detail with reference to FIG. FIG. 2 is a block diagram showing a configuration of the internal operation circuit 52.

The internal operation circuit 52, as shown in FIG.
Three read-side latch circuits 100, 102, and 1 for latching data read from the buffers 54 to 58, respectively.
04 and three write-side latch circuits 106 and 10 for latching the operation results to be written into the buffers 54 to 58, respectively.
8 and 110 and switches 112 and 1 for determining coefficients to be multiplied by the data of the read-side latch circuits 100 to 102, respectively.
14, a multiplier 118 for multiplying the data of the read-side latch circuit 100 by the output coefficient of the switch 112; a multiplier 120 for multiplying the data of the read-side latch circuit 102 by the output coefficient of the switch 114; Multiplier 12 for multiplying the data of side latch circuit 104 by the output coefficient of switch 116
2 are provided. Further, multipliers 118 to
An adder 124 for adding the multiplication result of 122, a switch 126 for switching the data path connecting the write-side latch circuits 106 to 110 to the adder 124, and data of the read-side latch circuits 100 and 102 are combined. And a switch 130 for outputting the data of the read-side latch circuit 104 to the multiplier 118 as an output coefficient of the switch 112. It is configured.

Each of the read-side latch circuits 100 to 104 and the write-side latch circuits 106 to 110 latches 8-bit data under the control of a control circuit (not shown).

The switch 112 selectively switches and outputs coefficients k _yr , k _ur , k _vr , k _ry , k _gy , and k _by of the register 60. That is, when performing YUV conversion, a coefficient k _yr is calculated when Y is calculated, a coefficient k _ur is calculated when U is calculated, and a coefficient k _vr is calculated when V is calculated. When performing RGB conversion, the coefficient k _ry when calculating the R, the coefficient k _gy when calculating the G, when calculating the B outputs the coefficient k _By.

The switch 114 selectively switches and outputs the coefficients k _yg , k _ug , k _vg , k _ru , k _gu , and k _bu of the register 60. That is, when performing YUV conversion, the coefficient k _yg when calculating the Y, the coefficient k _ug when calculating the U, when calculating V outputs the coefficient k _vg. When performing RGB conversion, a coefficient k _ru is output when calculating R, a coefficient k _gu is output when calculating G, and a coefficient k _bu is output when calculating B.

The switch 116 selectively switches and outputs the coefficients k _yb , k _ub , k _vb , k _rv , k _gv , and k _bv of the register 60. That is, when performing YUV conversion, the coefficient k _yb is output when Y is calculated, the coefficient k _ub is calculated when U is calculated, and the coefficient k _vb is output when V is calculated. When RGB conversion is performed, the coefficient k _rv is output when calculating R, the coefficient k _gv is output when calculating G, and the coefficient k _bv is output when calculating B.

The multiplier 118 is connected to the read-side latch circuit 100
The number of input bits on the switch side is 16 bits, and the number of input bits on the switch 112 side is 8 bits. Multiplication of 16 bits and 8 bits is performed, and 24-bit data as a result of the multiplication is output to the adder 124. It is supposed to.

The multiplier 120 is connected to the read-side latch circuit 102
The number of input bits on the input side is 8 bits, and the number of input bits on the switch 114 side is 8 bits. Multiplication of 8 bits and 8 bits is performed, and 16-bit data as a result of the multiplication is output to the adder 124. It is supposed to.

The multiplier 122 is connected to the read-side latch circuit 104
The number of input bits on the side is 8 bits, and the number of input bits on the switch 116 side is 8 bits. Multiplication of 8 bits and 8 bits is performed, and the 16-bit data resulting from the multiplication is output to the adder 124. It is supposed to.

The adder 124 outputs the 16
Bit data, the 16-bit data from the multiplier 120, and the 16-bit data from the multiplier 122, and according to a given instruction, 16-bit data of the addition result data is The data is output to the switch 126. Specifically, the adder 124 and the switch 1
26, the addition result is shifted by a predetermined bit in accordance with a given instruction by a shift register (not shown), and outputs, for example, lower 16-bit data of the shift register to the switch 126.

The switch 126 is used for YUV conversion or RGB.
When performing the conversion, the lower 8 bits of the 16-bit data from the adder 124 are selectively output to any of the write-side latch circuits 106 to 110. When performing the quantization operation or the inverse quantization operation, the upper 8 bits of the 16-bit data from the adder 124 are output to the write-side latch circuit 106, and the lower 8 bits are written. Side latch circuit 10
8 is output.

The switch 128 has two switching states,
In the first switching state, the data of the read-side latch circuit 100 is set to lower 8-bit data, the upper 8-bit data is set to 0, and they are combined to generate 16-bit data, which is output to the multiplier 118. It has become. Also,
In the second switching state, the data of the read-side latch circuit 100 is changed to upper 8-bit data,
Are combined as low-order 8-bit data to generate 16-bit data, which is output to the multiplier 118.

The switch 130 has two switch states,
In the first switching state, the output coefficient from the switching unit 112 is output to the multiplier 118, and in the second switching state, the data of the read-side latch circuit 104 is output to the multiplier 11.
8 is output.

When a YUV conversion instruction is given, the internal operation circuit 52 operates in units of six states as shown in FIG. FIG. 3 shows YUV
FIG. 3 is a diagram illustrating each state of an internal operation circuit 52 when converting. Since the RGB conversion is performed in the same manner as the YUV conversion, here, only the YUV conversion will be described, and the description of the RGB conversion will be omitted.

Each state is, as shown in FIG. 3, a reading state (State 0) for reading RGB component dye data (hereinafter simply referred to as RGB data) from the buffers 54 to 58 to the reading-side latch circuits 100 to 104, respectively. ,
A Y-component calculation state (State1) for calculating Y-component dye data based on the RGB data of the read-side latch circuits 100 to 104;
U for calculating U component dye data based on GB data
Component calculation state (State 2) and read-side latch circuit 1
A V component calculation state (State 3) for calculating the V component dye data based on the RGB data of 00 to 104, and the YUV component dye data (hereinafter simply referred to as YUV data) of the write-side latch circuits 106 to 110. Buffer 54
And the RGB data to be read in the next read state are stored in the buffer 5.
Waiting state (St
ate6).

Hereinafter, the dye data of the R component, the dye data of the G component, the dye data of the B component, the dye data of the Y component, the dye data of the U component, and the dye data of the V component are simply referred to as R data, G data, B data, Y data,
They are called U data and V data. Further, if each of these combinations is a combination of R data and G data, it may be referred to as RG data.

In the read state, each of the buffers 54 to 58
From the same address, and reads the data read from the buffer 54 into the read-side latch circuit 100.
The data read from the buffer 56 is output to the read-side latch circuit 102, and the data read from the buffer 58 is output to the read-side latch circuit 102. Thus, the CPU 40 stores the R data in the buffer 54 and the G data in the buffer 5 out of the image data of 8 × 8 pixels.
6, when the B data is written to the buffer 58, in the first read state, of the 8 × 8 pixel data, the image data located at the upper left on the display screen, and the R data thereof is the read side latch circuit 100. The G data is stored in the read-side latch circuit 102, and the B data is stored in the read-side latch circuit 1.
04 is latched. That is, by repeating the read state 64 times, the RGB data in the buffers 54 to 58 is read into the read-side latch circuits 100 to 104 one by one.

In the Y component calculation state, the switches 112 to
116, the coefficients k _yr , _kyg , and _kyb are selected, the R data of the read-side latch circuit 100 and the output coefficient k _yr from the switch 112 are multiplied by a multiplier 118, and the read-side latch circuit 102 G data and output coefficient k from switch 114
_yg is multiplied by a multiplier 120 and the read-side latch circuit 104
, And the output coefficient k _yb from the switch 116 is multiplied by the multiplier 122, the multiplication result is added by the adder 124, the switch 126 is switched, and the data from the adder 124 is written as Y data. The latch circuit 106 latches the data.

In the U component calculation state, the switches 112 to
116, the coefficients k _ur , k _ug , and k _ub are selected, the R data of the read-side latch circuit 100 and the output coefficient k _ur from the switch 112 are multiplied by a multiplier 118, and the read-side latch circuit 102 G data and output coefficient k from switch 114
_ug is multiplied by the multiplier 120 and the read-side latch circuit 104
, And the output coefficient k _ub from the switch 116 is multiplied by the multiplier 122, the multiplication result is added by the adder 124, the switch 126 is switched, and the data from the adder 124 is written as U data. The latch circuit 108 latches.

In the V component calculation state, the switches 112 to
116, the coefficients k _vr , k _vg , and k _vb are selected, and the R data of the read-side latch circuit 100 and the output coefficient k _vr from the switch 112 are multiplied by a multiplier 118. G data and output coefficient k from switch 114
_vg is multiplied by a multiplier 120 and the read-side latch circuit 104
_Is multiplied by the output coefficient k _vb from the switch 116 by the multiplier 122, the multiplication result is added by the adder 124, the switch 126 is switched, and the data from the adder 124 is written as V data. The latch circuit 110 latches the data.

In the write state, write-side latch circuit 10
6 to the buffer 54 and the write-side latch circuit 10
8 into the buffer 56 and the write-side latch circuit 11
The V data of 0 is written in the buffer 58. Here, the write address is the same address as the read address specified in the read state. In the write state, when the CPU 40 is accessing or starting to access the buffers 54 to 58, the data is written after the access by the CPU 40 is completed. Te

In the standby state, when the RGB data to be read in the next read state has not been written to the buffers 54 to 58, the process waits until the writing is completed. Also, the CPU 40
When an access is being made or an attempt is being made to start access to ５８58, the CPU 40 waits until the access by the CPU 40 ends. In addition,
Whether or not the RGB data to be read in the next read state has been written to the buffers 54 to 58 depends on the value of the CPU operation counter that is incremented each time a calculation trigger from the calculation trigger generation circuit 64 is input, and The determination is made by comparing the value of the internal operation circuit operation counter that is incremented after the end of the write state. That is, when it is determined that the value of the CPU operation counter is larger than the value of the internal operation circuit operation counter, the RGB data to be read in the next read state is stored in the buffers 54-5.
8 is written, and the standby is released.

The internal operation circuit 52 operates on the basis of the operation clock of the bus 49, and performs the read state, the Y-component calculation state, the U-component calculation state, and the V-component calculation state in one clock. . If the standby condition is not satisfied, the write state and the standby state are performed in one clock. However, it is determined whether or not the standby condition is satisfied, every clock, and it is determined that the standby condition is satisfied. Then, it waits for one clock. Thereby, the CP
In parallel with the writing operation by the U40 to the buffers 54 to 58, the CPU 4
Each state is performed independently of 0.

When a quantization operation command is given, the internal operation circuit 52 operates in units of four states as shown in FIG. FIG. 4 is a diagram showing each state of the internal operation circuit 52 when performing a quantization operation. Since the inverse quantization operation is performed in the same manner as the quantization operation, here, only the quantization operation will be described, and the description of the inverse quantization operation will be omitted.

Each state is, as shown in FIG. 4, a read state (State 0) for reading data from the buffers 54 to 58 to the read-side latch circuits 100 to 104, respectively.
Quantization operation state (State 4) for performing a quantization operation based on the RGB data of the read-side latch circuits 100 to 104
A write state (State 5) for writing the data of the write-side latch circuits 106 to 110 into the buffers 54 to 58;
Data to be read in the next read state is buffer 5
Waiting state (St
ate6).

In the read state, each of the buffers 54 to 58
From the same address, and reads the data read from the buffer 54 into the read-side latch circuit 100.
The data read from the buffer 56 is output to the read-side latch circuit 102, and the data read from the buffer 58 is output to the read-side latch circuit 102. Thus, when the CPU 40 performs DCT on the image data of 8 × 8 pixels, frequency component data in units of 16 bits is generated. However, the CPU 40 converts the upper 8 bits of the frequency component data obtained by performing DCT. Buffer 5
4, the lower 8 bits of data are written to the buffer 56 and the quantized coefficients are written to the buffer 58.
In the second read state, the horizontal frequency and vertical frequency of 8 × 8 pixels are the lowest frequency component data, and the data of the upper 8 bits is the read-side latch circuit 10.
0, the lower 8 bits of the data are read-side latch circuit 1
02, and the quantization coefficient to be multiplied is latched by the read-side latch circuit 104. That is, the read state is repeated by the number of divisions of the frequency in the horizontal direction and the vertical direction, so that the frequency component data of the buffers 54 and 56 is read one by one into the read-side latch circuits 100 and 10.
Read in 2.

In the quantization operation state, the switch 128 is switched to combine the data of the read-side latch circuits 100 and 102 and output to the multiplier 118, and the switch 130 is switched to switch the quantization coefficient of the read-side latch circuit 104. To the multiplier 11
8 and the multiplier 118 multiplies the frequency component data of the read-side latch circuits 100 and 102 by the quantization coefficient of the read-side latch circuit 104, and outputs the higher-order 8 bits of the 24-bit data resulting from the multiplication. The data is discarded, the upper 8 bits of the remaining 16 bits of data are latched by the write side latch circuit 106, and the lower 8 bits of data are latched by the write side latch circuit 108.

In the write state, write-side latch circuit 10
6 to the buffer 54 and the write-side latch circuit 108
Is written to the buffer 56.
Here, the write address is the same address as the read address specified in the read state. In the write state, when the CPU 40 is accessing or starting to access the buffers 54 to 58, the data is written after the access by the CPU 40 is completed. Te

In the standby state, when the frequency component data and the quantization coefficient to be read in the next reading state are not written in the buffers 54 to 58, the process waits until the writing is completed. Also, CP
When U40 is accessing or starting to access buffers 54-58,
It waits until the access by the CPU 40 is completed. The frequency component data and the quantization coefficient to be read in the next reading state are stored in the buffers 54 to 54.
Whether it is written in 58 or not is determined by comparing the value of the CPU operation counter with the value of the internal operation circuit operation counter. That is, when it is determined that the value of the CPU operation counter is larger than the value of the internal operation circuit operation counter, it is determined that the frequency component data and the quantization coefficient to be read in the next read state have been written to the buffers 54 to 58. , Release the wait.

The internal operation circuit 52 operates based on the operation clock of the bus 49, and performs both the read state and the quantization operation state in one clock. If the standby condition is not satisfied, the write state and the standby state are performed in one clock. However, it is determined whether or not the standby condition is satisfied, every clock, and it is determined that the standby condition is satisfied. Then, it waits for one clock. Accordingly, each state is performed independently of the CPU 40 while referring to the writing status of the CPU 40 in parallel with the writing operation of the buffers 40 to 58 by the CPU 40.

Next, the configuration of the address conversion circuit 62 is shown in FIG.
This will be described in detail with reference to FIG. FIG. 5 is a block diagram showing a configuration of the address conversion circuit 62.

Address conversion circuit 62, as shown in FIG. 5, converts a read address or a write address when CPU 40 reads or writes from / to buffers 54 to 58 based on an instruction of register 60. It has become.

When a YUV conversion command is given, the
As shown in (a), the write address is stored in the buffer 54,
The buffer is switched in the order of the buffer 56 and the buffer 58, and after the buffer 58, the write address is incremented by 1, and the buffer is switched again in the order of the buffer 54, the buffer 56, and the buffer 58. Thus, for example, when the CPU 40 writes data in the order of R data 0, G data 0, B data 0,..., R data 63, G data 63, and B data 63, the R data 0 to 63 Address 0-6
3, G data 0 to 63 are stored in the buffer 56
Are sequentially written to addresses 0 to 63 of B data 0 to 6
3 are sequentially written to addresses 0 to 63 of the buffer 58.

When an RGB conversion instruction is given, the write address is switched from address 0 of the buffer 54 to address 63, and then from address 0 of the buffer 56 to address 63, as shown in FIG. 63, and then from address 0 to address 63 of the buffer 58.
To switch over. Thereby, for example, Y data 0 to 63, U data 0 to 63, V data 0
When the CPU 40 performs writing in the order of
63 is sequentially written to addresses 0 to 63 of the buffer 54, and U data 0 to 63 are written to addresses 0 to 6 of the buffer 56.
3, V data 0 to 63 are stored in the buffer 58
Are sequentially written to addresses 0 to 63.

When a quantization operation instruction is given, as shown in FIG. 5 (c), in order to perform simultaneous writing to buffers 54 and 56, the write addresses to buffers 54 and 56 are changed. At the same time, one is added. Thus, for example, when the CPU 40 writes the frequency component data composed of 16-bit data, the upper 8 bits of the frequency component data are sequentially written to addresses 0 to 63 of the buffer 54, and the lower 8 bits of the frequency component data are stored in the buffer 54. The data is sequentially written to 56 addresses 0 to 63.

When a zigzag scan instruction is given, as shown in FIG.
In order to perform simultaneous writing to the buffer, write addresses to the buffers 54 and 56 are simultaneously added or subtracted according to a predetermined rule. The zigzag scan is obtained by performing a quantization operation on image data of 8 × 8 pixels.
This is a process of rearranging the frequency components in the horizontal and vertical directions in ascending order, and the rearrangement is performed in a predetermined order. Therefore, the addition or subtraction of the write address is
The increase and decrease are performed according to the predetermined order. The increase / decrease data indicating the increase / decrease is stored, for example, as a one-to-one table, and the addition or subtraction of the write address is performed with reference to the table. As a result, when the CPU 40 writes the quantized operation data composed of 16-bit data, the upper 8 bits of the quantized operation data are rearranged in addresses 0 to 63 of the buffer 54 in a predetermined order and written. The lower 8 bits of data are rearranged and written in addresses 0 to 63 of the buffer 56 in a predetermined order.

Next, the operation of the above embodiment will be described.

First, the operation in the case where image data is compressed by the DCT coding method will be described.

When compressing image data by the DCT coding method, the outline will be described first.
At 40, the YUV conversion command is written into the register 60, and the RGB data, which is the original image data stored in the external image memory 44, is written into the buffers 54 to 58, and the arithmetic auxiliary circuit 50 performs YUV conversion.

When the YUV conversion is completed, the CPU 40 reads the YUV data from the buffers 54 to 58 into the external image memory 44, and the external image memory 44 performs the thinning process and the DCT process in that order. DCT
When the processing is completed, the CPU 40 writes the quantization operation instruction into the register 60 and stores the frequency component data stored in the external image memory 44 into the buffer 5.
4, 56, and then the quantized coefficients are stored in buffer 5
8 and a quantization operation is performed by the operation auxiliary circuit 50.

When the quantization operation is completed, the CPU 40 reads the quantization operation data from the buffers 54 and 56 into the external image memory 44. Next, the CPU 40 writes the zigzag scan instruction into the register 60 and the quantization operation data stored in the external image memory 44 into the buffers 54 and 56, and the operation auxiliary circuit 50 performs the zigzag scan. When the zigzag scan is completed, the zigzag scanned data is read from the buffers 54 and 56 into the external image memory 44 by the CPU 40, and the external image memory 44 performs a variable length encoding process. Through this series of processing, the original image data is compressed, and compressed image data having a smaller data volume than the original image data is generated.

In the arithmetic assist circuit 50, when a YUV conversion instruction is given, the write address is converted by the address converter 62 into the buffers 54, 56 and 58.
, The write address is incremented by 1 after the buffer 58, and the buffer 54, the buffer 56, and the buffer 58 are switched again. Therefore, R
Data 0, G data 0, B data 0, ..., R data 6
3, when the CPU 40 writes in the order of the G data 63 and the B data 63, the R data 0 to 63 are sequentially written to the addresses 0 to 63 of the buffer 54, and the G data 0 to 63 are written to the addresses 0 to 63 of the buffer 56. The B data 0 to 63 are sequentially written to addresses 0 to 63 of the buffer 58.

On the other hand, when R data 0 is written in the buffer 54, G data 0 is written in the buffer 56, and B data 0 is written in the buffer 58, an operation trigger generation circuit 64 generates an operation trigger. When an operation trigger is input, the internal operation circuit 52 goes through a read state, a Y-component calculation state, a U-component calculation state, a V-component calculation state, a write state, and a standby state, and outputs RGB data 0.
Is converted to YUV data 0. At this time, the specific timing will be described in detail in the later stage of RGB conversion, but the read state, the Y component calculation state, the U component calculation state, the V component calculation state, the write state, and the standby state are stored in the buffer 54 by the CPU 40. In parallel with the writing operation to # 58, the writing is performed while referring to the writing status of the CPU 40.

In the read state, each of the buffers 54 to 58
, RGB data 0 is read from the start address of each of the data, and R data 0 read from the buffer 54 is read into the read-side latch circuit 100 by the G read from the buffer 56.
Data 0 is output to the read-side latch circuit 102, and B data 0 read from the buffer 58 is output to the read-side latch circuit 102 and latched.

In the Y component calculation state, the multiplier 118 multiplies the R data 0 by the coefficient k _yr ,
0 multiplies the G data 0 by the coefficient _kyg, and the multiplier 122 multiplies the B data 0 by the coefficient _kyb .
The multiplication results are added by the adder 124, and the data from the adder 124 is latched as Y data 0 by the write-side latch circuit 106.

In the U component calculation state, the multiplier 118 multiplies the R data 0 by the coefficient k _ur ,
0 multiplies the G data 0 by the coefficient k _ug, and the multiplier 122 multiplies the B data 0 by the coefficient k _ub .
These multiplication results are added by the adder 124, and the data from the adder 124 is latched as U data 0 by the write-side latch circuit 108.

In the V component calculation state, the multiplier 118 multiplies the R data 0 by the coefficient _kvr, and
0 multiplies the G data 0 by the coefficient k _vg, and the multiplier 122 multiplies the B data 0 by the coefficient k _vb .
The multiplication results are added by the adder 124, and the data from the adder 124 is latched as V data 0 by the write-side latch circuit 110.

In the write state, write-side latch circuit 10
6 is stored in the buffer 54 and the write-side latch circuit 1
08 U data 0 is written to the buffer 56, and V data 0 of the write side latch circuit 110 is written to the buffer 58. However, when the CPU 40 is accessing or starting to access the buffers 54 to 58, data writing is performed after the access by the CPU 40 is completed.

In the standby state, the process waits until the next operation trigger is input, that is, until the RGB data 1 to be read in the next read state is written to the buffers 54 to 58. In addition, the CPU 40
If the CPU 58 is accessing or starting to access, it waits until the access by the CPU 40 ends.

As described above, in the arithmetic auxiliary circuit 50, all of the RGB data, which is image data of 8.times.8 pixels, is converted into YUV data by repeatedly executing these six states. After the B data 63, which is the last data constituting the 8 × 8 pixel, is written into the buffer 58, the conversion is performed for five clocks of the operation clock of the bus 49 (read state, Y component calculation state, U component calculation state). , V component calculation state and writing state)).

Next, in the arithmetic assist circuit 50, when a quantization operation instruction is given, the address converter 62 writes write addresses to the buffers 54 and 56 in order to perform simultaneous writing to the buffers 54 and 56. One is added at a time. Therefore, when the CPU 40 writes the frequency component data composed of 16-bit data, the upper 8 bits of the frequency component data are sequentially written to the addresses 0 to 63 of the buffer 54 and the lower 8 bits of the frequency component data are stored in the address of the buffer 56. Data is written in order from 0 to 63. Thereafter, the quantized coefficients k _{q0 to} k _q63 are sequentially written to addresses 0 to 63 of the buffer 58.

On the other hand, when the upper bit data 0 of the first frequency component data is written to the buffer 54, the lower bit data 0 is written to the buffer 56, and the quantization coefficient k _q0 to be multiplied to the buffer 58 is written to the buffer 58, The generation circuit 64 generates an operation trigger. When an operation trigger is input, the internal operation circuit 52 performs a quantization operation on the frequency component data through a read state, a quantization operation state, a write state, and a standby state. At this time, the specific timing will be described in detail in the later stage of RGB conversion, but the read state, the quantization operation state, the write state, and the standby state
In parallel with the write operation to the buffers 54 to 58 by 0,
This is performed while referring to the writing status by the CPU 40.

In the read state, each of the buffers 54 to 58
, The frequency component data 0 and the quantization coefficient k _q0 are read from the head address of the read-side latch circuit 100, respectively.
The lower bit data 0 read from the buffer 56
Is output to the read-side latch circuit 102, and the quantization coefficient k _q0 read from the buffer 58 is output to the read-side latch circuit 102 and latched.

In the quantization operation state, the data of the read-side latch circuits 100 and 102 are combined by the switch 128 and output to the multiplier 118.
The quantization coefficient k _q0 of the read-side latch circuit 104 is
8 and the multiplier 118 multiplies the frequency component data 0 by the quantization coefficient k _q0 . The result of the multiplication is
The upper 8 bits of the 24-bit data are truncated, the upper 8 bits of the remaining 16-bit data are latched by the write-side latch circuit 106, and the lower 8 bits of the data are written to the write-side latch circuit. Latched at 108.

In the write state, of the quantized operation data, upper bit data 0 of the write side latch circuit 106 is written to the buffer 54 and lower bit data 0 of the write side latch circuit 108 is written to the buffer 56. However, CPU4
0 is accessing or starting to access buffers 54-58,
Data writing is performed after the access by U40 is completed.

[0108] In the standby state until the trigger for the next operation is input, i.e., the frequency component data 1 and the quantized coefficient k _q1 scheduled to read in the next read state to wait until they are written into the buffer 54-58. Also, C
When the PU 40 is accessing or starting to access the buffers 54 to 58, the process waits until the access by the CPU 40 ends.

As described above, in the arithmetic assist circuit 50, by repeatedly executing these four states, all the frequency component data of the image data of 8 × 8 pixels are quantized. In the conversion, after the quantization coefficient for multiplying the last data constituting the frequency component data is written in the buffer 58, the operation clock of the bus 49 is equivalent to three clocks (the read state, the quantization operation state, and the write state). Completion is delayed by the required clock).

Next, in the arithmetic auxiliary circuit 50, when a zigzag scan instruction is applied, the address converter 62 simultaneously writes data into the buffers 54 and 56 in order to perform simultaneous writing into the buffers 54 and 56. It is added or subtracted according to a predetermined rule.

Next, the operation in the case of decompressing the compressed image data by the DCT coding method will be described.

When decompression of compressed image data is performed by an encoding method based on DCT, the outline thereof will be described first.
The PU 40 performs a variable length decoding process in the external image memory 44, writes an inverse zigzag scan instruction to the register 60, and writes the decoded data stored in the external image memory 44 to the buffers 54 and 56, and performs an operation. The auxiliary circuit 50 performs an inverse zigzag scan.

When the reverse zigzag scan is completed, the CPU
At step 40, the quantization operation data is read from the buffers 54 and 56 to the external image memory 44. Then, CPU
At 40, the inverse quantization operation instruction is written into the register 60, and the quantization operation data stored in the external image memory 44 is written into the buffers 54 and 56. Thereafter, the inverse quantization coefficient is written into the buffer 58 and the operation is performed. The auxiliary circuit 50 performs an inverse quantization operation.

When the inverse quantization operation is completed, the CPU 40 reads the frequency component data from the buffers 54 and 56 into the external image memory 44, and the external image memory 44 performs the IDCT process and the interpolation process in that order.
When the interpolation process is completed, the CPU 40 writes the RGB conversion command into the register 60 and stores the YUV data stored in the external image memory 44 into the buffer 54.
To 58, and RGB by the arithmetic assist circuit 50
Conversion is performed.

When the RGB conversion is completed, the CPU 40 stores the RGB data as the original image data in the buffers 54 to 54.
From 58, it is read into the external image memory 44. Through such a series of processes, the compressed image data is decompressed, and the original original image data is restored.

Next, the operation when the RGB conversion is performed will be described in detail with reference to FIG. FIG. 6 is a time chart for explaining the RGB conversion performed by the arithmetic auxiliary circuit 50. In the following description, the time t _n is indicated by a larger value as time elapses.

In FIG. 6, “CLK” indicates a clock signal on the bus 49, “L_EXT_ID” indicates a data signal output from the CPU 40 to the bus 49, and “L_EXT_WR” indicates a C signal.
The write enable signal from the PU 40 is indicated by “S_TRG_
"EDGE" indicates an operation trigger signal of the operation trigger generation circuit 64, and "L_EXT_ADR [5: 0]" indicates a data signal of the CPU operation counter. In addition, "L_INT_ADR [5:
0] ”indicates a data signal of the internal operation circuit operation counter,“ O_STATE [2: 0] ”indicates a state signal indicating the state of the internal operation circuit 52, and“ S_INT_WR ”indicates a signal from the internal operation circuit 52. 2 shows a write enable signal.
Also, “L_MTRX_DA”, “L_MTRX_DB” and “L_MTRX_D
"C" indicates a data signal latched by each of the read-side latch circuits 100 to 104, and "O_MTRX_DA [7:
0], O_MTRX_DB [7: 0] and O_MTRX_DC [7:
[0] "indicates data signals latched by the write-side latch circuits 106 to 110, respectively.

In the arithmetic auxiliary circuit 50, when an RGB conversion instruction is given, the write address is switched by the address converter 62 from address 0 to address 63 of the buffer 54, and then from address 0 to address 63 of the buffer 56. , And then from address 0 to address 63 of the buffer 58. Therefore, Y data 0 to 63, U data 0 to 63, V data 0
When the CPU 40 performs writing in the order of
63 is sequentially written to addresses 0 to 63 of the buffer 54, and U data 0 to 63 are written to addresses 0 to 6 of the buffer 56.
3, V data 0 to 63 are stored in the buffer 58
Are sequentially written to addresses 0 to 63.

On the other hand, in a state in which Y data 0 is written in the buffer 54 and U data 0 is written in the buffer 56, as shown in FIG. 6, the CPU 40 outputs V data 0 to the bus 49, and at time t ₀ When the write enable signal goes low, the V data 0 is written to the buffer 58 between times t _{0 and} t ₁ when the write enable signal goes low. Then, Y is stored in the buffer 54.
Data 0, U data 0 in buffer 56, buffer 5
When the V data 0 is written to 8, at time t ₂
An operation trigger is generated by the operation trigger generation circuit 64, and the operation trigger signal becomes high level.

In the internal arithmetic circuit 52, an arithmetic trigger is input.
At the time t_ThreeRead state at (State 0)
In the read state, the read status in the YUV conversion
The data is read in the same manner as the Tate. Data
When reading is completed, time t _FourAt the read-side latch
The YUV data 0 is latched in the
Minute calculation state (State1), and the R component calculation state
Same as the Y component calculation state in YUV conversion
The calculation of the R data 0 is performed in the same manner.

Next, when the calculation of the R data 0 is completed,
At time t ₅ , the R data 0 is latched by the write-side latch circuit 106 to enter the G component calculation state (State 2). In the G component calculation state, the G data 0 is calculated in the same manner as the U component calculation state in the YUV conversion. Is performed. When the calculation of the G data 0 is completed, at time t ₆ , the G data 0 is latched by the write-side latch circuit 108 to enter the B component calculation state (State 3). In the B component calculation state, the V component calculation state in the YUV conversion is performed. Calculation of B data 0 is performed in the same manner as described above.

Next, when the calculation of the B data 0 is completed,
At time t ₇ , B data 0 is latched by write-side latch circuit 110, and the write state (State 5) is set. The write state, but the write enable signal goes low at time t _8, since the write enable signal from the CPU40 at the same time is at a high level, the write latch circuit at time t ₉ 106 - 110
RGB data 0 is written to the buffers 54 to 58.

[0123] When writing of data is completed, the waiting state (STATE 6) next to the time t _10, in the standby state, since the write enable signal from the CPU 40 at time t ₁₁ is at low level, CPU 40 is in a write And waits for one clock. Then
1 in the clock elapsed time t ₁₂ was, because the value of the CPU clock counter is equal to or less than the value of the internal computation circuit operation counter, the YUV data 1 are to be loaded at the next reading state is not written in the buffer 54 to 58 Judge and wait for one more clock. Then, at time t ₁₃ which has passed one clock is at a high level write enable signal from the CPU 40, and, CPU
Since the value of the operation counter is larger than the value of the internal operation circuit operation counter, the standby is terminated.

[0124] When the standby is completed, the next read state (State0) next at time t _14, the read state, read of data is performed in the same way as reading state in YUV conversion. When the data reading is completed,
At time t _15, YUV data 1 are latched in read latch circuit 100 to 104, R component calculation state (St
ate1), and in the R component calculation state, the R data 1 is calculated in the same manner as in the Y component calculation state in the YUV conversion.

Next, when the calculation of the R data 1 is completed,
At time t ₁₆ , the R data 1 is latched by the write-side latch circuit 106 to enter the G component calculation state (State 2). In the G component calculation state, the G data 1 is calculated in the same manner as the U component calculation state in the YUV conversion. Is performed. When the calculation of the G data 1 is completed, at time t _17, G data 1 are latched in the write latch circuit 108, the B component calculated state (State3) becomes, the B component calculation state, V component calculating state in YUV conversion B data 1 is calculated in the same manner as described above.

Next, when the calculation of the B data 1 is completed,
At time t _18, B data 1 to the write latch circuit 110 is latched, the write state (State5). The write state, but the write enable signal goes low at time t _19, write enable signal from the CPU 40 at the same time becomes the low level at time t ₂₀ CPU 40 is determined to be in writing 1
Wait for the clock. Then, at time t ₂₁ which has passed one clock, since the write enable signal from the CPU40 is at high level, the write latch circuit 1
The RGB data 1 of 06 to 110 is written to the buffers 54 to 58.

[0127] When writing of data is completed, the waiting state (STATE 6) at time t ₂₂ becomes, in the standby state, at time t _23, has a high level write enable signal from the CPU 40, and, CPU clock counter Is larger than the value of the internal operation circuit operation counter, the standby is terminated.

[0128] Then, the wait is completed, the next of the read state (State0) at time t _24.

As described above, in the arithmetic auxiliary circuit 50, by repeatedly executing these six states, all the YUV data, which is image data of 8 × 8 pixels, is converted into RGB data. After the V data 63, which is the last data constituting the 8 × 8 pixel, is written into the buffer 58, the conversion is performed by five operation clocks of the bus 49 (read state, R component calculation state, G component calculation state). , B component calculation state and write state)).

Note that the operation auxiliary circuit 50 operates in the same manner as the zigzag scan and the quantization operation for the inverse zigzag scan and the inverse quantization operation.
Detailed description is omitted.

As described above, in the present embodiment, the arithmetic auxiliary circuit 50 includes the internal arithmetic circuit 52 and the buffer 5 that can be accessed by both the CPU 40 and the internal arithmetic circuit 52.
4 to 58, and the internal arithmetic circuit 52, when given any one of the YUV conversion instruction, the RGB conversion instruction, the quantization operation instruction, and the inverse quantization operation instruction,
To 58, each of which performs an operation including a common operation common to the above-described operation methods based on the plurality of read data, and writes the operation results to different buffers.

As a result, processes having a part of operations such as YUV conversion, RGB conversion, quantization operation and inverse quantization operation can be executed by one internal operation circuit 52. However, there is no problem that the cost is increased, the manufacturing time is increased, and the circuit scale is increased. Therefore, while realizing high-speed operation by hardware as compared with the related art, it is relatively advantageous in terms of cost and manufacturing time, and it is possible to reduce the circuit scale to some extent. In addition, since the software can obtain each operation result only through a procedure of outputting an instruction to the operation auxiliary circuit 50, writing data to the memory, and reading data from the memory, the software design can be compared. It becomes easy.

Further, in the present embodiment, the internal arithmetic circuit 52 performs each state while referring to the writing status of the CPU 40 in parallel with the writing operation of the CPU 40 to the buffers 54 to 58.

As a result, since the calculation is performed while the CPU 40 is performing the writing, the calculation is completed almost at the same time when the CPU 40 completes the writing. As a result, the state in which the hardware waits until the transfer by the software processing is completely completed as in the related art is eliminated,
The waiting time is shortened, and the calculation speed can be improved to some extent as compared with the related art.

Further, in the present embodiment, the operation of the internal arithmetic circuit 52 includes a read state for performing a read, an arithmetic state for performing an operation, a write state for performing a write, and a standby state for performing a standby. , In the write state, C
When the PU 40 is accessing or starting to access the buffers 54 to 58, the writing is performed after the access by the CPU 40 is completed. Data to be read in the read state is stored in buffers 54 to 5
When the data has not been written to the memory 8, the system waits until the writing is completed.

As a result, the software does not need to particularly consider the data write timing, so that the software design is further facilitated.

Further, in the present embodiment, the internal operation circuit 52 writes the operation result to the addresses of the buffers 54 to 58 from which the data on which the operation is based has been read.

As a result, it is not necessary to provide a special area for storing the operation results in the buffers 54 to 58, so that the memories of the buffers 54 to 58 can be used efficiently.

Further, in the present embodiment, when a zigzag scan instruction is given, address converter 62 sets a write address when CPU 40 writes to buffers 54 to 58 according to a predetermined rule. It is designed to convert.

Thus, the zigzag scan process can be executed by simply adding a simple process to the address converter 62 without performing a complicated rearrangement process. Therefore, the speed of the arithmetic processing can be further increased with a simple configuration.

In the above embodiment, the CPU 40
The internal arithmetic circuit 52 corresponds to the external arithmetic means according to claims 1 to 6, 9, 10, or 12.
Buffers 54 to 58 corresponding to the internal arithmetic means
Corresponds to the storage unit according to claims 1 to 5, the buffer 54 corresponds to the first storage unit according to claims 6 to 13, and the buffer 56 corresponds to the second storage unit according to claims 6 to 13. The buffer 58 corresponds to the third storage means. The address translator 62 corresponds to the address translator described in claim 12, and includes a Y component calculation state, a U component calculation state, a V component calculation state, an R component calculation state, a G component calculation state, a B component calculation state, and The quantization operation state corresponds to the operation state described in claim 10.

The read-side latch circuits 100 to 104
Corresponds to the first to third reading-side holding means in claim 13, and the write-side latch circuits 106 to 110 correspond to claim 1.
The register 60 corresponds to the first to third writing-side holding means according to claim 3, and the register 60 corresponds to the coefficient holding means according to claim 13,
The multipliers 118 to 122 correspond to the first to third multipliers according to claim 13, the switch 126 corresponds to the path switching means according to claim 13, and the switches 128 and 130 include
The present invention corresponds to the first and second data output means.

In the above embodiment, the arithmetic auxiliary circuit according to the present invention is applied to a case where image data is compressed or decompressed by a coding method using DCT by software and hardware. However, the present invention is not limited to this. The present invention can be applied to other cases without departing from the gist of the present invention. For example, the present invention can be applied to a case where audio data is compressed or decompressed.

[0144]

As described above, according to the arithmetic auxiliary circuit according to the first to thirteenth aspects of the present invention, the cost and the manufacturing time can be improved while realizing a high-speed operation by hardware as compared with the prior art. This is relatively advantageous in terms of the size, and the effect that the circuit size can be reduced to some extent is obtained. Further, on the software side, each operation result can be obtained only through a procedure of outputting an instruction to the operation auxiliary circuit according to the present invention, writing data to the storage unit, and reading data from the storage unit. The effect of relatively easy software design is also obtained.

Further, according to the arithmetic auxiliary circuit according to the second, fourth, fifth or ninth aspect of the present invention, an effect is obtained that the arithmetic speed can be improved to some extent as compared with the conventional one.

Further, according to the arithmetic auxiliary circuit according to the tenth aspect of the present invention, since the software does not need to particularly consider the data write timing, the design of the software is further facilitated. can get.

Further, according to the arithmetic auxiliary circuit according to the eleventh aspect of the present invention, it is not necessary to provide a special area for storing the operation result in the storage means, so that the memory of the storage means can be efficiently used. The effect of being able to use is also obtained.

Further, according to the arithmetic auxiliary circuit according to the twelfth aspect of the present invention, it is possible to obtain the effect that the speed of arithmetic processing can be further increased with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing system to which the present invention has been applied.

FIG. 2 is a block diagram showing a configuration of an internal operation circuit 52.

FIG. 3 is a diagram showing each state of an internal operation circuit 52 when performing YUV conversion.

FIG. 4 is a diagram showing each state of an internal operation circuit 52 when performing a quantization operation.

FIG. 5 is a block diagram showing a configuration of an address conversion circuit 62.

FIG. 6 is a time chart for explaining the RGB conversion performed by the arithmetic assist circuit 50;

FIG. 7 is a diagram illustrating processing for compressing and decompressing image data by an encoding method using DCT.

[Explanation of symbols]

 40 CPU 44 External image memory 49 Bus 50 Operation auxiliary circuit 52 Internal operation circuit 54 to 58 Buffer 60 Register 62 Address converter 64 Operation trigger generation circuit 100 to 104 Read-side latch circuit 106 to 110 Write-side latch circuit 112 to 116 Switch 118-122 Multiplier 124 Adder 126-130 Switch

Continued on the front page F term (reference) 5B056 BB11 HH03 5B057 CA08 CA12 CA16 CB08 CB12 CB16 CG05 CH01 CH11 CH12 CH14 5C059 KK12 KK50 LA00 MA23 MC01 MC11 ME01 UA02 UA05 UA29 UA38 5J064 AA03 BC04 BC16 BC04 BC16 BC04 BC

Claims (13)

[Claims] 1. A circuit for assisting an operation of an external operation means, comprising: an internal operation means; and a storage means accessible by both the external operation means and the internal operation means. Data is read from the storage unit, and based on the read data, an operation including a common operation common to the respective operation methods is performed by any one of a plurality of operation methods common to a part of the operation. And a calculation result written in the storage means. 2. A circuit for assisting an operation of an external operation means, comprising: an internal operation means; and a storage means accessible by both the external operation means and the internal operation means. Data is read from the storage means, a predetermined calculation is performed based on the read data, and the calculation result is written to the storage means. The write operation to the storage means by the external calculation means is performed in parallel. The arithmetic assisting circuit is configured to perform the reading, the arithmetic operation, and the writing while referring to a writing situation by the external arithmetic means. 3. A circuit for assisting an operation of an external operation means, comprising: an internal operation means; and a plurality of storage means accessible by both the external operation means and the internal operation means. Read data from each of the storage means, and, based on the plurality of read data, specify one of a plurality of operation methods in which a part of the operation is common, and specify a common common method among the operation methods. An operation including an operation is performed, and when the operation result is one, the operation result is written to any of the plurality of storage units. When the operation result is plural, each of the operation results is stored in a different one. An arithmetic assisting circuit characterized in that the arithmetic assisting circuit is adapted to write in the means. 4. A circuit for assisting an operation of an external operation means, comprising: an internal operation means; and a plurality of storage means accessible by both the external operation means and the internal operation means. Reads data from each of the storage means, performs a predetermined calculation based on the plurality of read data, and when the result of the calculation is one, stores the calculation result in any of the plurality of storage means. When a plurality of operation results are written, each of the operation results is written to a different storage unit. In parallel with the write operation to the storage unit by the external operation unit, the external operation unit Wherein the reading, the calculation, and the writing are performed while referring to a writing situation of the calculation assisting circuit. 5. The internal arithmetic unit according to claim 1, wherein the internal arithmetic unit refers to a writing state of the external arithmetic unit in parallel with a write operation of the external arithmetic unit to the storage unit. An arithmetic assisting circuit for performing the reading, the arithmetic operation, and the writing while performing the read operation. 6. An image data compression process of compressing image data by performing a dye conversion, a discrete cosine transform, a quantization operation, and a zigzag scan, or an image data decompression process of decompressing compressed image data through a reverse process. A circuit for assisting processing of an external arithmetic means, comprising: an internal arithmetic means; a first storage means, a second storage means, and a third storage means accessible by both the external arithmetic means and the internal arithmetic means. Wherein the internal operation means reads data from the first to third storage means, and is designated based on the plurality of read data from among a plurality of operation methods in which a part of the operation is common. By performing the operation including the common operation common to each of the operation methods, if the operation result is one, the operation result is stored in the first to third storage units. Write to or Chiizure, operation auxiliary circuit for the operation result, characterized in that when a plurality are adapted to write the result of each operation in the respective different storage means. 7. The image processing apparatus according to claim 6, wherein the internal operation unit is configured to output the first to third instructions when a dye conversion instruction indicating that the dye conversion is performed is given as an instruction for specifying the operation method. Each of the data is read from the storage means, a first multiply-accumulate operation, a second multiply-accumulate operation, and a third multiply-accumulate operation are performed based on the three read data, and the first multiply-accumulate result is calculated by The first storage means stores the second product-sum operation result in the second storage means.
The third product-sum operation result is written in the third storage means. In the first to third product-sum operations, the read three data are each multiplied by a coefficient. An arithmetic assisting circuit for adding the respective multiplication results. 8. The apparatus according to claim 6, wherein the internal operation means is provided with a quantization operation instruction indicating that the quantization operation is to be performed as an instruction specifying the operation method. Data is read from each of the first to third storage units, a predetermined operation is performed based on the read three data, and a part of the predetermined operation result is stored in the first to third storage units. In any one of the embodiments, the remaining part of the predetermined operation result is written into another storage unit, and the predetermined operation combines data read from the first and second storage units. An arithmetic assisting circuit for multiplying the obtained data by data read from the third storage means. 9. The internal arithmetic unit according to claim 6, wherein the internal arithmetic unit refers to a writing situation by the external arithmetic unit in parallel with a write operation to the storage unit by the external arithmetic unit. An arithmetic assisting circuit for performing the reading, the arithmetic operation, and the writing while performing the read operation. 10. The operation according to claim 9, wherein the operation by the internal operation means includes a read state for performing the read, an operation state for performing the operation, a write state for performing the write, and a standby state for performing standby. In the write state, when the external arithmetic means is accessing or starting to access the first to third storage means, the access by the external arithmetic means ends. In the standby state, when the data to be read in the next read state is not written in the first to third storage units, the writing is performed. An arithmetic assisting circuit, which waits until the operation is completed. 11. The internal processing means according to claim 6, wherein said internal calculation means stores the calculation result in an address of said first to third storage means which reads data on which the calculation is based. An arithmetic assist circuit characterized in that it is written in any of them. 12. The address according to claim 6, wherein said external arithmetic means converts a read address or a write address when reading or writing to said first to third storage means. A conversion unit, wherein, when a zigzag scan instruction indicating that the zigzag scan is performed is given as an instruction for specifying the operation method, the address conversion unit changes a read address or a write address of the external operation unit. An arithmetic assist circuit characterized in that conversion is performed according to a predetermined rule. 13. The first to third reading-side holding means for holding data read from the first to third storage means, respectively, and the first to third reading means, respectively. First to third writing-side holding means for respectively holding the calculation results to be written in the storage means, coefficient holding means for holding the coefficients used for the calculation, and any one of the coefficient holding means and the first A first multiplier for multiplying the data of the reading-side holding unit by a second multiplier for multiplying any of the coefficients of the coefficient holding unit by the data of the second reading-side holding unit; A third multiplier for multiplying any of the coefficients of the coefficient holding means by the data of the third reading-side holding means, an adder for adding the operation results of the first to third multipliers, First to third writing side holding means and the addition Path switching means and said first by combining data of said first reading-side holding means and the second reading-side holding means for switching the data path connecting the bets to either
First data output means for outputting to the first multiplier as data of the reading side holding means, and data of the third reading side holding means as coefficients of the coefficient holding means.
And a second data output means for outputting the data to the multiplier.