JPH02237370A - Picture data processor - Google Patents

Abstract

PURPOSE:To minimize the hardware in an arithmetic means by applying discrete cosine transformation(DCT) to a picture data in an arithmetic means depending on a control data and quantizing the result of calculation in response to the shift assigned to the control data in a shifter. CONSTITUTION:Arithmetic means 19, 20 apply the DCT to a picture data from a picture data storage section by using a control data of a control data storage means and shifters 17, 18 apply quantization to the result of calculation in response to the shift assigned to a control data of the control data storage means. Since the DCT and quantization processing are applied by using a common hardware, the hardware of the arithmetic means 19, 30 is minimized and advantageous economically.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image data processing device used for compression processing of image data.

[Prior Art] Recently, image data compression processing using discrete cosine transformation (hereinafter abbreviated as DCT) has been attracting attention in fields such as videophones.

Here, DCT is one of the orthogonal transformations, and Karnen
Along with the Lewe transformation, this is said to be the transformation method with the highest degree of energy concentration.

Now, the signal f (j) (j = 0, 1, ... N-1)
The result of one-dimensional DCT of F (u) (u=0,1,・
..., N-1) is defined by the following equation.

F (u) =2C(u)/N ・ ,/−1 Σ f (j) cos [(2j+1) u
π/2N]4sO U=O , 1, ...N-1 When U=O When U≠0 Also, the inverse transformation is c (u) = 1/ 2 c (u) =1 f(j) -ΣC (u) F (u) cos [(
2j+1) U π/2N] defined as j=0, 1,...N+1.

In other words, DCT divides a certain waveform into frequency components,
It is expressed using the same number of cosine waves as the number of input samples. And each waveform is F (0): DC F (1): cos [(2j+1) π/2N]
F (2): Expressed as cos [(2j+1)2π/2N]. Here, when N=8, the result is as shown in FIG.

Compression of image data using such DCT involves performing DCT processing in horizontal and vertical two-dimensional directions on image data divided into NxN (for example, 8x8 or 16x16) sub-blocks. Further, the obtained coefficient components are quantized and encoded to compress the amount of data.

[Problem to be Solved by the Invention] However, according to such image data processing, a multiplier is used for the cosine matrix transformation shown in the above-mentioned DCT or inverse DCT definition formula, and furthermore, a multiplier is used for the cosine matrix transformation shown in the above-mentioned DCT or inverse DCT definition formula, and the coefficient components after the DCT are Quantization requires processing circuits such as a sorting circuit and a processing circuit that divides each sub-block pixel by a different quantization value, resulting in an enormous amount of hardware and an expensive price, making it difficult to use economically. There were disadvantageous disadvantages.

The present invention has been made in view of the above circumstances, and provides an economically advantageous image data processing device that can perform DCT processing and quantization processing for data compression using common hardware. I aim to do so.

[Means for Solving the Problems] The present invention has an image data storage means for storing image data, an 11-control data storage means for storing m1j control data, and an arithmetic means having at least one set of shifters and adders/subtractors. Based on the control data of the control data storage means, the calculation means performs DCT conversion of the image data from the image data storage unit, and the calculation result is converted into control data of the control data storage means in the lid. Quantization is performed according to the shift amount assigned to the image.

[Function] As a result, DCT transformation and quantization processing can be performed using common hardware, so the hardware of the calculation means can be minimized, making it economically advantageous.

[Example code] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration of the main circuit of the same embodiment. In the figure, 1 is an external interface circuit, and this external interface circuit has a command register that is addressed by a control signal CP (IC): 12) from a CPU (not shown), and controls internal operation/external operation, DCT/inverse operation. D
It specifies switching such as CT, READ/WRITE, Y/B-Y-RY, etc., and also controls the entire system by setting the flag EXEC. Also, two-dimensional DC
During calculation or quantization of T, it has a function of outputting the NBUSY signal to the outside. 2 is a timing generator, and this timing generator 2 generates a basic timing clock for operating the system. 3 is 10
This counter 3 is a bit synchronous counter that counts the clock P3 from the timing generator 2 and specifies the address of the sequencer memory 6, which will be described later. Here, the synchronous counter 3 is
It is constructed as shown in FIG.

31 is an OR circuit, and an end mark signal LNEND written in a sequence memory 6 (to be described later) together with a DCT conversion program is applied to one input terminal of this OR circuit 3 through an inverter 32, and to the other input terminal. Counter 1 of counter 8, which will be described later, constitutes the second counter.
The output of the NAND circuit 33 to which the contents CT(0) to CT(3) are input is given. The output of this OR circuit 3 is applied to one input terminal of an AND circuit 34. The other input terminal of this AND circuit 34 is connected to the external interface 1.
The flag EXEC output from is given.

The output of the AND circuit 34 is given to the D terminal of the flip-flop 35. The output from the Q terminal of this flip-flop 35 is connected to the D terminal of the flip-flop 36, and the NOR circuit 37
and one input terminal of the AN1 circuit 38, and the output from the Q terminal is supplied to one input terminal of the Nantes circuit 39. Furthermore, the output from the Q terminal of the flip-flop 36 is given to the other input terminal of the NOR circuit 37, and the output from the Q terminal is given to the other input terminals of the three NAND circuits. From Noah circuit 37,
A busy signal NBUSY is output.

Further, the other input terminal of the AND circuit 38 is given the clock P3 from the timing generator 2, and is configured to output this clock P3 to the counter 40. Furthermore, the output of the Nantes circuit 39 is the output of the Nantes circuit 4
I''i is input to one human input terminal of the line 1.The other input terminal of this Nantes circuit 41 is connected to the line 1 enable signal W.
E is given, and the NWE signal is output from its output terminal. The counter 40 consists of three 4-bit binary counters 401, 402, 403, and an AND circuit 3.
IA (0) to I for counting the clock P3 given by 8 and reading out the data in the sequence memory 6.
The address signal of A(9) is output.

Note that the reset signal RESET is applied to the CLR terminals of the flip-flops 35 and 36 via the inverter 42, and to the binary counters 401, 402, and 4 constituting the counter 4o.
The end mark signal LNE is given to the CLR terminal of 03.
ND is connected to the pinary counter 40 via the inverter 32.
It is applied to the LD terminals 1, 402, and 403. Further, the timing signal ARCK is applied to a flip-flop 35,
36 CK terminals.

Returning to FIG. 1, 4, 5, ]] are 2 tol multiplexers, of which multiplexer 4 has a width of 1 bit, and multiplexers 5 and 11 both have a width of ]O bits 1. These multiplexers 4, 5,] are connected to the A side input when the control signal from the CPU is at rLJ level.
” level, the B side input is selected. In this case, the multiplexer 4 receives the write 1 enable signal NCWE from the timing generator 2 or the CPU, and the multiplexer 5 receives the address signal IA (0:9) from the synchronous counter 3 or the address signal C from the CPU.
P(0:9), multiplexer]] is configured to select the output of the address conversion circuit 10 or the address signal (0:9) from the CPU via the comparator 23.

Reference numeral 6 denotes a sequence memory, and this memory 6 stores various control data required for DCT or inverse DCT calculations given from the external interface circuit 1 as a program for each step, and also outputs an end mark signal LNEND or an end mark signal at a predetermined step. It is written. In this case, the control data required for DCT and inverse DCT are in different areas, in this case, the DCT program is in the lower area, and the inverse DCT program is in the second area, and the area designation signal DCT I of the external interface is used. Either DCT or inverse DCT program is designated and read.

Here, the sequence memory 6 is composed of a rewritable 40 bits
It is possible to operate a program of up to 1024 steps in response to the control signals necessary for calculating T. Fourth
The figure shows a configuration diagram of the sequence memory 6. 3 bits are the read address AR (0:2) of the A area of the dual port memory 12, and 3 bits are the read address AR (0:2) of the A area of the memory 12. : 2) Read address BR (0:2) of B area of 3 bits 1 and 2 in the same memory
, 3 bits as write address B of area B of memory 12
W (0:2), 5 bits to the shifter 17 control SA (0:4), 1 bit to the adder/subtractor 19
Control ASA, 2 bits to flip-flop 1
3, 1.4 latch mode AM (0:1), 5 bits shift] 8 control SB (.0:4), 1 bit 1. control ASB of adder/subtractor 20, 2 bits flip-flop 15, 16 latch modes BM (0
:1), 1 bit as through/loop switching A of calculation system A
TL, 1 bit as through/loop switching BT of calculation system B
L, 1 bit is cross/parallel switching CP, 1 bit is sequencer end mark LNEND, 2 bits is quantization data AN (0:1) of calculation system A, 2 bits is quantization data BN (0: 0) of calculation system B. 1), 1 bit is used for quantization control COMP.

Various control signals of the sequence memory 6 are an inverted signal N of the clock P3 from the timing generator 2.
After being temporarily latched by the flip-flop 7 at the rising edge of P3, it is output.

Here, the end mark signal LNEND latched by the flip-flop 7 is applied to the counter 8 via the inverter 24. In this case, the counter 8 counts the falling edge of the end mark signal LNEND with 4 bits 1 and 8x8 sub-block 1]? First-order row operations are performed on the image data that has been converted into blocks from 0 to 7 I1, and second-order column operations are performed to 8 to F It. Further, the read address AR (0:2) and write address AW (0:2) stored in the flip-flop 7 are sent to the address conversion circuit 9 as read address BR (0:2) and write address BW (0:2). ) are respectively applied to the address conversion circuit 10. The address conversion circuit 9 includes a flip-flop 7
The address signal A (0:9) of the A area of the dual port memory 12 is output from the read address AR (0:2), write address AW (0:2) and the count value of the counter 8, and the address conversion circuit 10 is the address signal B (0:9) of the B area of the dual port memory controller 2 from the write address BR (0:2) from the flip-flop 7, the write 1 address BW (0:2), and the count value of the counter 8. It is designed to output .

The dual port memory 12 stores image data and is composed of 16 bits x 1024 words.

Then, according to the address signals A (0:9) and B (0:9) from the address conversion circuit 9, ]0,
data MA (0:15), MB (0:1
5) can be written and read. Further, this dual port memory 12 is used not only to store input data when performing DCT or inverse DCT and output data that is the result of the calculation, but also as a work memory to temporarily store data in the middle of calculation.

Next, FIG. 2 shows the circuit configuration of the arithmetic unit of the same embodiment. In this case, the arithmetic unit has two arithmetic systems A and B.

13 and 14 are a group of 16-bit flip-flops, and the first data MA (0:1
5) Latch. Further, 15 and 16 are also a group of 16-bit flip-flops, which latch the second data MB (0:15) from the dual port memory 12. Here, the operation timing of the flip-flop groups 13 and 6 is determined by the timing signals ARCK and BRCK, and the operation timing of the flip-flop groups 14 and 15 is determined by the timing signals ARPCK and BRPCK.

The data latched in the flip-flop group 13 is applied to the shifter 17 and also to the ten terminals of the adder/subtractor 20 via the gate G1, and the data latched in the flip-flop group 16 is applied to the shifter 18 and the 1.G2 to the ten terminal of the adder/subtractor 19. Further, the data latched in the flip-flop group 14 is given to the ten terminal of the adder/subtractor 19 via gate G7, and the data latched in the flip-flop group 15 is given to the ten terminal of the adder/subtractor 19 via gate G8. .

Here, the shifter 17 is constructed as shown in FIG. 51 is a barrel shifter, and this barrel shifter 51 is 1
The 6-bit data can be shifted up and down by 8 bits in 1-bit units, and the amount of shift here is controlled by the output of the multiplexer 52. When the quantization control COMP is at the rLJ level in normal DCT calculation, the multiplexer 52 is controlled by the shifter control SA (0:4) by the rLJ level output of the AND circuit 53, and the quantization control COMP is at the rHJ level. In this case, it is controlled by the output of the table 54 after waiting for the AND circuit 53 to become rHJ level. Here, the table 54 includes quantized data AN (0:
The count value CT of the counter 8 mentioned above is determined by the shift amount shown in FIG.
The tables shown in FIGS. 6(b) and 6(c) are constructed corresponding to (0:2), thereby making it possible to realize power-of-2 quantization in units of pixels of a subblock of 8×8. Here, the sixth
Figure (b) shows the luminance signal Y, Figure (c) shows the color difference signal B-Y,
It shows a table of RY. Also, quantized data AN
(0) and AN (1) are both "1", and the output from the barrel shifter 51 is clipped by the clip circuit 56 based on the output of the NAND circuit 55. This is because the purpose of the 16-bit shift is to set harmonic component data to 0. Of course, the other chic 18 is also similar to the shifter 17.

Returning to FIG. 2, the output from shifter 17 is output from adder/subtractor 19.
The output from the shifter 18 is given to the second terminal of the adder/subtractor 20, and is written to the dual port 1 memory 12 via the gate G3.
It is written to the dual port memory 12 via G1 and G4. The adders and subtracters 19 and 20 are 4-bit full adders×
4 and an EX-OR group, and performs two's complement arithmetic. The calculation results from these adders and subtracters 19 and 20 are latched by flip-flops 21 and 22, respectively, and then written to the dual port memory 12 through gates G5 and G6, respectively. Here, the operation timing of the flip-flops 21 and 22 is determined by the timing signal ALCK.

Next, the operation of the embodiment configured as described above will be explained.

In this case, when the control signal CPU from the CPU is at the rLJ level, both the multiplexers 4 and 5 select the A manual side. In addition, the sequence memory 6 has already been loaded with a DCT program in the lower part/rear and an inverse DCT program in the -1 second area, and from this state, the sequence memory 6 is now loaded with the area designation signal DCT I of the external interface 1. It is assumed that the DCT program in the lower area of is specified.

First, in FIG. 3, flip-flops 35, 36 and counter 40 are cleared by reset signal RESET. After that, the 8-bit image data is expanded to 16-bit signed data, or transferred from the CPU to the DB (0:7).
The data is applied to the dual port memory 12 via the dual port memory 12. Then, when all 16 bits x 64 pieces of data of the 8 x 8 sub-blocks have been written, the flag EXEC is set in the external interface 1 [FIG. 7(b)]. Then,
Since the output of the AND circuit 34 becomes rHJ level, [7th]
Timing signal ARC shown in Figure (10) and Figure 7 (c)
At the rising edge of K, the outputs of the Q terminals of flip-flops 35 and 36 sequentially become rHJ level [Figure 7(d)(e)]
, the clock P3 shown in FIG. 7(a) is supplied to the counter 40 via the AND circuit 38 [FIG. 7(f)].

At the same time, the output of the NOR circuit 37 becomes rLJ level, and a busy signal NBUSY is output to the CPU [FIG. 7(1)].

Further, since the output of the NAND circuit 39 becomes rHJ level, the write enable signal WE shown in FIG. m)]. In this state, the output of the counter 40 is applied to the sequence memory 6 as the address signal IA (0:9) from the synchronous counter 3 [FIG. 7(g)]. Here, if the end mark signal LNEND is written in the control data read out at the third step of the sequence memory 6 as shown in FIG. O is loaded and reset at a single rising edge of the clock, and at the falling edge of the end mark signal LNEND, the count content CT (0:3) of the counter 8 is incremented by 1 [Figure 7 (1)] ]. In this case, the count content of counter 8 CT (0:3
), the 8×8 DCT transform advances to the second row. Thereafter, by repeating the same operation, when the two-dimensional final stage (No. 8, 1") is reached and CT (0:3) = 15, the output of the OR circuit 31 becomes rLJ due to the rHJ level of the end mark signal LNEND. level, and the output of the Q terminal of the flip-flop 35 becomes rLJ level with the next applied timing signal ARCK.
Clock P3 applied to counter 40 through AND circuit 38 is stopped, and data reading from sequence memory 6 is also stopped. In addition, the flip-flop 36 allows 1
Write enable signal NWE is also stopped with a timing delay.

Next, the calculation timing in the calculation section will be explained.

First, the address signal IA ([9) from the synchronous counter 3 to the sequence memory 6 shown in FIG. 8(C) is set to 0, 1, 2 by the clock P3 from the timing generator 2 shown in FIG. 8(a). When output in the order of...
The sequence data in sequence memory 6 is read out [8th
Figure (d)], falling signal NP3 of clock signal P3
is latched to the flip-flop 7 [Fig. 8(e)]
. This state is maintained for one cycle of operation.

Here, the first half of one cycle is a read section of the dual port memory 12 as shown in FIG. 8(f), and the read address AR (0
:2), BR (0:2) is address conversion circuit 9, 10
and the first and second address signals A (0:9
), B (0:9) to the dual port 1 memory 12.

As a result, data MA (015
), MB (0:15) or two are read at the same time,
Timing signals ARCK and BRCK shown in FIG. 8(g)
At this timing, the signal is latched by the flip-flops 13 and 16, and then a predetermined operation is executed by the adders and subtracters 19 and 20 [FIG. 8(i)].

Here, when the cross-parallel switching CP from the flip-flop 7 is at the rHJ level, the gates G1 and G2 are closed;
The gates G7 and G8 are opened, and the data latched in the flip-flop 3 is applied to the + terminal of the adder/subtractor 19 via the shifter 7, and is also applied to the + terminal of the adder/subtracter 20 via the gate Gl. The data latched in the flip-flop 16 is passed through the shifter 18 to the adder/subtractor 20.
It is applied to the terminal of the adder/subtractor 19 via the gate G2, and when the cross-parallel switching CP is at the rLJ level, the gates G1 and G2
opens, gates G7 and G8 close, the data latched in the flip-flop 13 is given to the 10 terminal of the adder/subtractor 19 via the shifter 17, and the data latched in the flip-flop 14 is given to the 10 terminal of the adder/subtractor 19. The data latched in the flip-flop 16 is transferred to the shifter 18.
The data that is applied to the 10 terminal of the adder/subtractor 20 through the adder/subtractor 20 and latched by the flip-flop 15 is then applied to the 10 terminal of the adder/subtractor 20, and a predetermined operation is executed.

Then, when the calculations in each adder/subtractor 19 and 20 are executed, the latter half write period shown in FIG. AW(0:2)BW of the dual port memory 12 at the rising timing of the write enable signal NWE shown in FIG. 8(j).
It is written to the address addressed by (0:2).

In addition, in the case of the through mode in which the through loop switching becomes ATL, BTL or rHJ level and gates 1-G3 and G4 are opened, the results shifted by the shifters 17 and 18 are written as they are to the dual port memory 12. It becomes like this.

Next, quantization performed on coefficient components obtained by such DCT processing will be described. in this case,
When the counter value of the counter 8 reaches (-15), that is, when the DCT transformation reaches the two-dimensional final stage, CT (3
) reaches the rHJ level, the quantization control COM
After waiting for P to reach the rHJ level, the rHJ level from the AND circuit 53 is applied to the multiplexer 52,
The output from the table 54 is now applied to the amplifier 5 through the multiplexer 52. In this case, in the table 54, the quantized data AN(1.)(
The output from the table shown in FIGS. 6(b) and 6(C), which is configured by the shift amount shown in FIG. 6(a) assigned to 0), is given to the barrel shifter 51. As a result, the DCT is read from the dual port memory] 2 and applied to the barrel shifter 51 via the flip-flop 13.
Power-of-2 quantization is performed on the data after the calculation according to the tables shown in FIGS. 6(b) and 6(c). In other words,
When the table 54 specifies the luminance signal Y shown in FIG. 6(b) or the color difference signal B-Y, RY shown in FIG. 6(c), the 8× For each pixel of the 8 image data, a shift l. is performed by the number of bits of the corresponding address in the table, and quantization is performed. Note that the quantized data AN (0)(
1) are both "1", the output from the NAND circuit 55 causes the clip circuit 56 to clip the output from the barrel shifter 5.

This is to set the data of ]6 bit 1, shift 1, and high ultrasonic components to 0.

In the following explanation, we have described the case where the DCT program in the lower area of the sequence memory 6 is designated by the area designation signal DCT I from the external interface 1, and the DCT operation is executed according to this program. Even when the inverse DCT program in the second area of the sequence memory 6 is specified, each circuit is operated according to the control data of the program in the same manner as described in section 2, and the inverse DCT operation is executed.

[Effects of the Invention] The present invention has an image data storage means for storing image data, a control data storage means for storing control data, and an arithmetic means having at least one set of shifters and adders/subtractors, and the control data storage means The calculation means performs DCT transformation of the image data from the image data storage section using the control data, and the calculation result is converted according to the shift amount assigned to the control data of the control data storage means in one chic. Since quantization is performed using common hardware, DCT conversion and quantization processing for data compression can be performed using common hardware, and the hardware required for calculation means can be kept to a minimum, making it inexpensive. This can be extremely advantageous economically.

[Brief explanation of drawings]

1 and 2 are block diagrams showing the circuit structure of an embodiment of the present invention, FIG. 3 is a block diagram showing the circuit structure of a synchronous counter used in the embodiment, and FIG. i) A configuration diagram of the sequence memory; Figure 5 is a block diagram showing the circuit configuration of a shifter used in the same embodiment; Figure 6 is a diagram for explaining the shifter; Figures 7 and 8 are diagrams showing the same implementation. A time chart for explaining an example, Figure 9 is D
It is a waveform diagram for explaining CT. 1... External interface, 2... Timing generator, 3... Synchronous counter, 4, 5,
11... Multiplexer, 6... Sequence memory, 7... Flip-flop, 8... Counter, 9, 1
0... Address conversion circuit, 12... Dual port memory, 13-16, 21, 22... Flip-flop, 17, 18... Shifter, 19, 20... Addition/subtraction device. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] an image data storage means for storing image data; a control data storage means for storing control data; a calculation means having at least one set of shifters and an adder/subtractor; means for performing discrete cosine transformation of the image data from the image data storage unit and quantizing the result of the calculation in the shifter according to the shift amount assigned to the control data of the control data storage means. An image data processing device characterized by: