JPH02237040A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to realize an increase in the output of a semiconductor device by a method wherein the device is provided with a first recessed grooved with a gate electrode and a second recessed groove provided in a semiconductor layer between the first recessed groove and a drain electrode. CONSTITUTION:A recessed groove 10a having a gate electrode 11 is formed in a semiconductor layer 3 between a source electrode 8 and a drain electrode 9 like a conventional one. Moreover, one piece of a recessed groove 10b is provided in the layer 3 between the groove 10a having the electrode 11 and the electrode 9 to constitute a semiconductor device. Thereby, a large current can flow on the condition of a gate voltage VG<0 like (x) and moreover, a high breakdown voltage can be attained on the condition of a gate voltage VG<0 like that, a load line can be made longer than a conventional one like F f and a high output can be realized.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device having a recess groove, a gate voltage v. >0, a large current can be achieved, and the gate voltage v. The purpose of the present invention is to provide a semiconductor device that can achieve high breakdown voltage at <0 and achieve high output, and has a recess groove in the semiconductor layer between the source electrode and the drain electrode. In a semiconductor device having a structure in which a gate electrode is provided in the recess groove, a first recess groove in which a gate electrode is provided, and a second recess provided in a semiconductor layer between the first recess groove and a drain electrode. It is configured to have a groove. [Industrial Field of Application] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device that can achieve high output. In recent years, GH. Semiconductor devices such as MES FETs, which use compound semiconductors such as GaAs and have a gate electrode in a recess groove formed between a source electrode and a drain electrode, are attracting attention as custom-order microwave communication devices. It has become to.

(Prior Art) FIGS. 4 and 5 are diagrams for explaining a conventional semiconductor device. FIG. 4 is a cross-sectional view showing the structure of the conventional example, and FIG. 5 is a diagram showing the drain voltage (Vos) and FIG. 3 is a diagram showing the relationship with drain current (I0). The illustrated semiconductor device is made of GaAs.
- This is the case when applied to FET.

In these figures, 31 is a substrate made of semi-insulating GaAs, 32 is a buffer layer made of i-GaAs, 33 is a semiconductor layer made of n-GaAs, etc.
4 is a recess groove, 35 is, for example, AuGe/N i /
The source electrode 36 is made of an A u layer, for example, an A u G layer.
A drain electrode made of e/Ni/Au layers, 37 a gate electrode made of A2, for example, and 38 made of Si. N. It is a passivation film consisting of.

In the conventional semiconductor device described above, the amount of current flowing between the source electrode 35 and the drain electrode 36 is adjusted by adjusting the thickness of the depletion layer generated in the semiconductor layer 33 under the gate electrode 37.
The voltage is adjusted as appropriate by adjusting the voltage applied to the voltage. Here, the gate electrode 3 is located in the recess groove 34 formed in the semiconductor layer 33 between the source electrode 35 and the drain electrode 36.
7 is formed. The recess groove ″34 here mainly has two functions, specifically, the recess groove ″34 has two functions.
The S portion of the Shosotky junction surface between the gate electrode 37 and the
The function is to reduce the influence of the surface unit (this creates a depletion layer on the surface of the semiconductor layer 33) by moving it away from the surface (T part) of the semiconductor layer 33 made of s, and to prevent abnormalities near the gate electrode 37 of the Schottky metal. It has two functions: one to control electric field concentration. Note that the depletion layer here does not occur only between the semiconductor N33 and the gate electrode 37, but extends to the surface of the semiconductor layer 33.

Therefore, in order to improve the operating characteristics, it is necessary to
It is desirable to keep the Schottky junction between the semiconductor layer 33 and the gate electrode 37 as far away as possible from the depletion layer formed on the surface of the semiconductor layer 33. The effect of the recess groove 34 is as shown in FIG.
It is mainly determined by the depth t of the recess groove 34 and the distances L and I from the bottom end of the recess groove 34 to the bottom end of the gate electrode 37, especially L. is important. This LR is usually 0.4 to 0.
It is 7 μm. When configuring a high output FET, as shown in FIG. 5, it has high current and high breakdown voltage operation. Here, when L and t are small, the influence of the surface states in the recess groove 34 is small, and the drain current at the gate voltage v,>0. , extends to a large current like A1, but on the other hand, the reverse breakdown voltage of the Schottky becomes small, and the gate voltage vr. Drain voltage V0 of breakdown at <0
, becomes small like A2. Note that as the voltage applied to the gate electrode 37 is increased with the gate voltage vG>0, the depletion layer generated in the semiconductor layer 33 under the gate electrode 37 tends to become smaller, and the gate voltage V, At 0, it tends to be large. Also, when LR is large, the Schottky reverse breakdown voltage becomes large, and the gate voltage VG<O
Although the drain voltage VOS of the breakdown at 82 becomes large, the influence of the surface level in the recess groove 34 becomes large, and the drain current 2 when the gate voltage vG>O. , becomes small as B1.

In addition, in Fig. 5, C is ■D3-V0 at v,=0
It is a characteristic.

[Problem to be solved by the invention]

Therefore, in such conventional semiconductor devices,
L. is determined automatically, and the load line shown in Fig. 5 cannot be lengthened, reaching the limit of increasing the output. Specifically, when increasing the current at the gate voltage v,〉0 as shown in A1, and B2 There is a problem in that it is not possible to increase the breakdown voltage at the same time when the gate voltage VG<0 as shown in FIG.

Here, when the gate voltage v6>0, the ideal drain current ■.

, ideally the semiconductor layer 3 under the gate electrode 37
We want to flow a current equivalent to the thickness of V.3, but the gate voltage V. No matter how much you swing in the positive direction, the semiconductor layer 33
Since the depletion layer formed on the surface does not become smaller, it becomes impossible to increase the current. And even if the fifth
Even if a large current is applied with <ve>o as shown in A1 shown in the figure, VG
<At 0, the part you want to break down with B2 is A
It breaks down at 2. Therefore, the present invention is capable of increasing the current when the gate voltage V,>Q, and when the gate voltage V. It is an object of the present invention to provide a semiconductor device that can achieve a high breakdown voltage at <0 and can achieve high output.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device according to the present invention has a recess groove in a semiconductor layer between a source electrode and a drain electrode, and a gate electrode in the recess groove. The semiconductor device has one recess groove and a second recess groove provided in the semiconductor layer between the first recess groove and the drain electrode.

[Effect]

The present invention provides a first recess groove provided with a gate electrode formed in a semiconductor layer between a source electrode and a drain electrode, and a second recess provided in a semiconductor layer between the first recess groove and the drain electrode. It is configured to have a groove. Therefore, as shown in Fig. 2, it is now possible to increase the current at the gate voltage 〉0, as indicated by X.
In addition, it is now possible to achieve a high breakdown voltage when the gate voltage vG>Q as shown in y, and the load line can be changed to F-f.
In this way, it is now possible to make it longer than the conventional one, making it possible to achieve higher output.

〔Example〕

1 to 3 are diagrams explaining one embodiment of a semiconductor device according to the present invention, FIG. 1 is a cross-sectional view showing the structure of one embodiment, and FIG. 2 is a diagram explaining the effects of one embodiment. Figure 3 (a
) to (k) are diagrams illustrating the manufacturing process of one embodiment.

In these figures, l is a substrate made of, for example, semi-insulating GaAs, 2 is a buffer layer made of, for example, i-GaAs, 3 is a semiconductor layer made of, for example, n-GaAs, . 4a,
4b, 4c are insulating films made of, for example, SiOz, 5a, 5
b is a mask layer made of resist, for example, 6a, 6b, 6
c, 5d, 6e, and 6f are openings, and 7a is, for example, AuGe.
Layer/Ni layer/Metal layer made of 3N of A u @, 7b
7c is a metal layer made of, for example, three layers of WSi layer/Ti layer/Au layer, 7c is a metal layer made of plating such as Au, and 8
9 is a source electrode, 9 is a drain electrode, and the source electrode 8 and the drain electrode 9 are made of a metal layer 7a.

10a and 10b are recess grooves, and the recess groove 10a corresponds to a first recess groove according to the present invention, and the recess groove 10b corresponds to a second recess groove according to the present invention. Reference numeral 11 denotes a gate electrode, which is made up of metal layers 7b and 7C.

12 is a passivation film made of Si x N4, for example. Here, as shown in FIG. 1, the distance L1 from the bottom end of the gate electrode l1 to the bottom end of the recess groove 10a is set to about 0.1 to 0.3 μm, and the recess groove 10b
*LII is formed with a bottom width L of about 0.1 to 3 μm, for example, and is preferably smaller than I. Next, we will explain the manufacturing process. First, Figure 3 (
As shown in a), for example, vPE (Vapour P
Semi-insulating GaAs
i-GaAs and n-GaAs are sequentially grown epitaxially on the substrate l to form the i-GaAs bathophore layer 2 and the n-GaAs
An aAs semiconductor layer 3 is formed, and a Sin. After forming the insulating film 4a by depositing resist, a resist is applied on the insulating film 4a, and this resist is patterned to form a mask layer 5a for forming source/drain electrodes. At this time, an opening 6a is formed.

Next, as shown in FIG. 3(b), for example, HF solution and N
Mixed solution of HFS liquid (HF: NHI'l = 1:1
After selectively etching the insulating film 4a in the opening 6a using the mask N5a as a mask to expose the semiconductor layer 3 by wet etching according to No. 0), a metal layer 7a is formed on the entire surface.
form. Specifically, the metal N 7 a is formed by, for example, an AuGe layer having a layer thickness of, for example, 400 mm, a Ni layer having a layer thickness of, for example, 100 mm, and an A layer having a layer thickness of, for example, 1500 mm.
Three AuGe layers with sequential formation of uN/N i Ji
/ A u II3.

Next, as shown in FIG. 3(C), lift off? By removing the mask N5a, a source electrode 8 and a drain electrode 9 are formed. At this time, the metal 15 7 on the mask layer 5a
a is also removed. Next, the insulation #4a is removed by wet etching using, for example, a mixed solution of HF solution and NHF solution (HF:NHF3=1:10), and then heat treatment is performed at, for example, 450° C. to make the source electrode 8 and the drain electrode 9 ohmic. Make contact. Next, after depositing SiO2 to cover the source electrode 8 and drain electrode 9 by, for example, the CVD method to form an insulating film 4b with a thickness of 3000, a resist is applied on the insulating film 4b.
This resist is patterned by, for example, EB exposure to form a mask jW5b for forming a recess groove. At this time, the opening 6b has a width of, for example, 0.9 μm, and the width of the opening 6b has a width of, for example, 0.3 μm.
m openings 6c are formed.

Next, as shown in FIG. 3(d), for example, CF. Using the mask layer 5b as a mask, the insulating film 4b in the openings 6b and 6C is selectively etched by RIE using a mixed gas of gas and CHF3 gas to expose the semiconductor layer 3. At this time, for recess groove formation? Mouth portions 6d and 6e are formed.

Next, as shown in FIG. 3(e), wet etching is performed using a mixed solution of, for example, H20 solution, HF solution, and Semiconductor layer 3 is selectively etched to form recess grooves 10a and 10b. Then, mask N5b is removed.

Next, as shown in FIG. 3(f), Sin. is deposited to form an insulating film 4C having a thickness of 3,000.

Next, as shown in FIG. 3(g), the semiconductor N3 in the recess 110a is removed by RIE using SF h gas, for example.
The insulating film 4C is etched until exposed. At this time,
The insulating film 4C that has not been etched remains on the side wall portion of the recess groove 10a and inside the recess groove 10b.

Next, as shown in FIG. 3(h), a metal layer 7b is formed so as to make contact with the semiconductor layer 3 within the recess groove 10a. Specifically, the metal N1b is formed by sputtering rvj. After forming a WSi layer with a thickness of, for example, 1,500, a layer with a thickness of, for example, 20
TiJiJ of 0 and AuJ with a layer thickness of e.g. 1000.
3N WSii/TiJiW/Au formed sequentially
It consists of H. Next, resist the metal JW? b, and this resist is patterned to form a mask layer 5C for forming an overgate. At this time, opening 6f
is formed.

Next, as shown in FIG. 3(i), a metal layer 7C as an overgate is formed by Au plating so as to make contact with the metal layer 7b using the mask layer 5C as a mask.

Next, as shown in FIG. 3(j), after removing the mask layer 5C, the metal Wi7b is selectively etched using the metal layer 7c as a mask to form a gate electrode l1 made of the metals Ji7b and 7C. ．． At this time, the insulating films 4b and 4C are exposed. Specifically, the metal layer 7b is removed by removing the uppermost layer A1N forming the metal IJ7b by, for example, ion milling using Ar gas, and removing the second layer forming the metal layer 7b by, for example, RIE using CF4 gas and 02 gas. ,3
This can be achieved by sequentially removing the TiN and WSi layers.

Then, after removing all of the insulating films 4b and 4c using the gate electrode 11 as a mask by wet etching using a mixed solution of HF and NHFj solutions (HF:NHF3=1:1O), for example, the insulating films 4b and 4c are etched using a photo-CVD method, for example. By depositing Si3N on the entire surface to form a puffscivation film 12 having a film thickness of, for example, 500, as shown in FIG.
A semiconductor device having the structure shown in k) is completed.

That is, in the above embodiment, as shown in FIG. 1, a recess groove 10a having a gate electrode 11 is formed in the semiconductor layer 3 between the source electrode 8 and the drain electrode 9, as in the conventional case. Recess groove 10 having gate electrode 1l
Further, a recess groove 10 is formed in the semiconductor N3 between a and the drain electrode 9.
Since the configuration is provided with one b, as shown in Fig. 2,
A large current can be achieved with the gate voltage 《〉〉0 as shown in Figure y, and a high breakdown voltage can be achieved with the gate voltage V〉〉Q as shown in Figure y, and the load line is called F-f. So can it be longer and higher than the traditional one? It is possible to realize empowerment.

Here, the reason why a large current can be achieved at a gate voltage vG>0 as shown in
is the conventional L. shown in FIG. →L+u CLti < L
+u), the recess groove 1
This can be achieved by reducing the region of the depletion layer formed on the surface of the semiconductor N3, which was conventionally affected by the provision of 0b, to a region with a width of LRg.

In addition, the reason why it is possible to simultaneously increase the current and increase the breakdown voltage at gate voltage Ve<0 is that electric field concentration occurs in the Lllll region and L■ region, but the electric field in the L■ region This can be achieved because the concentration is alleviated by the electric field concentration in the wrinkle area. Therefore, it is possible to achieve high output. In the above embodiment, as shown in FIG. 1, a case has been described in which one recess groove 10b is further provided in the semiconductor layer 3 between the recess groove 10a having the gate electrode 11 and the drain electrode 9. The invention is not limited to this, and it is sufficient if at least one or more recess grooves 10b are further provided in the semiconductor JW3 between the recess groove 10a having the gate electrode 11 and the drain electrode 9;
It is also possible to provide two or three b.

〔Effect of the invention〕

According to the present invention, it is possible to increase the current when the gate voltage V,>Q, and the gate voltage is low. This has the effect that it is possible to achieve a high breakdown voltage at a low voltage of 0, and that it is possible to achieve a high output.

[Brief explanation of drawings]

1 to 3 are diagrams for explaining one embodiment of a semiconductor device according to the present invention, FIG. 1 is a cross-sectional view showing the structure of one embodiment, and FIG. 2 is a diagram explaining the effects of one embodiment. 3 is a diagram explaining the manufacturing process of one embodiment, FIG. 4 is a sectional view showing the structure of the conventional example, and FIG. 5 is the drain voltage (V■) and drain current (■) of the conventional example. , ). 1...substrate, 2...buffer layer, 3...n GaAs semiconductor layer, 8...
・Source electrode, 9...Drain electrode, lQa, 10b...Recess groove, l1...
・Gate electrode. Figure 3 is a diagram explaining the manufacturing process of the embodiment. Figure 3 is a diagram explaining the manufacturing process of the embodiment. Figure 3 is a diagram explaining the cleaving process of the embodiment. ) and Dray 4th style (lo
M

Claims (1)

[Scope of Claims] A semiconductor device having a structure in which a recess groove is provided in a semiconductor layer between a source electrode and a drain electrode, and a gate electrode is provided in the recess groove, comprising: a first recess groove in which a gate electrode is provided; A semiconductor device comprising the first recess groove and a second recess groove provided in a semiconductor layer between the drain electrode.