JPH02188931A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make a characteristic of a semiconductor device good by reducing a resistance between electrodes and to realize a high integration by a method wherein eaves composed of a semiconductor layer and an insulating film are formed at the upper part of an opening made in the semiconductor layer on a semiconductor substrate, a conductive material is deposited from the upper part and electrodes are formed at the bottom of the opening and on the surface of the semiconductor layer. CONSTITUTION:A first semiconductor layer and a second semiconductor layer 40, 41 are laminated on a semiconductor substrate 42; after that, the second semiconductor layer 41 is etched; and a first opening 43 is formed. Then, the surface of the semiconductor layer 41 and a side wall, of the semiconductor layer 41, exposed from the first opening 43 are covered with an insulating film 44. Then, the first semiconductor layer 40 is etched isotropically by making use of the insulating film 44 as a mask; a second opening 45 whose width is wider than a gap between mutual parts of the insulating film 44 at the side wall of the second semiconductor layer 41 is formed; and thereby, eaves 46 composed of the second semiconductor layer 41 and the insulating film 44 are formed at the upper part of the second opening 45. Then, the insulating film 44 is etched anisotropically; the insulating film 44 formed at the side wall of the second semiconductor layer 41 is left; after that, a conductive material 47 is deposited from the upper part; and electrodes are formed at the bottom of the second opening 45 and on the surface of the second semiconductor layer 41.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device, which improves the characteristics of the semiconductor device and improves the characteristics of the semiconductor device. For the purpose of increasing the area ratio, a first semiconductor layer and a second semiconductor layer are sequentially stacked on a semiconductor substrate, and then the second semiconductor layer is etched to form a first opening. 1 etching process and the above 2nd etching process.
The upper surface of the semiconductor layer and the second semiconductor layer exposed from the first opening.
isotropically etching the first semiconductor layer using the insulating film as a mask, and etching the insulating film on the sidewalls of the second semiconductor layer. By forming a second opening wider than the gap formed by the second opening, a second opening formed of the second semiconductor layer and the insulating layer is formed above the second opening. an etching step, and a third etching step for anisotropically etching the insulating film to leave the insulating film formed on the sidewall of the second semiconductor layer after the second etching step; The method includes the step of depositing a conductive material from above the semiconductor substrate that has undergone the process to form an electrode at the bottom of the second opening and on the surface of the second semiconductor layer.

(Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device including a plurality of wiring electrodes and a method for manufacturing the same.

[Conventional technology]

High electron mobility transistor (HEMT) and GaAsME
Semiconductor devices such as SFETs employ recessed structures to reduce source resistance, and in line with the demand for cylindrical integration of compound semiconductors, these types of semiconductor devices require non-blowing when forming electrodes. It has been proposed to make ohmic metal semiconductor contacts.

When forming an ohmic electrode in a transistor that employs a recessed structure, in order to shorten the manufacturing process, a conductive material is deposited from above the semiconductor substrate 50, as shown in FIG. , a process is performed in which the ohmic electrode 51 for the source and drain and the gate electrode 52 are formed simultaneously in a self-aligned manner.

However, when these electrodes are formed by vacuum evaporation, sputtering, etc., sidewalls W as shown in FIG. 5 are partially generated, and the gate electrode 52 formed in the recess 53 of the semiconductor substrate 50 is There is a problem in that the ohmic electrode 51 on the side thereof is short-circuited.

Therefore, in order to prevent short circuit between the ohmic electrode 51 and the gate electrode 52, as shown in FIG.
An insulating film 54 is provided on the side of the area where the insulating film 54 is formed, and a resist 55 is formed on the insulating film 54. A conductive metal 56 for forming an electrode is then laminated on top of this. A method of removing the conductive metal 56 using a lift-off method has also been proposed.

[Problem to be solved by the invention]

However, when the insulating film 54 is provided between the gate electrode 52 and the ohmic electrode 51, the gate electrode 52 is separated from the ohmic electrode 51 for source and drain, so that the depleted region on the substrate surface is There are problems in that the spread increases the source resistance, deteriorating transistor characteristics, and lowering the integration density of semiconductor elements only in the area where the insulating film 54 is formed.

The present invention has been made in view of these problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the characteristics of the semiconductor device and achieve high integration.

(Means for Solving the Problems) The above problems can be solved after sequentially stacking the first semiconductor layer (4o) and the second semiconductor layer (41) on the semiconductor substrate (42) (see FIG. 1(a)). )), a first etching step of etching the second semiconductor layer (41) to form a first opening (43) (FIG. 1(b));
41) an insulating film (44) covering the upper surface and the side wall of the second semiconductor layer (40) exposed through the first opening (43);
(FIG. 1(C)) and the step of forming the insulating film (44).
The first semiconductor layer (4o) is isotropically etched using the second semiconductor layer (4o) as a mask, and a second semiconductor layer (4o) having a width wider than the gap formed between the insulating films on the sidewalls of the second semiconductor layer (41) is etched. By forming an opening (45), a second eaves (46) made of the second semiconductor layer (41) and the insulating film (44) is formed above the second opening (45). After the etching process (FIG. 1(d)) and the second etching process, the insulation D formed on the side wall of the second semiconductor layer (4o) by anisotropically etching the insulation [(44)]
a third etching step in which I(44) remains;
(e), a conductive material (47) is deposited from above the semiconductor substrate (42) that has undergone the third etching step to form the bottom of the second opening (45) and the second semiconductor layer (41). The problem is solved by a method of manufacturing a semiconductor device characterized by comprising a step of forming an electrode on the surface (FIG. 1(f)).

[Function] In the above invention, the inner wall of the first opening (43) formed in the semiconductor substrate (42) and the insulating lFi attached thereto
! (44) protrudes inwardly from the inner wall of the second opening (45) below to form an eave (46), so it can be self-aligned from above by vacuum, vapor deposition, sputtering, etc. The formed conductive material (47) is connected to the second opening (45).
It does not adhere to the inner wall of the

For this purpose, electrodes formed on the second semiconductor layer (41) on both sides of the first opening (43) and the second opening (43) are formed on the second semiconductor layer (41).
5) is not electrically connected to the electrode formed at the bottom of the second semiconductor layer (41) due to the conductive sidewall, and an insulating film as shown in FIG. 6 is interposed on the surface of the second semiconductor layer (41). Therefore, the distance between the electrodes can be made extremely small.

Furthermore, since the insulating film (44) used as a mask when etching the first semiconductor layer (40) can be used as the eaves (46), the amount of protrusion of the eaves (46) can be increased and the opening ( 45) It becomes possible to completely prevent the conductive film from adhering to the inside.

As a result, the semiconductor device can be highly integrated, and the resistance between the electrodes of the semiconductor device can be reduced.

[Example] (a) Description of one embodiment of the present invention Fig. 2 is a cross-sectional view of a high electron mobility transistor (HEMT) showing an embodiment of the present invention, and the symbol l in the figure is
The active layer is formed on the semiconductor 5Fi, 2, and is composed of a GaAs layer 3 and an n-AlGaAs layer 4, and is configured so that a two-dimensional electron gas n is generated at the interface on the GaAs layer 3 side.

On top of this active layer 7111 is GaA doped with impurities.
A first cap layer 8 consisting of an s layer 5, an AlGaAs layer 6, and a GaAs layer 7 is formed, and on top of the first cap layer 8, an AlGaAs layer 9 doped with impurities and an InGaAs layer 8 are formed.
A second cap jlNll having O is provided, and a groove 13 for forming a gate electrode is provided in a region 12 of the first and second cap layers 8.11 where a gate electrode is to be formed. A side wall 14 made of an insulating material is formed on the inner wall portion of the second cap layer 11 of the groove 13 so as to protrude laterally.

Reference numeral 15 denotes a gate electrode formed in the gate electrode forming region 12 of the active layer 1. This gate electrode 15 is formed by passing a conductive element from above the semiconductor substrate 2 through the gate electrode forming groove 13 into the active layer by sputtering or the like. The first cap layer 8 is thinner than the first cap layer 8.

Further, when forming this gate electrode 15, at the same time, the second cap layer 11 existing on both sides of the gate electrode 15 is
A conductive element is deposited on top of the ohmic electrode 1.
6.

In this case, since the insulating sidewall 14 protruding inward from the gate electrode forming groove 13 functions as an eaves, the conductive element entering the gate electrode forming groove 13 is prevented from adhering to the inner wall of the first cap N8. No, Ohmic Den I! 11
6 and the gate electrode 15 is prevented.

This allows the gate electrode 15 to be formed in a self-aligned manner.

Next, an example of a method for manufacturing the above-described high electron mobility transistor will be described in detail with reference to FIG.

As shown in FIG. 3(a), first, non-doped GaA
s layer 3 and an n layer with an impurity concentration of 2×10”/C−
-1caAs layer 4 to 500 and 400 people respectively
These two layers 3 and 4 are formed on the semiconductor substrate 2 so as to have a layer thickness of .

Further, on the n-AlGaAs1i4, a GaAs layer 5 with an impurity concentration of 2×10”/cnl,
AlGaAsN6 and GaAs layers 7 are sequentially formed to have a thickness of about 100, 30, and 2,500 layers, and the circumferences 5 to 7 of these layers are used as a first cap N8.

Furthermore, on the first camp layer 8, an impurity of 4 degrees 2×1
0I7/cI11 AlGaAs layer 9 and lXlO1
InGaAs layer 10 with an impurity concentration of 9/ci
The layers 9 and 10 are laminated in a layer 111I'I so as to have a thickness of about 30 and 2000, respectively, and these layers 9 and 10 are used as the second cap layer 11.

The above compound semiconductor layers are laminated by MBE method, MOCVD method, or the like.

Using the semiconductor substrate 2 that has undergone the compound semiconductor 4ili layer process in this way, a groove 13 for forming a gate electrode is formed.First, as shown in FIG. 3(a), the LnGaAs I 5iONIlff 21 is laminated on OO, and an organic resist 22 is applied thereon.

Then, by performing exposure processing and development processing on this resist 22, a window 2 is formed at a position above the gate electrode forming region 12.
3 and use it as a mask (see Figure 3(a)
)).

After this, the 5iON exposed through the window 23 of the resist 22 is
l! 21 was removed by reactive ion etching using gases such as CFa, NPi, and SPa, and further, C1l
.

and 1 (2) to form the best TnGaAs
After dry etching lm 10, the underlying Al
The GaAs layer 9 is wet-etched with ammonia (FIG. 3(b)).

The etched portion constitutes the upper part of the gate electrode forming groove 13 shown in FIG.

After completing the above etching process and stripping off the resist 22, 5iON is further laminated on top of it.
As the thickness of the 5iON film 21 on the surface of the nGaAs layer 10 increases, the GaAs exposed from the gate electrode forming groove 13 increases.
The surface of the layer 7 and the sidewall of the second cap layer 11 are 5iONJ.
l'! 21 (Figure 3 (C))
.

Next, in order to form the sidewalls 14 shown in FIG. 2, anisotropic etching is performed using CHF3-based gas, CF, and other gases to form the inner bottom of the gate electrode forming groove 13. 5i ONIPJ 21 is removed, and 5i is removed from the sidewall of the groove 13 formed in the second cap layer 11.
The ONW 121 is left (FIG. 3(d)).

The sidewall 14 thus formed prevents etching of the side part of the InGaAs layer 10 in the process described later, and also prevents the conductive material entering the gate electrode forming groove 13 from adhering to the inner wall of the first camp layer 8. He will be responsible for making this happen.

In this state, 5iONl desert 2 on TnGaAsnGa
1 will remain as a thin layer, so this 5iO
Using the N film 21 as a mask, the GaAs layer 7 above the first cap layer 8 is isotropically etched.

The etching is performed in a reduced pressure atmosphere of about 101 Pal using a mixed gas of CChFz and He, but under these conditions, the etching rate is lower than that of GaAs.
Since the etching rate of nGaAs and GaAs is large, AlG constituting the two cap layers 8.11
The aAs layer 6.9 is the G of the first and second cap layer 8.11.
It functions as an etching stopper for the aAs layer 5 and the InGaAs layer 10, and selectively etches only the upper GaAs layer 717 constituting the first cap layer 8.

As a result, the AlGaAs layer 6 underlying the GaAs layer 7 is exposed, and the GaAspl layer 6 is exposed by etching.
The width of the groove formed in the second cap layer 11 is wider than the gap formed by the sidewall 12 or the groove formed in the second cap layer 11 (FIG. 3(e)).
.

Next, the 5iON film 21 on the surface of the second cap layer 11 is removed by anisotropic etching using a CIIFI-based gas, a CP-based gas, or a CP-based gas. At this time, the upper part of the sidewall 14 made of 5iON is slightly removed (the third
Figure (f)).

After that, using the second cap layer 11 as a mask, the AlGaAs1 exposed from the gate electrode formation groove 13 is removed.
While removing W6 with ammonia, CCIJz
Using gas and He gas, the underlying GaAs layer 5 is
[Anisotropic etching in a reduced pressure of about Pal (3rd step)
Figure (g)).

This completes the process of forming the gate electrode forming groove 13.

Next, when a conductive metal such as aluminum or gold is sputtered toward the top of the semiconductor substrate 2 by a sputtering method, a vacuum evaporation method, etc., the InGaAs of the second cap N11 is
As a conductive metal film is deposited on the surface of 1 I O,
The conductive metal that has entered the gate electrode formation groove 13 deposits a conductive metal film on the surface of the n-AlGaAs layer 4 of the active layer 1 in a self-aligned manner.

In this case, in the gate electrode formation groove 13, the insulating sidewall 14 overhangs the underlying GaAs layer 7, so it acts as an eaves, and this GaAs
No conductive element is attached to the side wall of As'ffj1 (FIG. 3(h)).

For this reason, when the gate electrode 15 is formed thinner than the thickness of the GaAs layer 7, a conductive side wall as shown in FIG. 5, which connects the gate electrode 15 and the ohmic electrode 16, is not formed.

Furthermore, since no insulating film as shown in FIG. 6 is interposed between the gate electrode 15 and the ohmic electrode 16, the interval therebetween can be made extremely small, and the source resistance does not increase.

Then, the metal film deposited on the active layer 1 is connected to the gate electrode 15.
The metal film laminated on the second cap layer 11 is used as an ohmic electrode 16.

Note that the cap layer 1.2 in FIG. 2 is laminated with a compound semiconductor having a high impurity concentration, so that the source resistance does not become high.

(b) Description of other embodiments of the present invention In the embodiments described above, the case where electrodes were formed in a HEMT having a recessed structure was explained.
When an electrode is to be formed in a groove formed in a semiconductor device such as an FET, as shown in Figure 1, an eave A5 is formed on the upper part of the inner wall of the recessed groove to prevent conductive elements from adhering to the lower part. You can also do it like this.

In the above embodiment, GaAs, A
Although 1GaAs, 1nGaAs, etc. are used, other materials can also be used. In addition, in the above embodiment, the sidewall was formed of 5iON, but SiO
It is also possible to use an insulating material such as 1, 5iJ, etc. According to this, the insulating mask material used when forming the groove of the recessed structure can be used as it is as an eave.

[Effects of the Invention] As described above, according to the present invention, the second semiconductor layer formed on the substrate is etched to form the first opening, and the sidewall of the opening and the second semiconductor layer are etched. Using the insulating film formed thereon as a mask, the first semiconductor layer formed thereunder is isotropically etched to form a second opening, thereby forming a recessed structure of the semiconductor device;
Since the insulating film formed on the sidewall of the first opening is used as an eaves, when forming an electrode by sputtering or the like, a conductive film will not be formed on the sidewall at the bottom of the groove in the recessed structure. Short circuits between the electrodes formed on both sides and the electrodes formed in the groove can be prevented. Moreover, since no insulating film is formed on the top surface of the second semiconductor film, the distance between the electrode in the trench and the electrodes on both sides of the trench can be made extremely small, reducing the source resistance of the transistor and improving the characteristics of the semiconductor device. This makes it possible to improve the performance and achieve high integration.

Furthermore, since the insulating film used for the mask remains on the inner wall of the groove of the recessed structure, the amount of protrusion of the eaves can be increased, and the conductive film formed by sputtering etc. will adhere to the inner wall of the groove. This can be completely prevented.

[Brief explanation of the drawing]

Fig. 1(a) to <f> are diagrams of the principle of the present invention, Fig. 2 is a sectional view of an apparatus showing an embodiment of the present invention, and Fig. 3(a) to (h) are diagrams of the principle of the present invention. FIG. 4 is a cross-sectional view showing an ideal electrode formation state; FIG. 5 is a cross-sectional view showing a first example of a conventional device; FIG. FIG. 2 is a sectional view showing a second example of the conventional device. Process drawing box 3 showing an embodiment of the manufacturing method of the present invention in cross section
Figure (Part 2) Process diagram box diagram showing an embodiment of the manufacturing method of the present invention in cross section (Part 3)

Claims (1)

[Claims] A first etching step of sequentially stacking a first semiconductor layer and a second semiconductor layer on a semiconductor substrate and then etching the second semiconductor layer to form a first opening. forming an insulating film that covers the top surface of the second semiconductor layer and the sidewall of the second semiconductor layer exposed from the first opening; and using the insulating film as a mask to By isotropically etching the semiconductor layer and forming a second opening wider than the gap formed between the insulating films on the sidewalls of the second semiconductor layer, A second layer forming an eave made of the second semiconductor layer and the insulating film.
a third etching step in which the insulating film is anisotropically etched after the second etching step to leave the insulating film formed on the sidewall of the second semiconductor layer; A method for manufacturing a semiconductor device, comprising the step of depositing a conductive material from above the semiconductor substrate that has undergone an etching process to form an electrode on the bottom of the second opening and on the surface of the second semiconductor layer.