JPH02236673A - Logical circuit diagram verifying device - Google Patents

Abstract

PURPOSE:To easily verify a circuit diagram in a different describing system by selecting a verification object by rewriting the contents of the object to be stored into a rule storing means, extracting an attribute at every verification object, and verifying it. CONSTITUTION:The verification object, an attribute necessary for the verification concerning the object, etc., are stored into a rule storing means 6. The attribute concerning a part to be verified 14 designated by a rule storing means 16 is extracted, and it is compared with a parameter stored into the rule storing means 16. Consequently, by rewriting the contents of the object to be stored in the rule storing means 16, the part to be verified 14 can be selected. Further since the attribute is extracted and verified at every part to be verified 14, the said operation is made generally applicable. Thus the circuit diagram in the different describing system can be easily verified.

Description

[Detailed description of the invention] [Industrial field of application] This invention is applicable to CAE (Computer Aid).
LS produced by ed Englneer1ng)
The present invention relates to a verification device for logic circuit diagrams such as I, and particularly to one that efficiently verifies necessary items.

[Conventional technology] With the dramatic progress in semiconductor technology in recent years, concave circuits have become larger in scale, and their circuit designs have come to be performed using computers. Such a circuit design is
Normal C A E (Cosputer A1ded E
ng1neer1ng) device, and is performed while inputting data in an interactive format.

Furthermore, circuits fabricated using a CAE device must also be verified after fabrication. However, verifying large-scale circuits manually is extremely inefficient, so this verification is now being performed by computers to some extent. For example, checks for unconnected wiring, etc. are often made using log lags as pointed out by CAE equipment when creating circuit diagrams, and checks of various circuit operations are also performed by simulations in CAE equipment.

[Problem to be solved by the invention] However, circuits such as element attributes, fan-in (number of input signal lines that can be connected in parallel to a logic element, etc.), fan-out (number of input signal lines that can be connected in parallel to a logic element, etc.) There is a problem in that checking specific attributes is not general and cannot be easily performed using a computer. Also,
This can be checked by creating a program to check this, but this program lacks versatility and has problems such as being able to check only specific circuit diagrams.

In addition, although some verification devices that can verify large-scale circuits have been proposed, they may only be able to verify circuit diagrams using a specific description method, or the checking function may not work even after verification using other devices. There were problems such as not being able to make a selection and having to verify things that had already been verified again.

This invention was made with the aim of solving the above-mentioned problems, and one object thereof is to provide a logic circuit diagram verification device that can easily and accurately verify a necessary verification target. .

[Means for Solving the Problems] In order to solve the above-mentioned object, the present invention provides a logic circuit diagram creating means, and logic circuit diagrams created by the logic circuit diagram creating means, logic element attributes and each logic. A means for extracting circuit information to be verified, such as attributes of input/output terminals of elements, connection relationships between logic elements, etc., designating the target to be verified, and supplying parameters regarding the attributes of the pair I. It has a rule storage means, a means for extracting the attributes of the verification target stored in the rule storage means, and a means for comparing the extracted attributes and parameters to detect the suitability of the attributes, and for each verification target. It is characterized by performing verification.

[Operation] The logic circuit diagram verification device according to the present invention has the above-described configuration, and stores an object to be verified and attributes necessary for verification of the object in the rule storage means.

Then, the attributes of the specified verification target are extracted in the rule storage means and compared with the parameters stored in the rule storage means.

Therefore, the verification target can be selected by rewriting the contents of the target stored in the rule storage means.

Furthermore, since attributes are extracted and verified for each verification target, its operation is versatile, and circuit diagrams with different description methods can be verified easily.

[Embodiment] Hereinafter, a logic circuit diagram verification device according to an embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing a schematic configuration, and a circuit diagram production section 10 and a circuit diagram data file 12 that stores a circuit diagram produced by this circuit diagram production section correspond to a normal CAE apparatus. The circuit diagram verification device according to the present invention is usually built into a CAE device as hardware, and can utilize the CPU of the CAE device (circuit diagram creation section 10), but the circuit diagram verification device according to the present invention is operated by a dedicated program. part 14
and a rule file 16 that supplies rules to the verification section 14.

The verification result in the verification section 14 is output to the error table 18, and the verification section 14 also accesses the correction command file according to the result. That is, the verification section l4 accesses the modification command file 20, reads the corresponding modification command, and supplies it to the circuit diagram production section 10, depending on the type of error obtained through verification. Therefore, the circuit diagram creation section 10 can modify the circuit diagram according to the supplied modification command.

Next, the operation of the verification section 14 will be explained based on FIG.

The verification section 14 extracts connection information necessary for verification from the circuit diagram data stored in the circuit diagram data file 12, and reads this (S1).

Here, this connection information includes the name of the element, the attributes of the element, the name of the net connected to the input and output ends of the element, the connection destination of the net, the fan-in value of the input end of the element, and the fan-out of the output end of the element. value etc.

Next, the verification section 14 reads verification items (check items and parameters such as attribute values in the check items) from the rule file 16. Here, it is necessary to write check items and parameters in the leakage file 16 in advance. Normally, the information is written using a keyboard or the like in the CAE device. Since check items can be freely selected when writing to the rule file 16, only necessary items can be specified. For example, if you only want to check the attributes of an element, you only need to write this.

In the example shown in FIG. 2, the attributes of the element and the attributes of the terminals to which nets such as fan-in and fan-out are attached are checked.

In this example, in order to first check the element attributes, the element attributes are extracted from the connection information (S3
). That is, attributes about the element such as the name of the element (element name) and which library the element belongs to are extracted.

Next, the extracted attribute is compared with the parameter Z regarding the element attribute read from the rule file 16 (S4). Here, this attribute is, for example, the name of the element, and according to the example of the logic circuit diagram shown in FIG.
ND1 to ND4 are its attributes.

Then, if the attribute is incorrect, the fact that there is an error in that attribute is output to the error table 18, and a correction command is supplied to the circuit diagram production unit 10 (S5).

After outputting this error, or if attributes such as element names are correct, it is verified (checked) whether attributes have been checked for all elements (S6). If all elements are not checked, extract element attributes (
In order to return to S3), the attributes of all elements are checked.

In this way, element attributes are checked for all elements, and when an error occurs, information about it is output to the error table 18, and the circuit diagram can also be corrected using a correction command.

Next, while other verification targets are verified, attributes of terminals to which wiring (nets) are attached are extracted (S7). Here, the attributes of this terminal are the fan-in value at the input terminal and the fan-out value at the output terminal of the logic element shown in FIG. These fan-ins, fan-outs 1.
Since the value is determined by the capability of the element, it is uniquely determined by the element name.

When the attributes of the terminal are extracted in this way, the attributes are then verified (checked) (S8).

That is, as described above, the attributes of the terminals are determined by the elements, so these are written in the rule file 1 as parameters for each element. Therefore, by comparing this parameter with the number of nets actually connected to that terminal, it is possible to judge whether fan-in or fan-out is correct or not. Therefore, the verification section 14 verifies attributes (eg, fan-in, fan-out) by counting the nets connected to terminals in the circuit diagram and comparing this with parameters.

If an error occurs, for example, if the number of nets connected to a terminal in the circuit diagram exceeds the fan-in or fan-out values, an error command and correction command are output (S9
)L, if there is no error, the process moves directly to checking whether all the nets have been checked (S10). Then, to repeat this until all Ne Sotos are covered,
All terminals can be verified.

In this way, fan-in, fan-out, etc. can be verified. For example, in the case of a logic circuit as shown in FIG. 4, the fan-out value of the element SDI is "2".
is set to . However, the net N1 connected to the output terminal of this element NDI is connected to two NAND circuits and one inverter, and the fan-out value in this circuit is "3". Therefore, the verification section 14 can detect this as an error in the attribute checking step (S8) in the above operation, output it to the error table 18, and supply a correction command to the circuit diagram production section 10 (S9).

As described above, according to this embodiment, the check items described in the rules act as switches in the operation of the verification section, and only the check items can be verified. Therefore, by changing the description in the rule table 16, it is possible to arbitrarily set the items to be verified. Therefore, unnecessary verification operations can be omitted. Furthermore, changes in LSI type (technology) and post-process C A D (CoII puter aided
Dcslgn ) can also be dealt with flexibly by changing the rule description.

In addition to the above example, verification items include oven pin check to detect unconnected output terminals, floating bin check to detect unconnected input terminals, floating net check to detect unconnected wiring, etc. be.

[Effects of the Invention] As explained above, according to the logic circuit diagram verification device according to the present invention, the verification target can be selected by rewriting the content of the target stored in the rule storage means. Effects can be obtained. Furthermore, since attributes are extracted and verified for each verification target, the operation is versatile, and circuit diagrams with different description methods can be easily verified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a logic circuit diagram verification device according to an embodiment of the present invention, FIG. 2 is a flow chart for explaining the operation of the same embodiment, and FIG. FIG. 4 is a circuit diagram showing another example of a logic circuit diagram to be verified. 10... Circuit diagram creation section 12... Circuit diagram data file 14... Verification section 16... Rule file (rule storage means) 18
...Error table

Claims (1)

[Claims] (1) Logic circuit diagram creation means; Verification of logic element attributes, attributes of input/output terminals of each logic element, connection relationships between each logic element, etc. from the logic circuit diagram created by this logic circuit diagram creation means. a means for extracting circuit information to be verified; a rule storage means for specifying a target to be verified and supplying parameters regarding attributes of the target; and a means for extracting circuit information to be verified; A logic circuit diagram verification device comprising: means for extracting; and means for comparing the extracted attributes and parameters to detect suitability of the attributes, and performing verification for each verification target.