JPH0223666A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0223666A JPH0223666A JP17412388A JP17412388A JPH0223666A JP H0223666 A JPH0223666 A JP H0223666A JP 17412388 A JP17412388 A JP 17412388A JP 17412388 A JP17412388 A JP 17412388A JP H0223666 A JPH0223666 A JP H0223666A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- gate
- trench
- diffusion layer
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 3
- 238000009792 diffusion process Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、トレンチ・ゲートＭＯＳ ゲート電極配線構造に関する。[Detailed description of the invention] [Industrial application field] The present invention is a trench gate MOS This invention relates to a gate electrode wiring structure.
ＦＥＴの
［従来の技術］、
従来、トレンチ・ゲー）ＭＯＳ ＦＥｊＴの要部の断
面（イヴ造は、第３図に示す如き構造であった。[Prior art] FET (conventional technology, trench gate) A cross section of the main part of a MOS FEjT (Ives structure had a structure as shown in FIG. 3).
すなわち、Ｓｉ基板２１０表面にはトレンチ・ゲートと
なるべき位置にトレンチ（溝）が形成され、該溝内にゲ
ート酸化膜２２が形成され、該溝内に多結晶Ｓｉより成
るゲート電極２３が少なくとも埋め込まれて成り、前記
８１基板の表面で、トレンチ・ゲートの両側にソースあ
るいはドレインと成る拡散層２４．２４’が形成されて
成り、該拡散層２４．２４’とゲート電極２３とはゲー
ト酸化膜２２を介して重ね合わされて成るのが通例であ
った。That is, a trench (groove) is formed on the surface of the Si substrate 210 at a position to become a trench gate, a gate oxide film 22 is formed in the groove, and a gate electrode 23 made of polycrystalline Si is formed in the groove. On the surface of the substrate 81, diffusion layers 24 and 24', which serve as sources or drains, are formed on both sides of the trench gate. It was customary to overlap them with a membrane 22 in between.
［発明が解決しようとする課題］
しかし、上記従来技術によるとゲート電極と拡散層とが
、とりわけドレイン拡散層とが誘電体膜をはさんで容量
結合することとなり、トランジスタの速度を定めるτ二
ＯＲ式（τ：速度、Ｃ：容量、Ｒ：抵抗）の内 Ｃを大
きくする事となり、トランジスタの速度を遅くすると云
う課題があった。[Problems to be Solved by the Invention] However, according to the above-mentioned conventional technology, the gate electrode and the diffusion layer, especially the drain diffusion layer, are capacitively coupled with each other across the dielectric film, and the τ2 which determines the speed of the transistor is This resulted in the problem of increasing C in the OR equation (τ: speed, C: capacitance, R: resistance) and slowing down the speed of the transistor.
本発明は、かかる従来技術の課題をなくする新しいトレ
ンチ・ゲー）ＭＯＳ ＦＥＴのゲート構造を提供する
事を目的とする。It is an object of the present invention to provide a new trench MOS FET gate structure that eliminates the problems of the prior art.
［課題を解決するだめの手段］
上記課題を解決するために、本発明は、半導体装置に関
し、トレンチ・ゲートＭＯ８ＦＦ１Ｔのゲート電極をソ
ース及びドレイン拡散層領域と重ね合わせ無く形成する
領域を有する様に形成する手段をとる。[Means for Solving the Problems] In order to solve the above problems, the present invention relates to a semiconductor device having a region where the gate electrode of the trench gate MO8FF1T is formed without overlapping with the source and drain diffusion layer regions. Take steps to form.
［実施例］ 以下、実施０例により本発明を詳述する。[Example] The present invention will be explained in detail below using Example 0.
第１図は本発明の一実施例を示すトレンチ・ゲ−）ＭＯ
Ｓ １’ＥＴの要部の断面図である。すなわち、Ｓｉ
基板１の表面には、トレンチ・ゲート部にトレンチが形
成され、該トレンチの内壁にゲート酸化膜２を形成し、
次でゲート電極６をａＶＤ法にて多結晶Ｓｉを埋め込ん
で形成すると共に、周辺は酸化膜で被覆されているので
、該酸化膜をマスクとしながら、ゲート電極の一部をホ
トレジストの窓開は部から拡散層の深さ寸法のみ深めに
エツチングし、ゲート電極６となし、次で拡散層４，４
′をイオン打込み等により形成する事により、ゲート電
極乙の一部又は全部が拡散層４゜４′と重ね合わせが無
い様に形成する事ができる第２面は、本発明の他の実施
例を示すトレンチ・ゲー）ＭＯＳ ＦＥＴの要部の断
面図である。Figure 1 shows an embodiment of the present invention.
It is a sectional view of the main part of S1'ET. That is, Si
A trench is formed in the trench gate portion on the surface of the substrate 1, and a gate oxide film 2 is formed on the inner wall of the trench.
Next, the gate electrode 6 is formed by embedding polycrystalline Si using the aVD method, and since the periphery is covered with an oxide film, using the oxide film as a mask, a part of the gate electrode is opened in the photoresist. Only the depth of the diffusion layer is etched from the bottom to form the gate electrode 6, and then the diffusion layers 4, 4 are etched.
The second surface, which can be formed so that part or all of the gate electrode B does not overlap with the diffusion layer 4°4' by forming the gate electrode B by ion implantation or the like, is another embodiment of the present invention. FIG. 2 is a sectional view of a main part of a trench MOS FET.
すなわち、Ｓｉ基板１１の表面にはトレンチ・ゲートと
なる部分にトレンチが形成され、該トレンチ内壁にゲー
ト酸化膜１２が形成されると共に、次で、多結晶Ｓｉを
ＯＶＤ法等によりトレンチ内を埋め込むと共に８１基板
１１の表面にも形成し、該多結晶Ｓ１をイオン打込みに
より拡散層となした後、ホトエツチングによりゲート電
極１３と拡散層１４．１４’とを重ね合わせ無く形成し
たものである。That is, a trench is formed on the surface of the Si substrate 11 in a portion that will become a trench gate, and a gate oxide film 12 is formed on the inner wall of the trench, and then polycrystalline Si is filled in the trench by an OVD method or the like. 81 is also formed on the surface of the substrate 11, the polycrystal S1 is formed into a diffusion layer by ion implantation, and then the gate electrode 13 and the diffusion layers 14 and 14' are formed without overlapping by photo-etching.
［発明の効果］
本発明により、ゲート電極と少くともドレイン拡散層と
の重ね合わせ部が減少し、重ね合わせに伴う容量の減少
による速度向上を計ることができる効果がある。[Effects of the Invention] According to the present invention, the overlapping portion between the gate electrode and at least the drain diffusion layer is reduced, and the speed can be improved due to the reduction in capacitance caused by the overlapping.
第１図及び第２図は本発明の実施例を示す要部の断面図
であり、第６図は従来技術を示す要部の断面図である。
１、ｉｉ、、２１・・・・・・・・・Ｓ１基板２．２１
，２２・・・・・・・・・ゲート酸化膜３．１３，２３
・・・・・・・・・ゲート電極１１ 、４’ 、 １
４ 、１４’・・・・・・拡散層以上1 and 2 are sectional views of essential parts showing an embodiment of the present invention, and FIG. 6 is a sectional view of essential parts showing a conventional technique. 1, ii, 21...S1 board 2.21
, 22... Gate oxide film 3.13, 23
......Gate electrode 11, 4', 1
4, 14'.......Diffusion layer or higher
Claims (1)
ース及びドレイン拡散層領域と重ね合わせ無く形成され
た領域を有する事を特徴とする半導体装置。A semiconductor device characterized in that a gate electrode of a trench gate MOSFET has a region formed without overlapping source and drain diffusion layer regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17412388A JPH0223666A (en) | 1988-07-12 | 1988-07-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17412388A JPH0223666A (en) | 1988-07-12 | 1988-07-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0223666A true JPH0223666A (en) | 1990-01-25 |
Family
ID=15973053
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17412388A Pending JPH0223666A (en) | 1988-07-12 | 1988-07-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0223666A (en) |
-
1988
- 1988-07-12 JP JP17412388A patent/JPH0223666A/en active Pending
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