JPH02236621A - Image forming device - Google Patents

Abstract

PURPOSE:To transfer a multilevel image with the interface of a binary image by generating a pulse width modulation signal based on multivalue data converted by a means to convert inputted serial data to parallel data based on the bits of the multivalue data, and forming a visible image. CONSTITUTION:A shift register 1 shifts the bit information of the serial data inputted from Q0 to Q3 synchronizing inputted serial data with its transfer clock, however, since a write pulse signal 5 is outputted from a transfer pulse generation circuit 4 at every clock, data at every four bits {a, b, c, d}, {e, f, g, h}... is written on a line buffer 2. And the data of four bits written on the line buffer 2 is inputted to a PWM circuit(pulse width modulation circuit) 135 on occasion, and signals whose pulse width are modulated corresponding to 16 gradation are formed, and is inputted to a laser driving circuit 136. Thereby, it is possible to perform the transfer of the multilevel image with the interface of the binary image, and to form the image.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image forming apparatus, and more particularly, to an image forming apparatus that inputs multivalued data and forms a visible image. [Prior Art] A laser beam printer is a typical device of this type. FIG. 5 shows the structure of an image forming system in a general laser beam printer.

In the figure, 121 is an image signal (video signal), which is an ON state of a laser beam 123 generated from a laser unit 122.
/OFF is controlled. 124 is a rotating polygon mirror (so-called polygon mirror), which is rotated by a motor 124 at a constant speed.

The laser beam is reflected by one side of the rotating polygon mirror, and the reflected laser beam passes through the imaging lens 126 and scans the photosensitive drum 128 in the horizontal direction as shown at 127 in the figure. scan).

129 is a beam detector, which includes a photoelectric conversion element 130,
For example, it has a photodiode and generates a timing signal (BD signal) 131 for reading out an image and outputting it as a video signal by irradiation using a rasp scan.

Reference numeral 132 is a transfer paper, on which a toner image obtained by developing an electrostatic latent image formed on the transfer drum 128 by a developing device (not shown) is transferred by a transfer device (not shown). Thereafter, the image is output as a print result to an external device via a known fixing device. In such a laser beam printer, in order to form an image by the rask scan, it is necessary to transfer the image in synchronization with a horizontal synchronization signal such as a BD signal.

Next, the image transfer will be explained.

Figure 6 shows the structure related to image transfer in a multilevel image forming device. The image developed in the bitmap memory of an external image processor (not shown) is transferred to the line buffer (of this device) as image data l37 (several bits) in synchronization with the BD signal.
FIFO).

The transfer at this time is performed in synchronization with the transfer clock 134. The image taken into the line buffer 133 is read out in synchronization with an internal image clock and input to a PWM circuit (pulse width modulation circuit) 135. This circuit generates a pulse width signal 13B according to the value of the multivalued data, and outputs the pulse signal to the laser drive circuit 136. This signal corresponds to the video signal 121 described earlier. P.W.
The internal configuration and operation of the M circuit 135 will be explained using FIG. Image data 13 read from line buffer 133
7° is input to a look-up table (hereinafter referred to as LUT) 140 in synchronization with the image clock 139, and gradation correction is performed here. This LUT 140 is, for example, a ROM
The data is converted to obtain appropriate density correction characteristics. The corrected image data 141 is then sent to a D/A converter 142.
The analog signal 143 is converted into an analog signal 143 corresponding to digital image data, and is input to the negative terminal of a comparator 144 .

On the other hand, the timing generation circuit 145 generates a timing signal 146 that is synchronized with the BD signal 131 and an image clock 139 that is formed based on, for example, the BD signal. The triangular wave generation circuit generates a triangular wave signal 147 according to this timing signal 146 and outputs it to the positive terminal of the comparator 144.

The relationship between the input signal and output signal of the comparator 144 is shown in FIG. As shown in the figure, the comparator 144 compares the input analog signal 143 and the triangular wave signal 147, and when the level input to each input terminal is in accordance with the logic, that is, the level of the triangular wave signal 147 is equal to that of the analog signal 147. The output is set to “1” only when the level is higher than the level of 143.
(true) ". This generates a pulse width modulated signal 138. [Problem to be solved by the invention] By the way, in an apparatus that inputs such a multivalued image and forms an image, Signal lines related to image transfer from external equipment are required at least as many as the number of bits of the multilevel data.

This creates a problem in that the hardware is completely different from the conventional interface for binary image formation using a single image signal line, and the interface cannot be used in common. The present invention has been made in view of such problems, and it is an object of the present invention to provide an image forming apparatus that can transfer multivalued images using a substantially binary image interface.

[Means for Solving the Problem] and [Operation] The image forming apparatus of the present invention that solves this problem has the configuration shown below. That is, in an image forming apparatus that forms a corresponding visible image based on multi-value data input from the outside, an input means for inputting the multi-value data that has been serially transferred, and a bit of the multi-value data that is input serial data. It is equipped with a conversion means for converting into parallel data based on a number, and generates a pulse width modulation signal based on the multivalued data converted by the conversion means to form a visible image. [Examples] Examples according to the present invention will be described in detail below with reference to the accompanying drawings.

Description of the first embodiment (Figs. 1 and 2)> Fig. 1 shows the configuration of the control system of the laser beam printer in the first embodiment, and Fig. 2 shows the configuration of the control system of the laser beam printer in the first embodiment. A timing chart is shown.

In this embodiment, a case will be described in which a visible image is formed based on 16-gradation image data. Image data is transferred from an external device (not shown) in synchronization with the transfer clock. In order to perform serial-to-parallel conversion, the shift register l shifts bit information in the transferred serial data in synchronization with the transfer clock. A frequency divider 3 and a pulse generation circuit 4 generate a write pulse signal 5 for writing converted parallel data (4 bits) into a line buffer memory (FIFO) 2 based on the transfer clock. The shift register 1 shifts the bit information of the input serial data, such as Q o - Q s, in synchronization with the transfer clock of the input serial data.
Since the transfer pulse generation circuit 4 outputs the write pulse signal 5 every 4 clocks, (a.b, c, d), (
e, f, g, h) - will be written to line buffer 2 every 4 bits. The 4-bit data written to line buffer 2 is always P
The signal is input to the WM circuit 135, generates a pulse width modulated signal corresponding to 16 gradations, and is input to the laser drive circuit 136. In the laser drive circuit 136, the laser unit 1
22, and form a visible image using a known printing system. <Description of the second embodiment (Fig. 3)> The second embodiment will be explained according to Fig. 3. In the figure, like the shift register 1 in the first embodiment, 6 is a shift register that shifts input image data in 1-bit units in synchronization with the transfer clock and outputs the shifted image data, as shown in the figure. It is possible to output 8 bits.

7 is a CPU that controls the entire printing apparatus, and includes a programmable frequency divider 8 and a mask circuit 9 (as shown in the figure).
(consisting of D gates). The rest of the configuration is the same as that of the first embodiment, so a detailed explanation will be omitted. Note that the programmable frequency divider can be constructed with a simple counter due to its nature.

Now, in the illustrated configuration, the CPU 7 is capable of inputting data ranging from 16 to 256 gradations. For example, when inputting 32 gradation data, that is,
When assigning 5 bits to each pixel, the procedure is as follows. In this case, the programmable frequency divider 8 is set to generate a write pulse signal every 5 clocks of the transfer clock,
In addition, the mask circuit 9 may be configured to mask bits 5 to 7. Incidentally, by adding the remaining three AND gates to the mask circuit 9,
By making it possible to arbitrarily mask bits 1 to 7 excluding the LSB (bit 0) of the output of the shift register 6, it becomes possible to capture data with 2 tones (binary data) to 256 tones. Also, although the explanation is complicated, the voltage value converted by the D/A converter (not shown) in the PWM circuit 135 can be changed based on the number of captured bits (number of gradations). do.

For example, when the input data is 4 bits (16 gradations), the line buffer memory 2 ends up with OOH to OOH.
Since data in the range of FH (H indicates a hexadecimal number) will be written, this range is used to convert into digital analog data and perform PWM conversion. Specifically, the conversion range of the A/D converter may be changed, or the immediately preceding correction lookup table may be stored in RAM, and the contents of the table may be rewritten.

<Explanation of Embodiment 3 (Fig. 4)> The third embodiment will be explained according to Fig. 4. The first mentioned above
In the second embodiment, multivalued data was converted from serial to parallel using a shift register.

However, this method cannot be applied to the transfer of binary data from an image processor that has an interface that does not have a transfer clock. Therefore, in order to enable such data transfer from the image processor, as shown in the figure, under the control of the CPU 7, the transferred shift register l1 line buffer 2 and the PWM circuit 135
A switch 1o is provided to select between the signal obtained through the switch and the transferred binary data itself. This results in
It also becomes possible to interface with image processors that handle conventional binary images. Note that this switching can be done by instructing the cPU 7 using a manual switch (not shown) provided outside the device 9. As explained above, according to this embodiment, if there is at least one data line and a transfer clock line, multi-level data can be transferred and images can be reproduced. In other words, multilevel data can be transferred simply by providing a transfer clock line to the conventional interface for binary image data. Furthermore, as explained in the third embodiment, by having the function of switching between the multi-value data transfer method and the conventional binary data transfer method, data transfer can be performed using a compatible multi-value interface. It's convenient.

Although the embodiments have been described using a laser beam printer employing a PWM method as an example, it is needless to say that the present invention is not limited to this. The point is that any device that inputs multivalued data and forms an image will suffice. [Effects of the Invention] As explained above, according to the present invention, multivalued images can be transferred and formed using essentially a binary image interface.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the print control system in the first embodiment, Fig. 2 is a timing chart for explaining the operation in the first embodiment, and Fig. 3 is the print control system in the second embodiment. FIG. 4 is a block diagram of the printing control system in the third embodiment. FIG. 5 is a diagram showing the configuration of the printing system of a general laser beam printer. FIG. 6 is a conventional printing control system. FIG. 7 is a diagram for explaining the configuration for pulse width modulation, and FIG. 8 is a timing chart for generating a pulse width modulation signal. In the figure, 1.6... Shift register, 2... Line buffer, 3... Frequency divider, 4... Pulse generation circuit, 7
... cpu, s... programmable frequency divider, 9...
-Mask circuit, 10...switch.

Claims (1)

[Scope of Claims] An image forming apparatus that forms a corresponding visible image based on multi-value data input from the outside, comprising: input means for inputting the multi-value data that has been serially transferred; An image comprising a conversion means for converting value data into parallel data based on the number of bits of the value data, and generating a pulse width modulation signal based on the multi-value data converted by the conversion means to form a visible image. Forming device.