JPH02234466A - Semiconductor memory cell and manufacture thereof - Google Patents

Abstract

PURPOSE:To maintain a large capacitance by a method wherein an information storing part is formed along an insulating film formed on the sidewall of a trench formed on a semiconductor substrate, the bottom of the trench and an insulated-gate field effect transistor. CONSTITUTION:A capacitance part is composed of a cell plate 10, a charge storing electrode 8 and a capacitive insulating film 9 isolating them from each other which are buried in a trench formed on a silicon substrate 1. A silicon oxide film 7 is provided between the charge storing electrode 8 and the sidewall of the trench. The silicon oxide film 7 is also provided between the charge storing electrode 8 and a first interlayer insulating film 6. A diffusion layer 12 is formed in the bottom of the trench by impurity diffusion from the charge storing electrode 8. The cell plate 10 is isolated from a bit line 14 by a second interlayer insulating film 11. Element isolation is provided by a silicon oxide film 2 formed on the silicon substrate 1. As the charge storing electrode 8 is not only formed in the trench but also extended over a switching transistor, a required capacitance can be obtained with a small cell area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a one-transistor/one-capacitor type semiconductor memory cell suitable for large-scale storage and a method for manufacturing the same. [Prior Art] Starting with the release of IK-bit dynamic random access memory in 1970, MOS dynamic memory has expanded in scale by a factor of four in the last three years, and the area of its memory cells has increased. It has been reduced by 0.3 to 0.4 times in one generation. Ensuring cell capacity is an important issue from the perspective of maintaining soft error resistance even when memory cells are reduced in size.

IEICE Technical Report [Silicon Materials and Devices] SDM88-39, which explains how to solve this problem.
On page 53, there is a method presented under the title ``16 megabit DRAM process technology.'' In this method, as shown in FIG. 3, a capacitor portion including a charge storage electrode 8 is buried in a trench formed in a silicon substrate 1, thereby securing the capacitance without increasing the cell area.

[Problem to be solved by the invention]

In such a structure, in order to reduce the cell area while securing the capacity necessary for memory operation, a technique for forming a deep trench with a small opening area is required. However, such groove processing cannot be realized because it causes problems such as damage to the silicon substrate and collapse of the groove formation. Therefore, reduction of the cell area in such a structure is limited by the limitations of processing technology. Furthermore, leakage between capacitances due to the narrowing of the memory cell spacing becomes an important problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory cell and its structure method that can secure a larger capacity and suppress leakage between trench capacitances without increasing the area of the memory cell.

[Means to solve the problem]

The semiconductor memory cell of the present invention has a capacitor and an insulated gate field effect transistor serving as an information storage section, in which the information storage section includes an insulating film attached to a side wall of a trench formed in a semiconductor substrate. The groove is formed along the bottom of the trench and above the insulated gate field effect transistor.

The method for manufacturing a semiconductor memory cell of the present invention includes the steps of digging a groove in a semiconductor substrate for an insulated gate field effect transistor, and a continuous information storage portion on an insulating film on the inner surface of the groove and on the insulated gate field effect transistor. The structure includes a step of providing a capacitance that becomes .

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view of one embodiment of a memory cell of the present invention.

A field effect transistor is constituted by two heavily doped diffusion layers 5 formed on a silicon substrate 1 and functioning as source/drain regions, and a gate electrode 4 laminated with a gate oxide film 3 interposed therebetween. This gate electrode 4 is embedded in the first interlayer insulating film 6. Further, one of the two high concentration diffusion layers 5 is connected to the bit line 14 through a contact hole formed in the first interlayer insulating film 6.

The capacitor section includes a cell plate 10 embedded in a cell formed on a silicon substrate 1 and a charge storage capacitor 8i! A silicon oxide film 7 is interposed between the charge storage electrode 8 and the first interlayer insulation film, and a silicon oxide film 7 is interposed between the charge storage electrode 8 and the first interlayer insulation film. An oxide film 7 is present. At the bottom of the groove, there is a diffusion layer 12 formed by diffusing impurities from the charge storage electrode 8 . Further, the cell plate 10 and the bit line 14 are isolated by a second interlayer insulating film 11, and element isolation is performed by a silicon oxide film 2 formed on the silicon substrate 1.

As will be explained later, the charge accumulation electrode 8 is a processed polycrystalline silicon layer extending from above the element isolation region to above the field effect transistor, including the inner surface of the groove. FIGS. 2A to 2F are cross-sectional views shown in order of steps for explaining an embodiment of the method for manufacturing a memory cell of the present invention.

Hereinafter, for convenience of explanation, an example using an n-channel type transistor will be shown. To make a p-channel type, the conductivity types of the silicon substrate and the diffusion layer may be reversed from those of the n-channel type.

First, as shown in Figure 2 (a), the surface orientation is <100)p
A mask oxide film 16 with a thickness of about 40 nm is formed on the mold silicon substrate 1 by thermal oxidation, then a silicon nitride film 17 is deposited with a thickness of about 120 nm by CVD, and a photolithography technique is used to deposit the mask oxide film 16 on the element region. After patterning so that mask oxide film 16 and silicon nitride film 17 remain, thermal oxidation is performed to form silicon oxide film 2 with a thickness of about 600 nm. Next, as shown in FIG. 2(b), the silicon nitride film 17
After removing the mask oxide film 16 by wet etching, it is thermally oxidized at 950°C in an elementary atmosphere to a thickness of about 20 nm.
A gate oxide film 3 having a thickness of m is formed. Next, a polycrystalline silicon film is deposited to a thickness of about 500 nm by CVD, and a gate electrode 4 is formed by ordinary photolithography. Next, arsenic was applied to the n-MOSFET region at an acceleration energy of 100 keV and a dose of 5×1015c.
m −2 is implanted to form an n-type high concentration diffusion layer 5.

Next, as shown in FIG. 2(c), the gate oxide film j directly under the gate electrode 4 is left, and other parts are wet-etched. Next, a silicon oxide film is deposited by the CVD method to form the first interlayer insulating film 6. Next, a pattern of the resist 23 is formed using a normal photolithography technique.

Next, as shown in FIG. 2(d), grooves 24 are formed by anisotropic etching using the resist 23 as a mask, and a silicon oxide film 7 is formed on the entire surface of the wafer including the inner surface of the grooves 24 by CVD. Deposit. Next, a silicon oxide film 7 is deposited by photolithography. Next, a resist 26 is formed by photolithography.

Next, as shown in FIG. 2(e), the silicon oxide film 7 and the first interlayer insulating film 6 are anisotropically etched using the resist 26 as a mask. Next, after depositing a polycrystalline silicon layer 27 by the CVD method, arsenic ions are implanted through the polycrystalline silicon layer 27. Arsenic diffuses into the bottom of 1I24, forming a diffusion layer 12. Next, as shown in FIG. 2(f), a polycrystalline silicon layer 2
7 is etched using photolithography and dry etching techniques to form a charge storage electrode 8. A capacitive insulation M9 of a thermal oxide film is formed on the charge storage electrode 8 by thermal oxidation. A polycrystalline silicon film is deposited thereon by CVD and patterned by photolithography and dry etching to form cell plate 10.

Next, a second interlayer insulating film 11 of a silicon oxide film is deposited by the CVD method, a contact hole is made, and a bit line 14 is formed of aluminum, thereby obtaining a memory cell having the structure shown in FIG.

In the memory cell obtained in this example, the charge storage electrode extends not only inside the trench but also over the switching transistor, so the desired capacity can be obtained with a small cell area, and the charge storage electrode Since it is insulated from the storage NI electrode via silicon oxide M7, interference between cells can also be suppressed.

In the above embodiment, a silicon thermal oxide film was used as the capacitor insulating film, but for the main purpose of increasing the capacitance value and improving reliability, either a silicon oxide film, a silicon nitride film, or both were used. It goes without saying that a one-layer to three-layer structure may be formed using the above.

〔Effect of the invention〕

As explained above, according to the present invention, the charge storage electrode, which is a component of the capacitor section, extends continuously from within the groove onto the switching transistor, thereby ensuring a large capacitance with a small memory cell area. can. Furthermore, since an insulating film is attached to the sidewalls of the groove in which the charge storage electrode is embedded, the structure is such that interference between cells is unlikely to occur even if the gap between the cells is small. Furthermore, since the junction between the switching transistor and the charge M product electrode, that is, the so-called cell contact, can be formed by a self-alignment line, an advantageous effect can be obtained in reducing the memory cell area.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of one embodiment of the memory cell of the present invention, and FIG.
Figures (a) to (f) are cross-sectional views showing one embodiment of the method for manufacturing a memory cell of the present invention, and FIG. 3 is a cross-sectional view of an example of a conventional memory cell. 1...p-type silicon substrate, 2...silicon oxide film,
3... Gate oxide film, 4... Gate electrode, 5...
High concentration diffusion layer, 6... First interlayer insulating film, 7... Silicon oxide film, 8... Charge storage electrode, 9... Capacitive insulating film, 10... Cell plate, 11... Second interlayer insulating film, 12... Diffusion layer, 14... Bit line, 16...
・Mask oxide film, 17...Silicon nitride film, 24...
- Groove, 27... polycrystalline silicon layer, 30... interlayer insulating film, 37... diffusion layer.

Claims (2)

[Claims] (1) In a semiconductor memory cell having a capacitor and an insulated gate field effect transistor serving as an information storage section, the storage section includes an insulating film attached to a side wall of a trench formed in a semiconductor substrate and a bottom of the trench. A semiconductor memory cell, characterized in that it is formed along the insulated gate field effect transistor. (2) a step of providing an insulated gate field effect transistor on a semiconductor substrate; a step of digging a trench in the silicon substrate; a step of forming an insulating film only on the side walls of the trench; and a step of forming an insulating film on the inner surface of the trench. and providing a capacitor serving as a continuous information storage section on an insulated gate field effect transistor.