JPH0223439A - Data processor - Google Patents

Abstract

PURPOSE:To eliminate the overhead of a CPU by providing a calculating circuit to beforehand store the peak address of a circulating buffer, area length and the number of areas, operate the address of an area processed by a CPU and deliver it to the CPU. CONSTITUTION:A CPU 1 writes the information such as the peak address of a circulating buffer 4, the length of an area and the number of areas beforehand to an address calculating circuit 6. Next, the CPU 1 receives the address of an area to be processed from the circuit 6 and processes the contents of the area corresponding to it. When this is completed, the CPU 1 gives the instruction of the processing completion to the circuit 6, the circuit 6 calculates the address of the area to be next processed by the CPU 1 and outputs it to the CPU 1 based on the peak address of the buffer 4, the length of the area and the number of the areas. Thus, the burden of the CPU 1 is decreased, and the overhead of the CPU can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device that uses part of a RAM area as a circular buffer.

[Conventional technology]

Figure 3 is a configuration diagram of a conventional general data processing device. A RAM that can read and write data is used as a buffer to temporarily hold the above data when performing
4 is a circular buffer which is a part of the area within RAMa. This circular buffer 4 is divided into a plurality of areas 5 having a constant length.

Next, the operation will be explained with reference to FIG.

First, the CPUI reads the next area address (NA) saved in a fixed area in RAMa (S21).

After reading the next area address (NA), the CPU
1 processes the contents of the area starting from this next area address (NA) (S22).

When this process is completed, the CPU 1 checks whether the next area address (NA) is the address of the last area of the circular buffer 4 (S23).

Here, if the next area address (NA) is not the address of the last area, the next area address (NA)
) is added with fixed & (X) and saved in a fixed area in RAMa as the next next area address (NA) (S24).

Also, if the next area address (NA) is the address of the last area, the next area address (NA)
is the starting address of the circular buffer 4, and this starting address is saved in a fixed area (S25).

In this way, CPU 1 processes the contents of the circular buffer in order starting from the first area, and the area becomes circular buffer 4.
When it reaches the end, it returns to the first area and repeats the process.

[Problem to be solved by the invention]

As explained above, in conventional data processing devices, each time the CPU processes the contents of a circular buffer area, it calculates the address of the next area to be processed, which poses a problem in that it places a heavy burden on the CPU and causes overhead. Ta.

This invention was made to solve the above problems, and aims to lighten the load on the CPU and eliminate CPU overhead by not burdening the CPU with address calculation for the next area to be processed.

[Means to resolve the issue]

For this reason, the data processing device according to the present invention stores the start address, area length, and number of areas of the circular buffer 4 in advance, and upon receiving instructions from the CPUI, the next CPU
It is characterized by the provision of a dedicated address calculation circuit 6 that calculates the address of the area processed by i and passes it to the CPU.

[Effect]

The address calculation circuit 6 according to the present invention stores in advance information on the start address of the circular buffer 4, the length of the area, and the number of areas.

Here, when the CPUI issues a command to the address calculation circuit 6,
The address calculation circuit 6 calculates the address of the area to be processed next by CPtJl. Then, by the read operation of the CPUI, the address of the area calculated in advance is
Pass to UI.

[Actual example]

An embodiment of the present invention will be described below with reference to the drawings. Note that the same components as those described above are given the same or corresponding numerals, and the explanation thereof will be omitted.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 6 is a dedicated address calculation circuit newly provided to calculate the address of the area processed by the CPU.

Next, the operation will be explained with reference to FIG. First, the CPUI writes information on the starting address of the circular buffer, the length of the area, and the number of areas into the address calculation circuit 6 in advance.

When the CPUI sequentially processes the circular buffer area,
First, the address of the area to be processed is received from the address calculation circuit 6 (Sll), and the contents of the area corresponding to the received address are processed (S12). When the processing of the contents of this area is completed, the CPUI issues an instruction to the address calculation circuit 6 to complete the processing (s+a).

The address calculation circuit 6 receives this processing completion instruction and calculates the CPU number based on the starting address of the circular buffer 5, the area length, and the number of areas written in advance by the CPUI.
I calculates the address of the next area to process.

If there is a read operation from the CPUI, the calculated address is output to the CPUI.

〔Effect of the invention〕

As explained above, according to the present invention, the starting address of the circular buffer, the length of the area, and the number of areas are stored in advance, and upon receiving instructions from the CPU, the address of the area to be processed next by the CPU is calculated. A dedicated address calculation circuit is provided to pass the address to the CPU, reducing the load on the CPU and reducing the burden on the CPU.
It becomes possible to override the PU.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an operation flow diagram showing the operation of the present invention, FIG. 3 is a block diagram of a conventional data processing device, and FIG. 4 is a block diagram of a conventional data processing device. FIG. 3 is an operation flow diagram showing the operation of the device. 1...CPU, 2...ROM, 3...RAM, 4...
- Circular buffer, 5...area, 6...address calculation circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding components. Agent: Masuo Oiwa (2 idiots) No. 82 Iris 82 procedural amendment (voluntary) 1. Indication of the case Patent Application No. 17420CS No. 1988 2. Name of the invention Atta processing device 3. Representative of the person making the amendment Shi Iji 1 Column for detailed explanation of the invention subject to the Kimoriya amendment. In the 10th line of page 6 of the statement of contents of the amendment, the phrase ``Based on the number of pieces'' is amended to read ``Based on the number of pieces.''that's all

Claims (1)

[Scope of Claims] The above-mentioned system comprises a CPU, a ROM storing a program, and a RAM used as a work area for the program and a buffer for the data when the CPU exchanges data with the outside. A part of the RAM is used as a circular buffer consisting of multiple areas of a fixed length, and the CPU processes the contents in order starting from the first area of the circular buffer, and when the area reaches the end of the circular buffer, it returns to the first area again. In a data processing device that processes a circular buffer, the start address, area length, and number of areas of a circular buffer are stored in advance, and upon receiving instructions from the CPU, the data processing device
A data processing device comprising a dedicated address calculation circuit that calculates an address of an area processed by a PU and passes it to a CPU.