JPH02232958A - Manufacture of semiconductor element lead frame - Google Patents
Manufacture of semiconductor element lead frameInfo
- Publication number
- JPH02232958A JPH02232958A JP1054113A JP5411389A JPH02232958A JP H02232958 A JPH02232958 A JP H02232958A JP 1054113 A JP1054113 A JP 1054113A JP 5411389 A JP5411389 A JP 5411389A JP H02232958 A JPH02232958 A JP H02232958A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- insulating film
- die pad
- diffusion bonding
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 238000009792 diffusion process Methods 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910045601 alloy Inorganic materials 0.000 abstract description 10
- 239000000956 alloy Substances 0.000 abstract description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052737 gold Inorganic materials 0.000 abstract description 7
- 239000010931 gold Substances 0.000 abstract description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052709 silver Inorganic materials 0.000 abstract description 4
- 239000004332 silver Substances 0.000 abstract description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 4
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 239000010949 copper Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 229910052718 tin Inorganic materials 0.000 abstract description 2
- 239000011135 tin Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 9
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 3
- 239000004071 soot Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910000833 kovar Inorganic materials 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000005660 chlorination reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
本発明は、少くとも半導体素子を取付けるためのダイパ
ッド部に絶縁性フィルムが貼り合わされた半導体素子用
リードフレームの製造方法に係り、特に、レジンモール
ド型半導体装置の製造に適用して好適な、超多ピン化可
能な半導体素子用リードフレームの製造方法に関するも
のである．The present invention relates to a method for manufacturing a lead frame for a semiconductor device in which an insulating film is bonded to at least a die pad portion for mounting a semiconductor device, and in particular, a method for manufacturing a lead frame for a semiconductor device, which is suitable for manufacturing a resin mold type semiconductor device. This paper relates to a method for manufacturing lead frames for semiconductor devices that can have multiple pins.
従来より、レジンモールド型半導体装置の組立用部材と
して用いられているリードフレームは、例えば第６図又
は第７図に示すような平面形状をしており、例えば、半
導体素子を取付けるためのダイパッド１と、その周囲に
配設された、前記半導体素子との結線を行うためのイン
ナーリード２と、該インナーリード２に連続するアウタ
ーリード３とを備えている．
上記リードフレームは、通常、コバール、４２合金、銅
系合金等の、導電性に優れ且つ強度が゜大きい金属板を
、ホトエッチング法やスタンビング法等により、前記グ
イパツド１、インナーリード２及びアウターリード３を
有する形状に加工して製遺されるものである．
上記リードフレームは、第８図に組立後の半導体装置の
要部を拡大して示すように、グイバツド１に半導体素子
《以下、単に素子ともいう》４を取付けると同時に、該
素子４のボンデイングパッド（図示せず）とインナーリ
ード２とを金等からなるワイヤ５により電気的に接続し
て用いられる．従って、通常、インナーリード２のボン
デイング位置に金や銀等の貴金属をメッキして、ワイヤ
ボンデイングが確実に行えるようになされている．近年
、半導体素子が高集積化され、入出力（■／０）端子の
数が増加するに伴い、半導体素子サイズは増大している
が、その一方で電子機器の小型・軽量化への要求は強く
、そのために半導体パッケージのより一層の小型化及び
同一サイズ内で一の多ビン化が進行している．このため
に、リードフレームに対しても加工サイズの微細化が求
められている，
しかしながら、エッチング法及びスタンビング法による
加工には限界が在存し、無制限に微少ピッチの加工がで
きるわけではない．概ね板厚に対してエッチング法では
８０％程度、スタ２ンピング法では板厚程度がスリット
の加工限界となっている．
又、半導体装置の組立では、ワイヤボンデイング法によ
る電気的接続が主に行われているが、前記インナーリー
ド２へのボンデイング時には、ワイヤ長に制限が存在す
る．これは、半導体装置のパッケージをレジンでモール
ドして形成する際のワイヤ流れによるショートを防止す
るためである．このようにワイヤ長に制限があるために
、インナーリード２をグイバツド１から離すことにより
、該インナーリード形成領域を拡げ、そのビン数を増や
すこともできない．
従って、搭載する半導体素子（チップ）サイズ及びダイ
パッドサイズが決定されると、インナーリード２の先端
の形成領域が決定されることになる．このようにインナ
ーリード形成領域が決定されると、それぞれの加工法に
よる加工限界ピッチから、最大加工ピン数が自ずと決ま
ってしまい、それ以上の多ピン化ができない．A lead frame conventionally used as an assembly member for a resin molded semiconductor device has a planar shape as shown in FIG. 6 or 7, for example, and has a die pad 1 for mounting a semiconductor element. , an inner lead 2 disposed around the inner lead 2 for connection to the semiconductor element, and an outer lead 3 continuous to the inner lead 2. The above-mentioned lead frame is usually made by using a metal plate with excellent conductivity and high strength, such as Kovar, 42 alloy, or copper alloy, by photo-etching or stamping. It is left after being processed into a shape with leads 3. As shown in FIG. 8, which shows an enlarged view of the main parts of the semiconductor device after assembly, the above-mentioned lead frame attaches the semiconductor element (hereinafter also simply referred to as element) 4 to the guide pad 1, and at the same time attaches the bonding pad of the element 4. (not shown) and the inner lead 2 are electrically connected by a wire 5 made of gold or the like. Therefore, the bonding position of the inner lead 2 is usually plated with a noble metal such as gold or silver to ensure wire bonding. In recent years, as semiconductor devices have become more highly integrated and the number of input/output (■/0) terminals has increased, the size of semiconductor devices has increased, but on the other hand, the demand for smaller and lighter electronic devices has increased. For this reason, semiconductor packages are becoming smaller and the number of bins within the same size is increasing. For this reason, miniaturization of processing size is required for lead frames as well. However, there are limits to processing by etching and stamping methods, and it is not possible to process infinitesimal micro pitches. ．． The processing limit for slits is approximately 80% of the plate thickness for the etching method, and approximately 80% of the plate thickness for the stamping method. Furthermore, in the assembly of semiconductor devices, electrical connections are mainly made by wire bonding, but when bonding to the inner leads 2, there are limitations on the wire length. This is to prevent short circuits caused by wire flow when molding semiconductor device packages with resin. Since the wire length is thus limited, it is not possible to expand the inner lead forming area and increase the number of bins by separating the inner lead 2 from the guide pad 1. Therefore, once the size of the semiconductor element (chip) to be mounted and the size of the die pad are determined, the area in which the tips of the inner leads 2 will be formed is determined. When the inner lead formation area is determined in this way, the maximum number of pins to be machined is automatically determined by the machining limit pitch of each machining method, and it is not possible to increase the number of pins further.
そこで、搭載するチップサイズ及びダイパッドサイズを
変更せず、しかもインナーリードにボンデイングするワ
イヤ長をも延長することなく、多ピン化を可能にするた
めに、ダイパッドに、半導体素子とインナーリードとの
電気的接続を中継する中間パッドが形成されている絶縁
性フィルムを貼り合せることにより、インナーリードを
ダイパッドから離在させることを可能とし、インナーリ
ードの形成領域を拡げ、結果としてインナーリードの数
を増設することを可能とすることが考えられる．
しかしながら、上述のような多ピン化を目的とする場合
を始めとして、例えば、モールド樹脂とダイパッドとの
接着性向上等を目的として絶縁性フィルムを貼り合せる
場合には、半導体装置の信頼性を確保するために、上記
絶縁性フィルムをダイパッドに確実に且つ強固に貼り合
わせることが極めて重要であり、その実現が強く要請さ
れる．本発明は上記要請に応えるべくなされたもので、
上記のように多ビン化等を目的とする絶縁性フィルムが
ダイパッドに確実に且つ強固に貼り合わされたリードフ
レームを容易に製造することができる半導体素子用リー
ドフレームの製造方法を提供することを課題とするもの
である．Therefore, in order to make it possible to increase the number of pins without changing the mounted chip size and die pad size, and without increasing the length of the wire bonded to the inner leads, the die pad has an electrical connection between the semiconductor element and the inner leads. By bonding an insulating film with an intermediate pad that relays physical connections, it is possible to separate the inner leads from the die pad, expanding the area where the inner leads are formed and increasing the number of inner leads. It is conceivable that it would be possible to do this. However, in cases where the purpose is to increase the number of pins as mentioned above, for example, when bonding an insulating film for the purpose of improving the adhesion between the mold resin and the die pad, it is necessary to ensure the reliability of the semiconductor device. Therefore, it is extremely important to reliably and firmly bond the insulating film to the die pad, and its realization is strongly requested. The present invention has been made in response to the above-mentioned demands.
An object of the present invention is to provide a method for manufacturing a lead frame for a semiconductor element, which can easily manufacture a lead frame in which an insulating film is reliably and firmly bonded to a die pad for the purpose of increasing the number of bins as described above. This is what we mean.
本発明は、少くとも半導体素子を取付けるためのダイパ
ッド部に絶縁性フィルムが貼り合わされた半導体装置用
リードフレームを製造するに際して、前記ダイパッドと
絶縁性フィルムを拡散接合により貼り合わせることによ
り、上記課題を達成したものである．
又、前記絶縁性フィルムのダイパッド部と接する裏面に
、予め金属層を形成しておくようにしたものである．
又、前記絶縁性フィルム及びダイパッド部の少くともい
ずれか一方の表面に、予め拡散接合を容易とするための
拡散接合用層を形成しておくようにしたものである．The present invention solves the above problems by bonding the die pad and the insulating film together by diffusion bonding when manufacturing a lead frame for a semiconductor device in which an insulating film is bonded to at least a die pad portion for attaching a semiconductor element. This has been achieved. Further, a metal layer is previously formed on the back surface of the insulating film that comes into contact with the die pad portion. Further, a diffusion bonding layer for facilitating diffusion bonding is formed in advance on at least one surface of the insulating film and the die pad portion.
本発明は、発明者等が鋭意研究した結果得られた知見に
基づいてなされたものであり、例えば第１図に示す如く
、グイパツド１と絶縁性フィルム８との間に拡散接合法
により接合層１０Ｂを形成するようにしたので、該ダイ
パッド１に対して絶縁性フィルム８を確実に且つ強固に
貼り合わせることができる．
又、前記絶縁性フィルム８のグイパツド１と接する裏面
に、予め金属層９を形成しておくようにした場合には、
拡散接合に利用できるだけでなく、熱膨張係数の適合も
容易となる．
又、前記絶縁性フィルム８及びダイパッド１の少くとも
いずれか一方の表面に、予め拡散接合を容易とするため
の拡散接合用層１０、ＩＯＡを形成しておくようにした
場合には、拡散接合が非常に容易となる．The present invention has been made based on the knowledge obtained as a result of intensive research by the inventors. For example, as shown in FIG. 10B, the insulating film 8 can be bonded to the die pad 1 reliably and firmly. Furthermore, in the case where a metal layer 9 is formed in advance on the back surface of the insulating film 8 that is in contact with the guide pad 1,
Not only can it be used for diffusion bonding, but it also makes it easier to match the coefficient of thermal expansion. Further, in the case where a diffusion bonding layer 10 and an IOA are formed in advance on at least one surface of the insulating film 8 and the die pad 1 to facilitate diffusion bonding, diffusion bonding is possible. becomes very easy.
以下、図面を参照して、本発明の実施例を詳細に説明す
る．
第２図（Ａ）は、本発明の笑施例であるリードフレーム
Ａの概略を示す部分平面図であり、同図（Ｂ）は、その
ＩＩＢ−ＩＩＢ断面図である．又、第３図（Ａ）は、本
実施例のリードフレームを作製する前の材料としてのリ
ードフレームＡ′と絶縁フィルム８の概略を示す部分平
面図であり、同図（Ｂ）はそのＩＩ［Ｂ−Ｉ［［Ｂ断面
図である．本実施例のリードフレームＡは、第２図（Ａ
）に示す構成単位が図中左右方向に連続されているもの
で、該構成単位は中央に位置するグイパツド１と、その
周囲に配設されたインナーリード２と、該インナーリー
ド２に連続するアウターリード３とからその基本が構成
されている．そして、上記グイパツド１には周縁部に中
間パッド（独立電極）６が配設された絶縁性フィルム８
が貼り合わされている．
上記リードフレームＡは、第３図（Ａ）及び（Ｂ）で示
すように、材料としてのリードフレームＡ′のグイパツ
ド１の上に、半導体素子取付部の周囲に配設された中間
パツド６を有する絶縁性フィルム８を貼り合わせること
により製造される．以下、第１図、第２図及び第３図を
参照しながら、本発明のリードフレームの作製方法につ
いて具体的に説明する．第１図（Ａ）〜（Ｄ）は、リー
ドフレームのグイパツド１上に絶縁性フィルム８を貼り
合わせる工程の概略を示す拡大部分断面図である．
まず、第３図に示すと同様のリードフレームＡ′と絶縁
性フィルム８とを用意する．このリードフレームＡ′は
、例えば、板厚１５０μｌの４２合金からなる３００ｎ
ｎ口の合金板を、トリクレン脱脂後、ＯＦＰＲ−８００
（商品名、東京応化■製ボジレジスト）をデイツブ方
式にてレジストコーティング（膜厚６μｌ）を行い、そ
の後所定のパターンマスクを用いて露光、次いで常法に
より現像及びボストベー夕等を行い、その後、塩化鉄に
よるエッチング及び更にその後にアセトンによる剥膜を
行うことにより作製することができる．又、絶縁性フィ
ルム８は、例えば、厚さ５０μ１のポリイミドフィルム
からなるフィルム基材８Ａの両面に、厚さ１８μｌの銅
箔がラミネートされている積層フィルムを用いて、次の
ようにして作製できる．なお、この積層フィルムとして
は、接着剤を用いていないもの、又は、高耐熱性の接着
剤を使用したものを用意する．
基本的には上記リードフレームＡ′の場合と同様のエッ
チング法により、上記積層フィルムの表面に所定パター
ンからなる中間バツド６を、その裏面には全体に上記銀
箔を残存させてなる裏面金属層９をそれぞれ形成する．
次いで、上記裏面金属層９には、拡散接合を容易とする
ための拡散接合用層１０を、例えば金（半田、すず又は
銀でもよい》をメッキすることにより形成する．なお、
必要に応じ上記中間パツド６の表面にも、金メッキ等の
表面処理を行うことができる．
又、前述の如く作製したリードフレームＡ′のグイパツ
ド１の表面にも、拡散接合を容易とするための拡散接合
用層１０Ａを、例えば半田（すすでもよい）をメッキす
ることにより予め形成しておく．
そして、第１図（Ａ）に示すように、上記ダイパッド１
の上に、上記絶縁性フィルム８を拡散接合用層１０が下
に向くように配し、次いで同図（Ｂ）に示すように、該
絶縁性フィルム８を上記ダイパッド１の上に載置し、上
記拡散接合用層１０をダイパッド１の拡散接合用層１０
Ａに接触させると同時に該両者の正確な位置合せを行う
．次いで、第１図（Ｃ）に示すように、拡散接合用加熱
治具１１により、上記絶縁性フィルム８をグイパツド１
に押圧（加圧）すると同時に加熱して、上記拡散接合用
層１０及び１，ＯＡによって拡散接合層１０Ｂを形成さ
せ、第１図（Ｄ）に示す如く、上記絶縁性フィルム８と
ダイパッド１とが確実且つ強固に貼り合わされた本実施
例のリードフレームＡが製造される．
第４図は、本実施例により製造されるリードフレームＡ
を用いて製造した半導体装置Ｃおいて、搭載される素子
４とインナーリード２との電気的接続の態様を示す概略
説明図である．本実施例の場合は、素子４のボンデイン
グパツド《図示せず》と中間バツド６とをワイヤ５Ａで
接続し、該中間パツド６とインナーリード２とをワイヤ
５Ｂで接続する．このように、中間バツド６を素子４と
インナーリード２との電気的接続の中継点とすることに
より、１本のワイヤ、特にワイヤ５Ｂを従来のワイヤ長
より延長することなく、グイパツド１からインナーリー
ド２のボンデイング位置（通常先端部）を離在させるこ
とが可能となる．その結果、樹脂をモールドする場合で
も、ワイヤが長いことに起因するショート等を起こすこ
となくインナーリード２の形成領域を拡張することが可
能となり、形成し得るインナーリード２の本数を増加さ
せ超多ビン化が容易に可能となる．
又、第５図は、本実施例により製造されるリードフレー
ムＡを用いる場合の他の態様を示す概略説明図であり、
このように搭載する素子４のサイズが小さい場合でも、
従来と同一サイズのリードフレームを使用して、第４図
で説明したと同様の電気的接続を行うことが可能であり
、本実施例によるリードフレームＡは一層の汎用性をも
有していることがわかる．
以上、本発明を実施例に基づいて具体的に説明したが、
本発明のリードフレームの製造方法は前記実施例に示し
たものに限られるものでない．例えば、リードフレーム
の形成材料としては、４２合金の他にコバール、銅系合
金等任意の材料を利用でき、絶縁性フィルムのフィルム
基材もポリイミドに限られず、絶縁性を備え且つ耐熱性
等の他の要求される性質を備えている材料であれば任意
のもので形成できる．
又、実施例では、絶縁性フィルムの裏面に銅からなる金
属層を設けた場合を示したが、この金属層は他の金属で
形成してもよいことはいうまでもなく、場合によっては
必ずしも設けなくともよい．又、実施例では、ダイパッ
ド及び絶縁性フィルムの両方に拡散接合用層が形成され
ている場合を示したが、゜何れか一方だけに形成するこ
ともできる．又、上記拡散接合層を形成する材料として
は、前述のように金、半田合金、すす、銀の外に金が主
成分である合金、すすが添加されている合金等の拡散接
合し易いものであれば任意の金属（合金を含む）で形成
することができる．
以上、本発明のリードフレームの製造方法を、多ビン化
を可能にするために中間パッドを備えた絶縁性フィルム
を貼り合せる場合を例に説明したが、本発明の適用範囲
は、これに限るものでなく、目的の如何に拘らず絶縁性
フィルムをダイパッド部に貼り合せる場合であれば如何
なる場合にも適用可能であることはいうまでもない．Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 2(A) is a partial plan view schematically showing a lead frame A according to an embodiment of the present invention, and FIG. 2(B) is a sectional view taken along line IIB-IIB. Further, FIG. 3(A) is a partial plan view schematically showing the lead frame A' and the insulating film 8 as materials before producing the lead frame of this example, and FIG. [B-I[[B sectional view. The lead frame A of this example is shown in FIG.
) are continuous in the left-right direction in the figure, and the structural units are a guide pad 1 located in the center, an inner lead 2 arranged around it, and an outer lead continuous to the inner lead 2. Its basic structure consists of lead 3. The guide pad 1 has an insulating film 8 on which an intermediate pad (independent electrode) 6 is disposed on the periphery.
are pasted together. As shown in FIGS. 3(A) and 3(B), the lead frame A has an intermediate pad 6 disposed around the semiconductor element mounting portion on the guide pad 1 of the lead frame A' as a material. It is manufactured by laminating the insulating film 8 having the following properties. Hereinafter, with reference to FIGS. 1, 2, and 3, the method for manufacturing a lead frame of the present invention will be specifically explained. FIGS. 1A to 1D are enlarged partial cross-sectional views schematically showing the process of bonding an insulating film 8 onto a lead frame pad 1. First, a lead frame A' and an insulating film 8 similar to those shown in FIG. 3 are prepared. This lead frame A' is, for example, 300n made of 42 alloy with a plate thickness of 150μl.
After degreasing the n-hole alloy plate, OFPR-800
(Product name, Bosiresist manufactured by Tokyo Ohka) was coated with a resist coating (film thickness: 6 μl) using a dipping method, then exposed using a predetermined pattern mask, and then developed and exposed using a conventional method, followed by chlorination. It can be fabricated by etching with iron and then removing the film with acetone. Further, the insulating film 8 can be produced in the following manner using, for example, a laminated film in which copper foil with a thickness of 18 μl is laminated on both sides of a film base material 8A made of a polyimide film with a thickness of 50 μl. ．． The laminated film should be one that does not use an adhesive or one that uses a highly heat-resistant adhesive. Basically, by the same etching method as in the case of the lead frame A', an intermediate pad 6 having a predetermined pattern is formed on the surface of the laminated film, and a back metal layer 9 is formed on the back surface of which the silver foil remains entirely. form each.
Next, a diffusion bonding layer 10 for facilitating diffusion bonding is formed on the back metal layer 9 by plating with, for example, gold (solder, tin, or silver may also be used).
If necessary, the surface of the intermediate pad 6 can also be subjected to surface treatment such as gold plating. Further, on the surface of the guide pad 1 of the lead frame A' produced as described above, a diffusion bonding layer 10A for facilitating diffusion bonding is formed in advance by plating, for example, solder (or soot). put. Then, as shown in FIG. 1(A), the die pad 1
The insulating film 8 is placed on top of the die pad 1 with the diffusion bonding layer 10 facing downward, and then the insulating film 8 is placed on the die pad 1 as shown in FIG. , the above diffusion bonding layer 10 is used as the diffusion bonding layer 10 of the die pad 1.
At the same time as making contact with A, accurately align the two. Next, as shown in FIG. 1(C), the insulating film 8 is bonded to a guide pad 1 using a heating jig 11 for diffusion bonding.
The diffusion bonding layer 10B is formed by pressing (pressurizing) and simultaneously heating the diffusion bonding layers 10 and 1 and OA, and as shown in FIG. 1(D), the insulating film 8 and the die pad 1 are bonded together. The lead frame A of this embodiment is manufactured in which the two are reliably and firmly bonded together. FIG. 4 shows a lead frame A manufactured according to this example.
FIG. 2 is a schematic explanatory diagram showing a mode of electrical connection between an element 4 to be mounted and an inner lead 2 in a semiconductor device C manufactured using the method. In this embodiment, the bonding pad (not shown) of the element 4 and the intermediate pad 6 are connected by a wire 5A, and the intermediate pad 6 and the inner lead 2 are connected by a wire 5B. In this way, by using the intermediate pad 6 as a relay point for electrical connection between the element 4 and the inner lead 2, one wire, especially the wire 5B, can be connected from the guide pad 1 to the inner lead without extending the wire length beyond the conventional wire length. It is possible to separate the bonding position of lead 2 (usually the tip). As a result, even when molding resin, it is possible to expand the formation area of the inner leads 2 without causing short circuits caused by long wires, increasing the number of inner leads 2 that can be formed, and increasing the number of inner leads 2 that can be formed. Binning is easily possible. Further, FIG. 5 is a schematic explanatory diagram showing another aspect when using the lead frame A manufactured according to this example,
Even if the size of the mounted element 4 is small in this way,
It is possible to make the same electrical connection as explained in FIG. 4 using a lead frame of the same size as the conventional lead frame, and the lead frame A according to this embodiment also has further versatility. I understand that. The present invention has been specifically described above based on examples, but
The method of manufacturing the lead frame of the present invention is not limited to that shown in the above embodiments. For example, in addition to 42 alloy, any material such as Kovar or copper-based alloy can be used as the material for forming the lead frame, and the film base material for the insulating film is not limited to polyimide. It can be formed from any material that has the other required properties. Further, in the example, a case was shown in which a metal layer made of copper was provided on the back surface of the insulating film, but it goes without saying that this metal layer may be formed of other metals, and in some cases, it may not necessarily be necessary. It does not need to be provided. Furthermore, although the embodiment shows a case in which the diffusion bonding layer is formed on both the die pad and the insulating film, it is also possible to form it on only one of them. In addition, the materials for forming the diffusion bonding layer include materials that are easy to bond by diffusion, such as gold, solder alloys, soot, alloys containing gold as a main component in addition to silver, and alloys to which soot is added, as described above. It can be made of any metal (including alloys). The method for manufacturing a lead frame of the present invention has been described above using as an example the case where an insulating film equipped with an intermediate pad is bonded to enable multi-bin production, but the scope of application of the present invention is limited to this. Needless to say, this method can be applied to any case where an insulating film is attached to a die pad, regardless of the purpose.
本発明のリードフレームの製造方法によれば、ダイパッ
ドに絶縁性フィルムが確実に且つ強固に貼り合された半
導体素子用リードフレームを容易に製造することができ
る．According to the lead frame manufacturing method of the present invention, it is possible to easily manufacture a lead frame for a semiconductor element in which an insulating film is reliably and firmly bonded to a die pad.
第１図（Ａ）〜（Ｄ）は、それぞれ本発明の実施例によ
るリードフレームの製造方法の工程の概略を示す部分断
面図、
第２図（Ａ）は、本発明の実施例であるリードフレーム
の概略を示す部分平面図、同図（Ｂ）は、そのｆｆＢ−
ｆｆＢ断面図、
第３図（Ａ）は、前記実施例のリードフレームを作製す
る前の段階にあるリードフレームと絶縁性フィルムの概
略を示す部分平面図、同図（Ｂ．）は、そのＩＩ［Ｂ−
１１ｒＢ断面図、
第４図及び第５図は、それぞれ前記実施例のリードフレ
ームを用いて製造した半導体装置の要部を示す概略説明
図、
第６図及び第７図は、それぞれ従来のリードフレームの
１単位を示す平面図、
第８図は、従来のリードフレームを用いて製造した半導
体装置の要部を示す概略説明図である．８・・・絶縁性
フィルム、
１０、ＩＯＡ・・・拡散接合用層、
１０Ｂ・・・接合層．FIGS. 1(A) to (D) are partial cross-sectional views showing the outline of the steps of a method for manufacturing a lead frame according to an embodiment of the present invention, and FIG. 2(A) is a lead frame according to an embodiment of the present invention. A partial plan view schematically showing the frame, (B) is its ffB-
ffB sectional view, FIG. 3(A) is a partial plan view schematically showing the lead frame and insulating film at a stage before producing the lead frame of the example, and FIG. 3(B.) is the II [B-
11rB sectional view, FIGS. 4 and 5 are schematic explanatory diagrams showing the main parts of a semiconductor device manufactured using the lead frame of the above example, and FIGS. 6 and 7 are respectively a conventional lead frame. FIG. 8 is a schematic diagram showing the main parts of a semiconductor device manufactured using a conventional lead frame. 8... Insulating film, 10, IOA... Diffusion bonding layer, 10B... Bonding layer.
Claims (3)
部に絶縁性フィルムが貼り合わされた半導体装置用リー
ドフレームを製造するに際して、前記ダイパッドと絶縁
性フィルムを拡散接合により貼り合わせることを特徴と
する半導体素子用リードフレームの製造方法。(1) A semiconductor device characterized in that when manufacturing a lead frame for a semiconductor device in which an insulating film is bonded to at least a die pad portion for attaching a semiconductor device, the die pad and the insulating film are bonded together by diffusion bonding. manufacturing method for lead frames for
製造方法において、前記絶縁性フィルムのダイパッド部
と接する裏面に、予め金属層を形成しておくことを特徴
とする半導体素子用リードフレームの製造方法。(2) The method for manufacturing a lead frame for a semiconductor element according to claim 1, wherein a metal layer is formed in advance on a back surface of the insulating film that is in contact with a die pad portion. Production method.
ームの製造方法において、前記絶縁性フィルム及びダイ
パッド部の少くともいずれか一方の表面に、予め拡散接
合を容易とするための拡散接合用層を形成しておくこと
を特徴とする半導体素子用リードフレームの製造方法。(3) In the method for manufacturing a lead frame for a semiconductor element according to claim 1 or 2, a diffusion bonding layer is provided in advance on the surface of at least one of the insulating film and the die pad portion to facilitate diffusion bonding. A method for manufacturing a lead frame for a semiconductor device, characterized by forming a layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1054113A JPH02232958A (en) | 1989-03-07 | 1989-03-07 | Manufacture of semiconductor element lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1054113A JPH02232958A (en) | 1989-03-07 | 1989-03-07 | Manufacture of semiconductor element lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02232958A true JPH02232958A (en) | 1990-09-14 |
Family
ID=12961539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1054113A Pending JPH02232958A (en) | 1989-03-07 | 1989-03-07 | Manufacture of semiconductor element lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02232958A (en) |
-
1989
- 1989-03-07 JP JP1054113A patent/JPH02232958A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH05129473A (en) | Resin-sealed surface-mounting semiconductor device | |
| JPS6231819B2 (en) | ||
| JPH11195742A (en) | Semiconductor device, manufacture thereof, and led frame therefor | |
| JPH04280462A (en) | Lead frame and semiconductor device using this lead frame | |
| WO2007148782A1 (en) | Resin-sealed semiconductor device, method for manufacturing the same, base for semiconductor device, and multilayer resin-sealed semiconductor device | |
| JP3550875B2 (en) | Lead frame and semiconductor device using the same | |
| JPH11121543A (en) | Chip scale package | |
| JPH0158864B2 (en) | ||
| JPS62232948A (en) | Lead frame | |
| JPH04127564A (en) | Manufacture of lead frame | |
| JPH0997868A (en) | Lead frame member and its manufacturing method | |
| EP0723293B1 (en) | Semiconductor device with a heat sink and method of producing the heat sink | |
| JPH02232958A (en) | Manufacture of semiconductor element lead frame | |
| JPH09306949A (en) | Tape automated bonding to composite bumps | |
| KR101297662B1 (en) | Manufacture method of lead frame | |
| JP2002164496A (en) | Semiconductor device and method for manufacturing the same | |
| JP3562304B2 (en) | Method for manufacturing multilayer lead frame | |
| JPH0485864A (en) | Semiconductor device lead frame | |
| JPH03119755A (en) | Manufacture of lead frame | |
| JPH04249356A (en) | Lead frame | |
| JPH02232945A (en) | Lead frame for semiconductor element | |
| JPH0496263A (en) | Manufacture of semiconductor circuit lead frame | |
| JPH03206633A (en) | Semiconductor device | |
| JPH0336755A (en) | Semiconductor device lead frame | |
| JPH0846112A (en) | Manufacture of semiconductor device |