JPH02232949A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To build P and N MOS transistors in a semiconductor integrated circuit device so that a revision of the device can be easily performed by a method wherein when an automatic arrangement wiring is performed on the device by a CAD device, a FEED cell, which is automacatically inserted in the circuit device, is used. CONSTITUTION:In case the function of an inverter is added between functional calls A(1) and B(2) of a semiconductor integrated circuit device, P and N MOS transistors Tr4 snd Tr5 provided in a FEED cell 3 are used. In case the function of the inverter is realized in this cell 3, contact holes (CH)6, Al1(7) and Al2(8) are arranged and wirings in through holes (TH)9, Al110 and Al211 are modified in such a way that the inverter is inserted in a purposed signal wiring. Moreover, in case the function of the cell A(1) or B(2) is modified in addition to an addition of the function of the inverter, the modification is performed using the cell 3 which is inserted.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention performs automatic placement and wiring using a CAD device, and is used to manufacture a wafer process mask (hereinafter abbreviated as mask) for a designed semiconductor integrated circuit device. The present invention also relates to a semiconductor integrated circuit device in which functional changes that occur after the device is completed can be easily changed.

[Conventional technology]

FIG. 3 is a diagram showing a conventional non-functional block (hereinafter referred to as FEED cell). As shown in the figure, the FEED cell has only aluminum wiring (All) for power supply between functional blocks (hereinafter referred to as cells) as cell data.

Generally, when automatic wiring is performed using a CAD device, when cells are efficiently arranged, gaps are created between the cells when only functional cells are used, and the power supply wiring for forming the cells is interrupted. Therefore, if a gap occurs, use FEED to fill the gap.
Cells are automatically inserted, but FEED cells are non-functional cells that only fill gaps.

[Problem to be solved by the invention]

In semiconductor integrated circuit devices designed and routed in this way, in order to confirm the validity of the placement and wiring length, the output results of automatic placement and wiring of the CAD device are used to calculate the delay using the actual wiring length. The reliability of semiconductor integrated circuit devices has been improved.

However, if a semiconductor integrated circuit device whose design has been completed needs to be revised, such as by deleting or adding functional cells, it is necessary to perform automatic placement and wiring again using a CAD device.

Therefore, the arrangement of functional cells and the wiring between cells are changed, and all the data that was previously designed, developed, and confirmed needs to be changed.

Furthermore, if the mask manufacturing has already been completed using the previous data, the entire mask must be manufactured again.

Due to the above-mentioned problems, the problem is that revising a semiconductor integrated circuit device once it has been designed and developed requires the same amount of time and expense as designing and developing a new semiconductor integrated circuit device. There was a point.

This invention was made to solve the above-mentioned problems, and when revising the functions of a semiconductor integrated circuit device that has been automatically placed and routed using a CAD device after the completion of design and development, the revision time and An object of the present invention is to obtain a semiconductor integrated circuit device that can minimize costs.

[Means to solve the problem]

The semiconductor integrated circuit device according to the present invention has an FEE that is automatically inserted when performing automatic placement and wiring using a CAD device.
Using a D cell, a P-channel MOS transistor and an N-channel MOS transistor are built into the FEED cell so that the semiconductor integrated circuit device can be easily revised.

[Effect]

In the semiconductor integrated circuit device of this invention, the FEED cells automatically inserted by the CAD device realize a master slice type semiconductor integrated circuit device similar to a gate array, and the functions of the semiconductor integrated circuit device are improved. When revising, functions can be easily added, and delays can be confirmed by using the wiring lengths between other functional blocks as they are, eliminating the need for re-placement and wiring.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 is a diagram of one embodiment of the FEED cell used in this invention.In the past, only aluminum wiring data for power supply was available, but data for P-channel MOS transistors and N-channel MOS transistors has been added. has been done.

FIGS. 2(a) and 2(b) show an embodiment of the present invention using the FEED cell shown in FIG. Figure 2(a) shows the state before revision, and the semiconductor integrated circuit device has functional cell A.
It consists of (1) and functional cell B (2), and CA
A FEED cell (3) that was automatically inserted to enable the CAD device to efficiently place and route the D device.
is located.

However, it became necessary to revise the semiconductor integrated circuit device,
When an inverter function is added between functional cell A (1) and functional cell B (2), conventionally, transistors (4) .
However, in the present invention, as shown in FIG. 2(b), the P-channel type M provided in the FEED cell (3) is
Addition can be easily made using an OS transistor (4) and an N-channel type MOS transistor (5).

Contact holes (CH) (6), All (7),
Place A12 (8) and insert the through hole (TH) (9) and A to insert the inverter into the desired signal arrangement.
11(7) and A12(8) may be changed.

Further, although the above embodiment shows the case where an inverter function is added, the added function can be similarly easily performed using a device other than an inverter.

Also, when changing the function of function cell A (1) or function cell B (2) other than adding a function, the inserted FE
This will be changed using the ED cell (3).

With these additions and changes, the maximum number of wafer process steps that need to be changed is All(7). TH(9), CH
This can be done by changing four masks in four steps (a) and A12(8).

In addition, there is no need to re-execute automatic placement and wiring when making revisions for delay confirmation that includes added or changed parts, so all previous data can be used, reducing design development time.

[Effect of birth]

As described above, according to the present invention, in a semiconductor integrated circuit device in which automatic placement and wiring are performed using a CAD device, when a function change or addition becomes necessary after the design and start-up is completed, the function can be easily changed or added. Additions and changes can be made, and the cost and time required for additions and changes can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a FEED cell which is an embodiment of the present invention, FIG. 2 is a plan view of a semiconductor integrated circuit using the FEDD cell shown in FIG. A part of the semiconductor integrated circuit device is shown, and figure (b) is the revised figure (a).
) FIG. 3 is a plan view showing a FEED cell used in a conventional semiconductor integrated circuit. In the figure, (1) is cell A, (2) is cell B, (3)
(4) is a P-channel MOS transistor, (5) is an N-channel MOS transistor, (6) is a contact hole, and (7) is an All. In addition, in the figure, is shown. The same code is the same,

Claims (1)

[Claims] In a semiconductor integrated circuit device, a CAD device is used to automatically place functional blocks within a semiconductor integrated circuit device, and signal wiring between these functional blocks is also performed using a CAD device. For the block,
A semiconductor characterized by incorporating an unused P-channel MOS transistor and an N-channel MOS transistor, and making it easy to change functions that occur during and after the fabrication of a mask for wafer processing of a semiconductor integrated circuit device. Integrated circuit device.