JPH02231706A - Reduced projection exposure method - Google Patents

Reduced projection exposure method

Info

Publication number
JPH02231706A
JPH02231706A JP1052323A JP5232389A JPH02231706A JP H02231706 A JPH02231706 A JP H02231706A JP 1052323 A JP1052323 A JP 1052323A JP 5232389 A JP5232389 A JP 5232389A JP H02231706 A JPH02231706 A JP H02231706A
Authority
JP
Japan
Prior art keywords
exposure
wafer
reflectivity
reflectance
amount
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1052323A
Other languages
Japanese (ja)
Inventor
Hiroshi Nozue
野末 寛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1052323A priority Critical patent/JPH02231706A/en
Publication of JPH02231706A publication Critical patent/JPH02231706A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the reliability and manufacturing yield of semiconductor devices by measuring the reflectivity for ultraviolet rays at the surface of the semiconductor device beforehand, and setting the amount of exposure in response to said reflectivity. CONSTITUTION:Before the exposure of a wafer, the reflectivity of the wafer is measured. When the reflectivity is R3, the optimum amount of exposure E3 at the reflectivity R3 is obtained. All the wafers in the objective lot are exposed with the amout of exposure E3. At this time, the most effective method is as follows: the relational straight line l1 between the reflectivity and the amount of exposure is inputted into a computer in a stepper beforehand; the optimum amount of exposure is automatically computed based on the result of the reflectivity measurement; and the exposure with the obtained optimum amount of exposure is performed automatically. Therefore, the time for exposure, development, size measurement and the like by using a test wafer can be omitted. Even if there is dispersion in reflectivity in the wafer, the pattern size can be formed constantly. In this way, the integrated circuit device whose reliability and manufacturing yield are improved can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体気積回路などの製造工程で用いられる縮
少投影露光方法に関する. 〔従来の技術〕 近年、半導体集積回路を低価格に大量生産し、かつ高性
能なものとすべく高集積化、微細化が推進され超LSI
と呼ばれる高密度記憶回路装置が開発されている.超L
SI回路パターンを半導体基板上に形成するためには、
微細パターンを正確に形成する必要があり、このため縮
少投影露光装置いわゆるステッパーが用いられている.
第4図は従来のステッパーの基本構成を示す模式図であ
る.防震台108上にX−Y2方向に移動可能なステー
ジ107が設置されている.ステージ107上には露光
を必要とするウェハー105を載せるためのウェハー台
106が設置されている.光源101から発生した紫外
光100はコンデンサレンズ102で平行光束となり、
半導体集積回路パターンが実寸よりもn倍に拡大され形
成されているレティクル103を通過する.レティクル
像は縮少投影レンズ104によって1 / nに、即ち
実寸に縮少されウェハー105上に結像露光される. ところで、縮少投影レンズ104を用いて一度に露光可
能な面積は通常52〜152mm2程度であり、それに
対して用いられるウェハーは100〜2 0 0 wu
aφ程度であるため、ウェハー全面に一度に露光するこ
とは不可能である.そこで、ある部位を露光した後、ス
テージ107を移動し、他の部位を露光し、再びステー
ジ移動と露光とを繰り返し、ウェハー全面を露光するが
、この時のそれぞれの部位における露光量は一定に保た
れている. 露光対象のウェハー上には被加工材及びパターン転写の
ためのレジストが塗布されているが、露光を行なう場合
レジスト下の被加工材の露光光に対する反射率によって
、設計寸法を得るための最適露光時間は異なっている. 例えば、被加工材がアルミニウムなどの金属の場合、反
射率は高くレジストは反射光によっても露光されるため
露光量は少なくてよい。これに対し、酸化シリコンや窒
化シリコンなど反射率が低い場合には露光量が多くなる
。例えば、アルミニウム膜上に約1.5μmの厚さに塗
布されたOFPR800レジスト(東京応化工業製)を
波長(λ)=436nmを持つ水銀のg線で露光する場
合、設計寸法1μmの孤立ラインに対する最適露光量は
約1 00mJであるが、下地が窒化シリコン膜(15
00人膜厚)の場合は約150mJである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reduction projection exposure method used in the manufacturing process of semiconductor volumetric circuits and the like. [Prior art] In recent years, high integration and miniaturization have been promoted in order to mass produce semiconductor integrated circuits at low cost and achieve high performance.
A high-density memory circuit device called . Super L
In order to form an SI circuit pattern on a semiconductor substrate,
It is necessary to form fine patterns accurately, and for this purpose a reduced projection exposure device, a so-called stepper, is used.
Figure 4 is a schematic diagram showing the basic configuration of a conventional stepper. A stage 107 movable in two directions, X and Y, is installed on a seismic stand 108. A wafer stand 106 is installed on the stage 107 on which a wafer 105 that requires exposure is placed. The ultraviolet light 100 generated from the light source 101 becomes a parallel beam of light at the condenser lens 102,
The semiconductor integrated circuit pattern passes through a reticle 103 formed to be enlarged n times larger than its actual size. The reticle image is reduced to 1/n, that is, to the actual size, by a reduction projection lens 104, and is imaged and exposed onto a wafer 105. By the way, the area that can be exposed at one time using the reduction projection lens 104 is usually about 52 to 152 mm2, and the wafer used for this is 100 to 200 wu.
Since it is about aφ, it is impossible to expose the entire wafer at once. Therefore, after exposing a certain area, the stage 107 is moved to expose another area, and the stage movement and exposure are repeated again to expose the entire wafer, but at this time, the amount of exposure at each area is constant. It is maintained. The workpiece and a resist for pattern transfer are coated on the wafer to be exposed, but when performing exposure, the optimum exposure to obtain the design dimensions is determined depending on the reflectance of the workpiece under the resist to the exposure light. The times are different. For example, when the workpiece is a metal such as aluminum, the reflectance is high and the resist is also exposed to reflected light, so the amount of exposure may be small. On the other hand, when the reflectance is low, such as silicon oxide or silicon nitride, the amount of exposure becomes large. For example, when exposing OFPR800 resist (manufactured by Tokyo Ohka Kogyo Co., Ltd.) coated on an aluminum film to a thickness of approximately 1.5 μm with mercury g-line having a wavelength (λ) = 436 nm, an isolated line with a design dimension of 1 μm The optimum exposure dose is about 100 mJ, but if the underlying layer is a silicon nitride film (15
00 human film thickness), it is approximately 150 mJ.

これら最適露光量を求める方法として、従来は数枚から
数十枚で構成される1ロットのうちから1枚のウエハー
を抜きとり、ウエハー上を露光ショット毎に露光量を変
化させて露光し、現像後測長装置によってパターンの寸
法を測長し、設計寸法通りにパターンの形成された露光
量を選択し、次で残りのウェハーをこの露光量で露光す
るという方法が用いられている.この作業は通常ロフト
毎に行なわれている. 〔発明が解決しようとする課題〕 上述した従来の縮少投影露光方法は1ロットから1枚の
ウェハーを抜きとり、そのウエハー上に露光量を変化さ
せて露光して現像し、その後パターンの寸法測定により
最適露光量を決定しているので、最適露光条件を決める
までに長時間を必要とすると共に条件出しのウェハーが
無駄になるという欠点がある.またロフト内のウエハー
間で反射率にばらつきがあったり、ウェハー内で反射率
にばらつきがあると、最適と思われる同一の露光量で露
光した場合でも、露光不足あるいは露光過剰で不良とな
り、半導体装置の信頼性及び製造歩留りを低下させると
いう欠点がある.上述した従来の縮少投影露光方法に対
し本発明は、あらかじめ各種ウェハーの露光光に対する
反射率と最適露光量との関係をもとめておき、ウェハー
を露光する場合、そのウェハーの反射率を求めることに
より、テスト露光することなく、最適露光量を前記関係
より求め、その露光量によりロットのすべてのウェハー
を露光するという相違点を有する. 〔課題を解決するための手段〕 本発明の縮少投影露光方法は、紫外光によりガラス基板
上に形成されているパターンを光感光性有機膜の塗布さ
れた半導体基板上に順次縮少投影露光を行なう縮少投影
露光方法において、あらかじめ前記半導体基板表面に於
ける前記紫外光に対する反射率を測定し、該反射率に応
じて前記半導体基板に対する露光量を設定するものであ
る.〔実施例〕 次に、本発明について図面を参照して説明する. 第1図は本発明の実施例を説明するためのステッパーの
模式図である.基本的構成は従来のステッパーとほとん
ど同じであるが、本実施例に用いるステッパーは、ウェ
ハー表面に於ける反射率を測定するための反射率測定機
能を有している.反射率測定機能は光源1,ハーフミラ
ー2,レンズ系3及び検出系4より構成される.ステー
ジ107は縮少投影レンズ104とレンズ系3の下を移
動可能となっている.反射率の測定には露光光と同じ波
長の光を用いるため、反射率測定時、レジストは露光さ
れてしまう.このため光源1で反射率を測定する場合は
、その測定領域はステッパーで露光を行なわないウェハ
ー上の部位にするか、あるいはあらかじめ測定領域を決
めておき、レジスト塗布前に測定する等の工夫が必要で
ある. 第2図はウェハー表面の反射率と最適露光量との関係を
示した図である. あらかじめ低反射率R1を持つウェハーに於ける最適露
光量E1及び高反射率R2を持つウェハーに於ける最適
露光量E2を求め、その関係直線e1を求めておく.2
lの算出に当たっては、より多くの異なる反射率を持つ
ウェハーを用いて、精度の高い直線を求めておく方が良
い.尚、第2図はウェハー上にレジストを塗布してない
場合について求めたものである.レジストが塗布されて
いる場合も同様に直線が求められる。
Conventionally, as a method for determining the optimum exposure amount, one wafer is extracted from a lot consisting of several to several dozen wafers, and the wafer is exposed by changing the exposure amount for each exposure shot. The method used is to measure the length of the pattern using a length measuring device after development, select an exposure dose that will form the pattern according to the designed dimensions, and then expose the remaining wafers to this exposure dose. This work is usually done for each loft. [Problems to be Solved by the Invention] The conventional reduced projection exposure method described above extracts one wafer from one lot, exposes and develops the wafer with varying exposure doses, and then changes the pattern size. Since the optimal exposure amount is determined by measurement, it takes a long time to determine the optimal exposure conditions, and the wafer used to set the conditions is wasted. In addition, if there are variations in reflectance between wafers in the loft or within a wafer, even when exposed with the same amount of light, which is thought to be optimal, the semiconductor may be defective due to underexposure or overexposure. This has the disadvantage of reducing device reliability and manufacturing yield. In contrast to the conventional reduction projection exposure method described above, the present invention involves determining in advance the relationship between the reflectance of each wafer to exposure light and the optimum exposure amount, and then determining the reflectance of the wafer when exposing the wafer. The difference is that the optimum exposure amount is determined from the above relationship without test exposure, and all wafers in the lot are exposed using that exposure amount. [Means for Solving the Problems] The reduction projection exposure method of the present invention sequentially applies reduction projection exposure to a pattern formed on a glass substrate using ultraviolet light onto a semiconductor substrate coated with a photosensitive organic film. In the reduction projection exposure method, the reflectance of the ultraviolet light on the surface of the semiconductor substrate is measured in advance, and the amount of exposure to the semiconductor substrate is set in accordance with the reflectance. [Example] Next, the present invention will be explained with reference to the drawings. FIG. 1 is a schematic diagram of a stepper for explaining an embodiment of the present invention. The basic configuration is almost the same as a conventional stepper, but the stepper used in this example has a reflectance measurement function for measuring the reflectance on the wafer surface. The reflectance measurement function consists of a light source 1, a half mirror 2, a lens system 3, and a detection system 4. The stage 107 is movable under the reduction projection lens 104 and the lens system 3. Since light of the same wavelength as the exposure light is used to measure reflectance, the resist is exposed when measuring reflectance. Therefore, when measuring the reflectance using light source 1, it is recommended to set the measurement area to a part of the wafer that will not be exposed using a stepper, or to decide the measurement area in advance and measure it before applying the resist. is necessary. Figure 2 shows the relationship between the reflectance of the wafer surface and the optimum exposure dose. The optimal exposure amount E1 for a wafer with a low reflectance R1 and the optimal exposure amount E2 for a wafer with a high reflectance R2 are determined in advance, and the relationship line e1 is determined. 2
When calculating l, it is better to use wafers with as many different reflectances as possible to obtain a highly accurate straight line. Furthermore, Figure 2 shows the results obtained when no resist is coated on the wafer. Straight lines are similarly determined when resist is applied.

まず第1の実施例としてウェハーの露光に先立ちその反
射率を測定する.反射率がR3であれば第2図より反射
率R3に対する最適露光量E3を求め、対象とするロッ
ト中のすべてのウェハーを露光量E3で露光する.第2
図に示した反射率と露光量との関係直線f.を、ステッ
パー内のコンピュータにあらか。しめ入力しておくこと
により、行ない、かつ求められた最適露光量による露光
を自動的に行わせる方法が最も有効である。
First, as a first example, the reflectance of a wafer is measured prior to exposure. If the reflectance is R3, the optimum exposure amount E3 for the reflectance R3 is determined from FIG. 2, and all wafers in the target lot are exposed at the exposure amount E3. Second
The relationship straight line f between reflectance and exposure amount shown in the figure. If there is any problem with the computer inside the stepper. The most effective method is to automatically perform exposure using the determined optimum exposure amount by inputting the information in advance.

このように、第1の実施例によれば、ウエハーの反射率
から最適露光量が定められるため、露光不良は極めて少
いものとなる. 第3図は本発明の第2の実施例を説明するためのウェハ
ーの上面図である。
In this way, according to the first embodiment, since the optimum exposure amount is determined from the reflectance of the wafer, exposure defects are extremely rare. FIG. 3 is a top view of a wafer for explaining a second embodiment of the present invention.

ウェハー105上に露光部A,B,C・・・の順に露光
を行なう場合、レジスト塗布前に露光部A,B,C・・
・の反射率をあらかじめ測定し、その測定データに応じ
て各露光部A,B,C・・・の最適露光量を求めておく
.ウエハー105上にレジストを塗布した後、求めた最
適露光量で露光を行なう. このように第2の実施例によれば、ウェハー105上の
各露光部ごとに最適露光量で露光できるため、ウェハー
上に被着されている被加工材の反射率が異っていても露
光不良の発生は抑制される. 〔発明の効果〕 以上説明したように本発明は、ウェハー表面の反射率を
求め、それをもとに最適露光量を決定するため、従来の
ようにテストウェハーによる露光,現像,寸法測定等の
時間をなくすことができ、またウェハー内で反射率にば
らつきがある場合でもパターン寸法が一定に形成できる
効果がある.従って信頼性及び製造歩留りの向上した集
積回路装置を得ることができる. ー、106・・・ウェハー台、107・・・ステージ、
108・・・防震台.
When exposing the exposed areas A, B, C, . . . on the wafer 105 in this order, the exposed areas A, B, C, . . . are exposed before applying the resist.
・Measure the reflectance of ・in advance, and find the optimal exposure amount for each exposed area A, B, C, etc. according to the measured data. After coating the resist on the wafer 105, exposure is performed using the determined optimum exposure amount. As described above, according to the second embodiment, each exposure area on the wafer 105 can be exposed with the optimum exposure amount, so even if the reflectance of the workpiece deposited on the wafer is different, the exposure can be performed. The occurrence of defects is suppressed. [Effects of the Invention] As explained above, the present invention determines the reflectance of the wafer surface and determines the optimum exposure amount based on the reflectance. This has the effect of saving time and making it possible to form patterns with constant dimensions even if there are variations in reflectance within the wafer. Therefore, an integrated circuit device with improved reliability and manufacturing yield can be obtained. -, 106... Wafer stand, 107... Stage,
108... Earthquake prevention stand.

Claims (1)

【特許請求の範囲】[Claims] 紫外光によりガラス基板上に形成されているパターンを
光感光性有機膜の塗布された半導体基板上に順次縮少投
影露光を行なう縮少投影露光方法において、あらかじめ
前記半導体基板表面に於ける前記紫外光に対する反射率
を測定し、該反射率に応じて前記半導体基板に対する露
光量を設定することを特徴とする縮少投影露光方法。
In a reduction projection exposure method in which a pattern formed on a glass substrate using ultraviolet light is sequentially subjected to reduction projection exposure onto a semiconductor substrate coated with a photosensitive organic film, the ultraviolet light on the surface of the semiconductor substrate is A reduction projection exposure method comprising measuring the reflectance of light and setting the amount of exposure to the semiconductor substrate according to the reflectance.
JP1052323A 1989-03-03 1989-03-03 Reduced projection exposure method Pending JPH02231706A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1052323A JPH02231706A (en) 1989-03-03 1989-03-03 Reduced projection exposure method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1052323A JPH02231706A (en) 1989-03-03 1989-03-03 Reduced projection exposure method

Publications (1)

Publication Number Publication Date
JPH02231706A true JPH02231706A (en) 1990-09-13

Family

ID=12911587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1052323A Pending JPH02231706A (en) 1989-03-03 1989-03-03 Reduced projection exposure method

Country Status (1)

Country Link
JP (1) JPH02231706A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008023693A1 (en) * 2006-08-24 2008-02-28 Tokyo Electron Limited Coating developing machine, resist pattern forming device, coating developing method, resist pattern forming method, and storage medium

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008023693A1 (en) * 2006-08-24 2008-02-28 Tokyo Electron Limited Coating developing machine, resist pattern forming device, coating developing method, resist pattern forming method, and storage medium

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