JPH0222885A - Manufacture of printed board - Google Patents
Manufacture of printed boardInfo
- Publication number
- JPH0222885A JPH0222885A JP17288088A JP17288088A JPH0222885A JP H0222885 A JPH0222885 A JP H0222885A JP 17288088 A JP17288088 A JP 17288088A JP 17288088 A JP17288088 A JP 17288088A JP H0222885 A JPH0222885 A JP H0222885A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- layer
- covering
- insulating
- shielding layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052802 copper Inorganic materials 0.000 abstract description 9
- 239000010949 copper Substances 0.000 abstract description 9
- 239000004020 conductor Substances 0.000 abstract description 3
- 238000001035 drying Methods 0.000 abstract description 3
- 239000011889 copper foil Substances 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 3
- 230000000191 radiation effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011253 protective coating Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
- H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
主ｌ上皇且里分立
本発明はプリント配線板の製造方法に関し、特に基板上
にプリント回路を形成し１回路の少なくとも一部に絶縁
層を被覆し、絶縁層の少な（とも一部にシールド層を被
覆するプリント配線板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a printed wiring board, and in particular to a method for manufacturing a printed wiring board, in which a printed circuit is formed on a board, at least a part of one circuit is coated with an insulating layer, and a method for manufacturing a printed wiring board is provided. (Both relate to a method of manufacturing a printed wiring board partially coated with a shield layer.
従米辺肢歪
上述の構成によるプリント配線板は既知であり例えば実
公昭５５−２９２７６号に記載される。このシールド層
は通常は銅ペーストの所要部分への全面被覆によって行
う。Printed wiring boards having the above configuration are known and are described, for example, in Japanese Utility Model Publication No. 55-29276. This shielding layer is usually formed by covering the entire surface with copper paste.
′しよ”と る
上記のシールド層被覆は通常は絶縁層のほぼ全面を銅ペ
ーストのシルク印刷によって被覆してマスクの新製を省
略する。しかし、この方法は銅ペーストの所要量が増加
し、放熱性が低下し、乾燥に際してクランクが生じ易い
。The above-mentioned method of covering the shield layer is usually done by covering almost the entire surface of the insulating layer by silk-screening copper paste, thereby omitting the need for a new mask. However, this method increases the amount of copper paste required. , heat dissipation is reduced and cranking is likely to occur during drying.
−゛ るための
上述の問題を解決するための本発明による方法は、シー
ルド層を網点とする。- The method according to the invention for solving the above-mentioned problem uses halftone dots in the shielding layer.
シールド層は連続した細線とすることもでき。The shielding layer can also be a continuous thin wire.
不連続の点とすることもできる。It can also be a discontinuous point.
立里
本発明の構成によって、銅ペーストの所要量は著しく減
少し、絶縁層の上を覆う平均厚さの減少によって放熱性
を阻害せず、乾燥に際してのシールド層の影響はなくな
る。シールド層の印刷の手数は既知の場合とほぼ同様で
あり、網点のマスクのみが付加される。By virtue of the configuration of the present invention, the amount of copper paste required is significantly reduced, the reduction in average thickness overlying the insulating layer does not impede heat dissipation, and the effect of the shielding layer on drying is eliminated. The number of steps for printing the shield layer is almost the same as in the known case, and only the halftone dot mask is added.
実施輿
本発明を例示とした実施例並びに図面について説明する
。Embodiments Examples and drawings illustrating the present invention will be described.
図はプリント配線板の一部を示し、絶縁基板１０の片面
又は両面に銅箔を被覆して周知の方法によってプリント
配線回路１２を形成する。回路導体Ｉ２の所要範囲に絶
縁ペーストをシルク印刷等によって被覆して絶縁Ｗ１１
４を形成する。絶縁［１４の全面又は一部に銅ペースト
をシルク印刷等によって被覆してシールド層１６を形成
する０通常の作業においては、別個のマスクを準備する
のを省略するために絶縁層を形成するマスクを使用して
絶縁Ｊｉｉ１４の全面にシールド層１６を被覆する。シ
ールド層１６は接地端子１８に接続する。所要に応じて
シールドＦｉｌ１６の上に保護液［ｔＩ２０を被覆する
。The figure shows a part of a printed wiring board, in which one or both sides of an insulating substrate 10 is coated with copper foil to form a printed wiring circuit 12 by a well-known method. The required range of the circuit conductor I2 is coated with insulation paste by silk printing etc. to insulate it W11.
form 4. A mask that forms an insulating layer in order to omit preparing a separate mask in normal operations. The shield layer 16 is coated on the entire surface of the insulating Jii 14 using the following method. Shield layer 16 is connected to ground terminal 18 . A protective liquid [tI20 is coated on the shield Fil16 as required.
上述の過程は既知であり、広く使用される。しかし、こ
の方法では１ｗ４ペーストの使用量が多くなり、放熱効
果が減少し、ペーストが厚くなるため熱膨張収縮が大き
く塗膜の亀裂を生ずることがあり寸法安定性に欠ける。The processes described above are known and widely used. However, in this method, the amount of 1w4 paste used is large, the heat dissipation effect is reduced, and the paste becomes thick, resulting in large thermal expansion and contraction, which may cause cracks in the coating film, resulting in a lack of dimensional stability.
本発明によって、シールド層１６を網点２２によって形
成する。好適な方法は不連続の多数の点によって例えば
第１図に示す網模様を形成したマスクを使用して銅ペー
ストを絶縁Ｆｉ１４の上にシルク印刷して形成する。絶
縁１ｉ！１４上に形成されたパターンはほぼ連続した細
線としたシールド［１６となり接地端子１８によって導
電接続される。所要に応じて最初から網を連続した細線
で形成することもでき、マスク上の不連続の点の配置を
網以外のバタンで形成することもでき、はぼ同様の効果
を得られる。According to the invention, the shielding layer 16 is formed by halftone dots 22 . A preferred method is to silk-print the copper paste onto the insulating film 14 using a mask in which a mesh pattern as shown in FIG. 1 is formed by a large number of discontinuous points. Insulation 1i! The pattern formed on the shield 14 becomes a substantially continuous thin wire shield [16], which is electrically connected by the ground terminal 18. If necessary, the net can be formed from the beginning with continuous thin lines, or the arrangement of discontinuous points on the mask can be formed with battens other than the net, and the same effect can be obtained.
漿果
本発明によってシールド層１６を網点て形成することに
よって回路１２上の塗ＩＩＦｉ！の厚さは著しく減少す
る。従って、従来の技法に比較して銅ペーストの所要量
は著しく減少し、放熱効果を阻害せず寸法安定性は高い
、網点形成用のマスクは簡単に製造できる。かくして本
発明は経済上、実用上に有利である。According to the present invention, coating IIFi on the circuit 12 can be achieved by forming the shield layer 16 in a dot pattern. The thickness is significantly reduced. Therefore, compared to conventional techniques, the amount of copper paste required is significantly reduced, and a mask for halftone dot formation that does not impede the heat dissipation effect and has high dimensional stability can be easily manufactured. Thus, the present invention is economically and practically advantageous.
第１図は本発明によるプリント配線板の一部の平面図、
第２ｔ！Ｉは第１図の一部の断面図である。
１０、、基板 １２．１回路導体 １４０．絶縁層１６
０．シールド層 １８６．接地端子 ２０．、保護被膜
２２、．８点FIG. 1 is a plan view of a part of a printed wiring board according to the present invention;
2nd t! I is a sectional view of a portion of FIG. 1; 10. Substrate 12.1 Circuit conductor 140. Insulating layer 16
0. Shield layer 186. Ground terminal 20. , protective coating 22, . 8 points
Claims (3)
一部に絶縁層を被覆し，絶縁層の少なくとも一部にシー
ルド層を被覆する場合に， 該シールド層を網点によって形成することを特徴とする
プリント配線板の製造方法。1. When a printed circuit is formed on a substrate, at least a part of the circuit is covered with an insulating layer, and at least a part of the insulating layer is covered with a shield layer, the shield layer is formed by halftone dots. A method for manufacturing printed wiring boards.
項１記載の製造方法。2. 2. The manufacturing method according to claim 1, wherein the halftone dots have a net shape formed by continuous thin lines.
ンとして形成する請求項１記載の製造方法。3. 2. The manufacturing method according to claim 1, wherein the halftone dots are formed as a desired pattern by a large number of discontinuous dots.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17288088A JPH0222885A (en) | 1988-07-12 | 1988-07-12 | Manufacture of printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17288088A JPH0222885A (en) | 1988-07-12 | 1988-07-12 | Manufacture of printed board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0222885A true JPH0222885A (en) | 1990-01-25 |
Family
ID=15950025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17288088A Pending JPH0222885A (en) | 1988-07-12 | 1988-07-12 | Manufacture of printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0222885A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2247570A (en) * | 1990-07-20 | 1992-03-04 | Nippon Cmk Kk | Cross-mesh shielded P.C.B. |
| US7132599B2 (en) | 2003-03-10 | 2006-11-07 | Denso Corporation | Circuit board |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5529276U (en) * | 1978-08-16 | 1980-02-26 | ||
| JPS63142889A (en) * | 1986-12-05 | 1988-06-15 | 日立エーアイシー株式会社 | Printed wiring board |
-
1988
- 1988-07-12 JP JP17288088A patent/JPH0222885A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5529276U (en) * | 1978-08-16 | 1980-02-26 | ||
| JPS63142889A (en) * | 1986-12-05 | 1988-06-15 | 日立エーアイシー株式会社 | Printed wiring board |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2247570A (en) * | 1990-07-20 | 1992-03-04 | Nippon Cmk Kk | Cross-mesh shielded P.C.B. |
| GB2247570B (en) * | 1990-07-20 | 1994-07-20 | Nippon Cmk Kk | A method of manufacturing a printed circuit board |
| US7132599B2 (en) | 2003-03-10 | 2006-11-07 | Denso Corporation | Circuit board |
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