JPH02228851A - Data demodulation system - Google Patents

Abstract

PURPOSE:To surely monitor and adjust the state of a demodulation circuit by providing a control voltage generating circuit outputting an upper limit when an integration value of the control signal exceeds a preset upper limit value and outputting the integration value as it is when smaller. CONSTITUTION:An output of an identification (A/D converter) 2 is inputted to an arithmetic circuit 5 through a delay circuit 4 and an output of a decoder (error correction circuit) 3 is inputted to the arithmetic circuit 5, the output difference is taken to obtain an error signal. A control signal generating circuit 6 generates a control signal according to a prescribed logic, a control voltage generating circuit 7 integrates an error signal and inputs a predetermined upper limit value when the integration value is larger than the upper limit value and inputs an output of the integration circuit as it is when the integration value is smaller than the upper limit to a clock adjustment circuit 8 to control a demodulator 1. Thus, the level of the control voltage is increased and the change in the control voltage near a level when a clock phase error is zero is increased, the state of the demodulator is surely monitored or adjusted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data demodulation system that can improve data transmission characteristics by reliably monitoring and adjusting the state of a demodulation circuit.

[Conventional technology]

Recently, a coded modulation technique that uses convolutional codes and maximum likelihood decoding as a coded modulation method and can obtain a large coding gain without expanding the signal bandwidth has attracted attention (for example, G., Ugerboeck et al. , “T.
rell 1s-Coded Modulation
n with Redundant SLgnal
5ets, IEEE COM.

Mag, Feb. 1987. (See pp. 5-21).

Various applications of this technology are being considered, mainly in the fields of data transmission modems and satellite communications. Normally, when a signal passes through a transmission path, it is affected by various noises and distortions, so when using a code modulation circuit on the transmitting side, it must be combined with a waveform equalizer such as a transversal equalizer. A transmission device is often configured using On the other hand, on the receiving side, it is necessary to provide a carrier wave regeneration circuit necessary for carrier wave recovery. In controlling the 5-equalizer and regenerating the carrier wave, an error signal indicating the magnitude and polarity of the error between the originally transmitted signal and the actually received signal is required. This error signal is processed by the clock synchronization circuit, automatic gain control (
AGC) circuit and drift compensation circuit (for example, Y, Nakan+ura, et, al, "2
56Q A M Modem for 1ult
icarrier 400 Mbit/s dig
ital radio” IEEE EJ, 5s
lact, Areas Cou+n+un, Vol.
(See SAC-5° No. 3 April 1987).

Accurately and quickly detecting the error signal indicating the size and polarity of the error mentioned above requires these clock synchronization circuits,
It is extremely important for automatic gain control circuits, drift compensation circuits, etc.

As a transmission device using the above-mentioned coded modulation technique, for example, the "data demodulation device" described in Japanese Patent Application Laid-open No. 190934/1982 or the patent application No. 3135/1983
There is a "data demodulation device" described in the No. 03 specification and drawings. In each of the above schemes, the error detected between the input and output of the Viterbi decoding circuit is used as the error signal.

Usually, in a transmission device equipped with an error correction circuit using coded modulation, etc., the error signal is extracted from (a) the output of the identification circuit (A/D converter), and (b) 1! A method of obtaining the signal from between the output of another circuit and the output of the error correction circuit has been considered.

As in (a) above, when the error signal is obtained from the output of the identification circuit (A/D converter), the identification circuit is located before the error correction circuit, so error correction is not performed on the identification circuit output signal. It has not been. Therefore, code errors are likely to occur due to noise in the transmission path, and as a result, accurate error signals may not be obtained. Using the error signal obtained in this manner, it is impossible to accurately control the equalizer and carrier wave regeneration circuit.

On the other hand, when the error signal is obtained from between the input and output of the error correction circuit as in (b) above, the error correction circuit reduces the probability of code error occurrence during steady state (when the C/N of the transmission path is high). Since the error signal is sufficiently suppressed, a more accurate error signal can be obtained compared to the method (a) described above.

Furthermore, in order to obtain an accurate error signal, it is effective to calculate the error signal to a finer value. (c) For this reason, there is a method of using a plurality of lower bits of the identification circuit as an error signal.

[Problem to be solved by the invention]

FIG. 2 is a diagram showing the relationship between a conventional clock error and a control signal, and shows a case where the lower one bit of the output of the identification circuit is used in the clock synchronization circuit and a case where three bits are used. The vertical axis shows the control voltage normalized so that the maximum value is 1, and the horizontal axis shows the clock phase error. The thick line indicates the case where the lower 1 bit of the identification circuit is used as an error signal and the error signal is extracted in the stage before the error correction circuit, that is, the identification circuit, and the clock phase at the time when the control voltage is returned to 0, that is, the pseudo pull-in point. The error is 10.5 degrees, whereas the broken line shows the case where the lower 3 bits of the identification circuit are used as the error signal and the error signal is extracted from the output of the error correction circuit at the stage after the error correction circuit. , the clock phase error at the pseudo pull-in point is 13.5 degrees. Second
As is clear from the figure, when the lower 3 bits are used, the pseudo-attraction point where the polarity is reversed becomes larger, making it difficult for pseudo-attraction to occur. However, since the area of the shaded portion in FIG. 1 becomes smaller, there is also a disadvantage that the control voltage becomes smaller. The reason for this is that if the lower 3 bits are used to normalize the control voltage to the maximum value, the control voltage will become smaller and its change will become smaller at locations where one phase error is small. In order to accurately monitor and adjust the state of the demodulator, it is necessary to increase the point at which the polarity is reversed to make it difficult for false pull-in to occur.
It is also desirable to increase the control voltage.

The purpose of the present invention is to solve such conventional problems, to increase the control voltage for monitoring and adjusting the state of the demodulator, and to increase the control voltage change in the vicinity where the error is O, thereby ensuring reliable operation. An object of the present invention is to provide a data demodulation system that can monitor and adjust the state of a demodulation circuit.

[Means to solve the problem]

In order to achieve the above object, the data demodulation system of the present invention includes an identification circuit that inputs a received signal, identifies the signal, and reproduces the signal, and an output signal of the identification circuit that inputs the signal and performs error correction. an error correction circuit; an error detection means that generates an error signal from the output of the identification circuit and the output of the error correction circuit; and a control signal generation circuit that receives the error signal and generates a control signal according to predetermined logic. In a data demodulation system having the above, if the integral value obtained by integrating the control signal is larger than a preset upper limit value, the upper limit value is output; and if the integral value obtained by integrating the control signal is smaller than the above upper limit value. The present invention is characterized in that a control voltage generation circuit is provided that outputs the integral value as it is, and the output of the control voltage generation circuit is used to monitor or adjust the state of the circuit before the identification circuit.

[For production]

In the present invention, in order to control a data demodulator etc. using an accurate error signal, the lower bits of the identification circuit are used as an error signal, and a control signal is generated from the error signal according to a predetermined logic. By outputting the integrated value of the control signal.

When controlling clock timing adjustment, waveform equalizer, carrier wave control, AGC, etc., if the integrated value of the control signal does not reach the preset upper limit,
The integrated value is used as the output, and if the value reaches this upper limit value, this upper limit value is used as the output. As a result, it is possible to increase the magnitude of the control voltage, as is clear from the characteristic diagram of the relationship between the clock phase error and the control voltage (see Figure 7), and the control voltage in the vicinity where the clock phase error becomes 0 Since the changes can be large, the state of the demodulator can be reliably monitored or adjusted.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a data demodulation system showing an embodiment of the present invention, and shows a case where an error signal from a demodulated signal is applied to a clock adjustment circuit.

In FIG. 1, 1 is a demodulator provided on the receiving side, 2 is an identification circuit (A/D converter), and 3 is a decoder.

4 is a delay circuit to match the delay time caused by the decoder;
5 is a circuit that takes the difference between the decoded signal and the delayed identification signal; 6
7 is a circuit that generates a control signal based on a fixed logic; 7 is a control voltage generation circuit that integrates the control signal and generates a control voltage from the integrated value; and 8 is a clock adjustment circuit.

The output of the identification circuit (A/D converter) 2 is input to the arithmetic circuit 5 through the delay circuit 4, and the output of the decoder (error correction circuit) 3 is also input to the delay circuit 4. The error signal is obtained by taking the difference between the outputs. By inputting this error signal to the control signal generation circuit 6, the control signal generation circuit 6 generates a control signal according to a certain logic and inputs it to the control voltage generation circuit 7. The control voltage generation circuit 7 integrates the error signal, and if the integral value is larger than a predetermined upper limit value, the upper limit value is input to the clock adjustment circuit 8, while if the integral value is smaller than the upper limit value In this case, the output of the integrating circuit is directly input to the clock adjusting circuit 8 as the output of the control voltage generating circuit 7.

The demodulator 1 on the receiving side is controlled by the clock output of the clock adjustment circuit 8.

FIG. 3 is a configuration diagram of the control voltage generation circuit in FIG. 1.

In FIG. 3, 31 is an integrator that integrates the input control signal, 32 is a comparator that receives the output of the integrating circuit 31 and an upper limit value, and compares the two values.33 is the integrator that integrates the input control signal. If the output of the integrating circuit 31 is larger than the upper limit value, the upper limit value is taken out as the selector output, and in other cases, the output of the integrating circuit 31 is taken as it is as the selector output.

FIG. 4 is a characteristic diagram showing the relationship between the output of the integrating circuit and the output of the selector in FIG. 3.

The integrated value increases from the intersection point O of both wheels toward both poles, but when the integrated value reaches a predetermined upper limit value, that upper limit value is used as the selector output, and the upper limit value of both polarities is reached. Until then, the integral value is used as the selector output.

FIG. 5 is a detailed diagram of the control signal generation circuit in FIG. 1. The circuits other than the control signal generation circuit 6 are exactly the same as those shown in FIG.

In FIG. 5, 1 is a demodulator, 2 is an identification circuit, 3 is a decoder, 4 is a delay circuit that delays the time corresponding to the decoder, and 5 is a difference between the decoded signal and the delayed identification signal. A circuit for calculating signals, 6 is a control signal generation circuit, 7 is a control voltage generation circuit, and 8 is a clock synchronization circuit that uses the integrator output as a control signal.

The control signal generation circuit 6 includes a delay circuit 14. Multiplication circuit 11.
12 is an exclusive NOA circuit (hereinafter referred to as EX-NO
R circuit), flip-flop 13, comparison circuit 9,
10. It is composed of delay circuits 15 and 16. Delay circuit 14 delays the decoded signal by two time slots, and delay circuits 15 and 16 delay the decoded signal by one time slot. Comparing circuits 9 and 1o.

By comparing the relationship between the previous and subsequent levels, it is determined whether the level will go up or down. The multiplication circuit 11 is.

A multiplication operation is performed to convert the polarity of the error signal to the polarity of the clock error. The EX-NOR circuit 12 outputs a signal only when the directions of change in the previous and subsequent levels are the same.

Flip-flop 13 is used when the directions of changes in the levels before and after are not equal.

Holds the signal of the previous time slot.

FIG. 6 is a diagram showing the operating principle of the control signal generation circuit in FIG. 5, and shows a method of using an error signal as a clock adjustment signal.

In FIG. 6, time is plotted in the horizontal direction and signal level is plotted in the vertical direction. The solid line shows the case where the clock is accurate, and the broken line shows the case where the clock is delayed.

In the case of locking as shown by the broken line, the signal level deviates (lags) from the actual level, resulting in an error. Regarding the polarity of the error, when the level increases before and after time 2, the level is higher than the correct level, and conversely, when the level decreases before and after, the level becomes lower than the correct level.

When the clock is ahead, contrary to the characteristics shown in Figure 6,
Until clock 3, it falls below the correct level, and clock 3
From the point beyond this point, the level rises above the correct level.

Furthermore, as at time 3, when the level increases before that time and decreases after that time, the polarity of the error will decrease whether the clock is ahead or behind.

Utilizing the above operating principle, the polarity of the error signal is converted into a 6-step error, which is used as a control signal for the clock adjustment circuit 8, while determining changes in level at previous and subsequent times.

The control signal generation circuit 6 in FIG. 5 generates a signal in which the output of the decoder 3, that is, the decoded signal, is delayed by one time slot and two time slots in the delay circuits 15 and 16, and a signal without delay is generated in the comparison circuit 9. The comparator circuit 10 compares the signal delayed by one time slot with the signal delayed by one time slot to determine whether or not it has increased.The comparison circuit 10 compares the signal delayed by one time slot with the signal delayed by two time slots to determine whether this signal has also increased. Determine whether or not there is. On the other hand, the difference signal output of the arithmetic circuit 5 is delayed by two time slots in the delay circuit 14 to match the time slot of the comparator circuit 10, and then inputted to the multiplication circuit 11 to change the polarity of the error signal to the polarity of the clock error. Convert. Now, if the error signal is rising as shown by the broken lines at clocks 1 and 2 in FIG.

Since the result output of both comparison circuits 9 and 1o is 11',
The output of the ER-NOR circuit 12 becomes Ill. In this case, in the multiplication circuit 11, as shown by clocks 1 and 2 in FIG. 6, it is necessary to advance the broken line to make it a solid line, so the result is 1'. When it is necessary to delay, use “O
'. Therefore, here, 1' is input to the clock terminal of the flip-flop 13, and 11' is input to the data terminal, so the flip-flop 13 is set, and the set output '1' is sent from the Q terminal to the control voltage generation circuit 7. It will be done.

FIG. 7 is a characteristic diagram when the present invention is used as a control voltage for clock synchronization.

Similarly to FIG. 2, in FIG. 7, the horizontal axis shows the clock phase error, and the vertical axis shows the control voltage. The control voltages are each normalized so that the maximum value is 1.

The broken line shows the conventional method, in which the signal after error correction is used and the error signal is expressed in 3 bits; the control voltage has no upper limit and is simply proportional to the integral value of the control signal. The value is output as is. On the contrary.

The solid line corresponds to the present invention, in which a value proportional to the integral value is output until the upper limit is reached, and after the upper limit is reached, the upper limit is output. Good results can be obtained with the pseudo pull-in point at 13.5 degrees for both.6th order, the result of adding the control voltage in the range from 0 degrees to 13.5 degrees is 6.0 degrees for the conventional method. On the other hand, the method of the present invention has a value of 13.5. This value is the magnitude of the control voltage, so the larger it is, the better. Therefore, the present invention has been shown to be fully effective.

Note that different logic circuits are used for the control signal generation circuit 6 depending on the application, such as a waveform equalizer, carrier wave control, AGC1 DC drift compensation, or clock timing adjustment.

〔Effect of the invention〕

As described above, according to the present invention, the pseudo-pulling point is large, making it difficult for pseudo-pulling to occur, and the control voltage for monitoring and adjusting the state of the demodulator can be increased, and furthermore, the error can be reduced to 0. Since it is possible to increase the change in control voltage in the vicinity of , it is possible to reliably monitor and adjust the state of the demodulator and improve the characteristics of the data transmission device.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram of a data demodulation system showing an embodiment of the present invention, FIG. 2 is a characteristic diagram showing the relationship between a conventional clock error and a control signal, and FIG. 3 is a control voltage generation circuit in FIG. 1. , FIG. 4 is an operational characteristic diagram of the control voltage generation circuit in FIG. 3, FIG. 5 is a detailed block diagram of the control signal generation circuit in FIG. 1, and FIG. 6 is a detailed block diagram of the control signal generation circuit in FIG. 5. FIG. 7 is a diagram showing the principle of control signal generation, and FIG. 7 is a comparative characteristic diagram when the present invention is used as a control voltage for clock synchronization. 1: Demodulator, 2: Identification circuit (A/D converter), 3: Decoder, 4: Delay circuit, 5: Arithmetic circuit (circuit that takes difference),
6: Control signal generation circuit, 7: Control voltage generation circuit, 8: Clock synchronization circuit, 31: Integrator, 32: Comparator, 33:
Selector, 9, 10: Comparator, 14, 15.16: Time slot delay circuit, 11: Multiplication circuit, 12: EX-N
OR circuit, 13: Flip-flop diagram

Claims (1)

[Claims] (1) An identification circuit that inputs a received signal to identify and reproduce the signal, an error correction circuit that inputs the output signal of the identification circuit and performs error correction, and the output of the identification circuit and the above. In a data demodulation system having an error detection means that generates an error signal from the output of an error correction circuit, and a control signal generation circuit that inputs the error signal and generates a control signal according to a predetermined logic, A control voltage that outputs the upper limit when the integrated value is larger than a preset upper limit, and outputs the integrated value as it is when the integrated value of the control signal is smaller than the upper limit. 1. A data demodulation system, comprising: a generation circuit; and the output of the control voltage generation circuit is used to monitor or adjust the state of a circuit before the identification circuit.