JPH02226763A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To facilitate the manufacture of a fine memory cell by a method wherein, in a semiconductor storage device constituting one switching transistor and one charge storage capacitor as minimum units, both a channel region and a source.drain region are not parallel to both word lines and bit lines. CONSTITUTION:A semiconductor device is constituted of the following; active regions 1.1, word lines 1.2, bit line contact holes 1.3, bit lines 1.4, storage capacitor part contact holes 1.5, and the lower electrode 1.6 of a charge storage capacitor. A special feature of this method in the above-mentioned constitution is that, in order to make the word line 1.2 secure a sufficient channel length, the width is wide in the active region and narrow in an element isolation oxide film forming part. That is, a part of the active region 1.1 is constituted of a region inclined at 45 deg. to the word line 1.2, and a region rectangular to the word line. Thereby, a fine cell required for a DRAM of, e.g. 16 megabit level can be manufactured by an ordinary photolithography method.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor memory device that is minute and has a large storage capacity as a stacked capacitor cell of a dynamic random access memory (DRAM) suitable for high integration. It is something.

[Conventional technology]

DRAM (Dynamic Random Access
ss Memory) has achieved a fourfold increase in integration density in three years, and mass production of megabit memory has already begun. This high degree of integration has been achieved by miniaturizing element dimensions. However, due to the reduction in storage capacity associated with miniaturization, adverse effects such as a decline in the signal-to-noise (S/N) ratio and signal inversion due to the incidence of alpha rays have become apparent, and maintaining reliability has become an issue. .

For this reason, as a memory cell that can increase the storage capacity, as described in Japanese Patent Publication No. 61-55528, a stacked structure in which a part of the storage capacitance part is stacked on a switching transistor or an isolation oxide film between elements is proposed. Capacitive cell (S
TC: S Tacked Capacitor c
(all) have come to be expected to replace conventional planar capacitor cells.

A plan layout diagram of a conventional STC cell is shown in Fig. 2.
Here, 2.1 is the active region where the channel region and impurity diffusion layer of the switching transistor are formed;
．． 2 is a word line that becomes the gate electrode of a switching transistor, 2.3 is a contact hole for contacting the bit line 2.8 and the diffusion layer of the substrate, 2.4 is a bit, 12.8
2.5 is a contact hole for connecting storage capacitor lower electrode 2.6 and the diffusion layer, 2.7 is a plate electrode, and 2.8 is a bit line. . In the STC cell, the storage capacitor lower electrode 2.6 can extend above the word line 2.2, so that
Compared to planar cells that use only the substrate surface as a storage capacitor, it is possible to achieve a much larger storage capacity, making it possible to secure sufficient storage capacity for circuit operation even with the small cell area used in megabit DRAM. Become. On the other hand, in conventional planar cells, it is difficult to achieve sufficient capacity with the same cell area even if the capacitor insulating film is made thinner.

[Problem to be solved by the invention]

However, the above-mentioned STC cell has various problems as described below. This will be explained in detail using the cross-sectional structure shown in FIG. This STC cell is manufactured through the following steps. First, a relatively thick oxide film 4.2 for electrically isolating each element is grown on a single crystal semiconductor substrate 4.1 using a known thermal oxidation method. The film thickness is approximately 100 to 11000 nm. Next, the gate insulating film 4.3 of the switching transistor is grown using a known thermal oxidation method. The film thickness becomes thinner with the miniaturization of element dimensions, and 10 to 50 nm is now used. Polycrystalline silicon containing impurities is deposited as the word line 4.4, and processed using a known photolithography method or dry etching method. Furthermore, using the processed word line 4.4 as a mask, an impurity having a conductivity type different from that of the substrate 4.1 is introduced by a known ion implantation method to form an impurity diffusion layer 4.5. Needless to say, heat treatment is necessary to activate the impurity diffusion layer. Next, in order to form a charge storage capacitor section 4.7, polycrystalline silicon 4.7 of the same conductivity type is placed in contact with the impurity diffusion layer in the substrate.
using the well-known CVD (Chemical Vapor D)
deposition method. As is clear from the plan view of FIG. 2, the polycrystalline silicon 4.7 is also formed on the word line 4.4 and the element isolation film 4.2, so that the storage capacitance portion 4.7 is The area increases, and as a result, a large storage capacity can be secured.

At this time, polycrystalline silicon is also simultaneously formed at a location where a contact hole (2.3 in FIG. 2) between the bit line 4.11 and the impurity diffusion layer is formed. Therefore, even if the distance between the word lines is small, there is a risk of an electrical short between the bit line 4.11 and the word line 4.4 through the polycrystalline silicon layer (2.4 in Figure 2). connection with the diffusion layer. In addition, here 4.6 and 4.10
is an interlayer insulating film.

However, in an STC cell with a conventional structure, the plate electrode 4.
9, the pad conductor layer 2.4 must be exposed. Therefore, in order to prevent the pad conductor layer from being scraped during processing of the plate electrode, a very thin capacitor insulation@4.8 is also formed on the surface of the pad conductor layer.
Therefore, advanced technology is required to stop the dry etching process on the plate. In addition to these manufacturing problems, the cell structure described above has the essential problem that it is difficult to reduce the cell area. This is plate electrode 4.9
In order to prevent contact between the pad conductor layer 2.4 and the pad conductor layer 2.4,
This is due to the fact that sufficient spacing must be maintained. It is also possible to delete the pad conductor layer 2.4, but in that case, the bit line 4.11 and the word line 4.
．． In order to prevent short circuits with word lines 4 and 4, the distance between word lines 4 and 4 must be increased, which also makes it difficult to reduce the cell area.

As described above, it is difficult to reduce the cell area with the conventional STC structure, and the conventional STC cannot be used in ultra-highly integrated DRAMs of 4 megabits or more.

As an STC structure to solve these problems,
There is one described in No.-178894. FIG. 3 shows a plan layout of the STC cell described above. For simplicity, the memory part contact hole 3.
The storage capacitor lower electrode and plate electrode disposed above 4 are omitted.

A feature of this structure is that, in the active region 3.1, the bit line 3.5 is not arranged above the portion where the memory section contact hole 3.4 opens.

Of course, the bit line 3.5 is in contact with the impurity diffusion layer of the substrate through the contact hole 3.3. The storage capacitor section is formed after the bit lines are formed. In this way, there is no need to expose the bit line contact portion as shown in FIGS. 2 and 4 when forming the plate electrode.

That is, the plate electrode only needs to cover the memory cell portion.

Although the cell area is reduced by the above-described cell structure, the area of the storage capacitor lower electrode is not limited by the processing of the plate electrode, so a large storage capacitance can be achieved.

However, even in the above structure, it is very difficult to reduce the distance between the bit lines simply by preventing the bit lines 3.5 and the active region 3.1, which are arranged in parallel, from overlapping each other. In the layout shown in FIG. 3, the bit line spacing is wide, and there is a limit to the reduction in cell area.

An object of the present invention is to obtain an even finer STC structure for use in an ultra-highly integrated DRAM of megabits or more.

[Means to solve the problem]

FIG. 1 shows a plan view of a memory cell according to the present invention. In the present invention, the main part of the active region 1.1 is In the present invention, in order to arrange the active regions most densely, they are arranged at an angle of 45 degrees to the word line and bit line, and the memory contact hole 1.5 is opened. Only the portion where the bit line 1.4 is connected is arranged parallel to the bit line 1.4. Moreover, the four active areas closest to one active area are
The main parts were made to be orthogonal. That is, bit line contact hole 1.1 in one active region 1.1.
With the center of 3 as the origin, the component parallel to word line 1.2 at the distance between each bit line contact hole is DP,
If the component parallel to the bit line 1.4 is WP, the centers of the bit line contact holes in the four active regions closest to the active region are (-wP+Dp), (
-Wpt-Dp), (WpeDp)-(Wp+-DP)
Therefore, each shape is an inversion of the central active area. Note that a memory array is constructed by using the plane layout diagram shown in FIG. 1 as a unit and repeatedly arranging it many times. Here, 1.3 is the bit line contact hole, 1.6 is the storage capacitor lower electrode, and 1.7 is the bit line contact hole.
is a plate electrode.

FIG. 5 shows a cross-sectional view of the STC structure of the present invention.1 In the present invention, the active region is arranged diagonally with respect to the word line and bit line, so the cross-sectional view shows a pair of memory cells. A piece cut along the line connecting the centers of the contact holes 1.5 is used.

The active region in the present invention is simply oblique, and the method of forming it is no different from the conventional method.
An element isolation oxide film as shown in 5.2 is grown on the substrate 5.1.

In the invention shown in FIG. 1, the word line is inclined with respect to the active region, but the gate length is determined by the shortest distance in the word line. Moreover, the manufacturing method is also the same as the conventional one.

Note that this word line is insulated from other conductive layers in a self-aligned manner by the interlayer insulating film shown in 5.6. Further, although the source/drain has a simple impurity diffusion layer structure in this cross-sectional view, it is also possible to use a known electric field relaxation type source/drain diffusion layer structure. After forming the diffusion layer, bit line 5.7 is formed, which is also word line 5.
．． Similarly to 4, insulation is performed in a self-aligned manner using an insulating film 5.8. In the cross-sectional view of FIG. 5, the pad conductor layer 2 of FIG.
There is a bit line 5.7 having the same shape as 4.

In this way, when a lattice is formed by the word line 5.4 and the bit line 5.7, the valley formed by the word line 5.4 and the bit line 5.7 is To,
A pair of diffusion layers in the active region 1.1 now represent the surface. On top of this, the lower electrodes 1.6 and 5 of the storage capacitor section
．． form 9. Furthermore, the lower electrodes 1.6 and 5.
After processing 9, capacitor insulating film 5. Make lO,
A plate electrode 5.11 is made on it.

Naturally, the plate electrodes 5.11 do not need to be processed as shown in FIGS. 2 and 4 on the memory array. Note that 5.12 is an insulating film between the eyebrows on the plate electrode 5.11, on which An and the like are wired, but it is omitted here.

[Effect]

By using the active area shape and arrangement as shown above,
Layout interference between bit lines 3.5, which is a problem in the conventional structure shown in FIG. 3, is eliminated, and the bit line pitch can be significantly reduced. That is, in the conventional structure, the bit line 3.5 passes through only one side of the memory contact hole 3.4, but in FIG.
．． 5 is surrounded by two bit lines 1.4.

Also, as mentioned above, by insulating the word line 1.2 and bit line 1.4 from other conductor layers in a self-aligned manner,
Not only the word line pitch is reduced, but also the storage capacitor part 1.6
and 5.9 are in contact with the substrate memory part contact hole 1
．． 5 can be opened in a self-aligned manner.

With the configuration of the memory cell described above, the first memory cell is a micro-area memory cell that can configure an ultra-highly integrated DRAM of 4 megabits or more.
This can be achieved as shown in the figure. Moreover, unlike the conventional STC structure shown in FIG.
Since there is no area restriction on the shape of the 1, it is possible to arrange them evenly with the minimum additional space. In addition, the S of the present invention
In the TC structure, the bit line 1.4 is connected to the plate electrodes 1.7 and 5.11 whose potential is fixed, and the storage capacitor lower electrode 1.
．． 6 and 5.9, the line-to-line capacitance between the bit lines is greatly reduced, which also has the effect of reducing memory array noise compared to conventional structures.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing a first embodiment of a semiconductor memory device according to the present invention, FIG. 5 is a cross-sectional view of the memory cell shown in the above embodiment, and FIG. 6 shows the shape of the active region and the shape of the channel region. 7 is a plan view of a memory cell showing a second embodiment of the present invention, FIG. 8 is a plan view of a memory cell showing a third embodiment of the present invention, and FIG. 9 is a plan view of a memory cell showing a third embodiment of the present invention. FIG. 10 is a plan view of a memory cell showing a fourth embodiment of the invention, and FIG. 10 is a plan view of a memory cell showing a fifth embodiment of the invention.

First Embodiment In FIG. 1 showing the first embodiment, FIG. 6 shows the shape of the main parts that characterize the present invention.

To simplify the explanation, only the active area 1.1 and the word line 1.2 are shown. Word lines 1 and 2 must have a sufficient channel length, so they are wide on the active area and thin in the area where the element isolation oxide film is formed, but the overall width is similar to that of conventional memory. Like cells, they are parallel to the long or short sides of the memory chip.

If an attempt is made to arrange the active region in the most dense manner according to the layout rules while realizing the memory cell structure of the present invention, the main inclined portion will be at an angle of 45 degrees with respect to the word line 1.2, as described above. However, simply arranging a rectangular active region tilted at 45 degrees with respect to the word line will cause adjacent active regions to interfere with each other, making it necessary to increase the cell area in order to satisfy element isolation characteristics. Must be. That is, if the cell area remains small, it is not possible to secure a portion where the storage capacitor lower electrodes 1.6 and 5.9 contact the active region after forming the bit line 1.4.

In order to solve this problem, as shown in Figure 6, a part of the active area 1.1 should be made up of an area at 45 degrees to the word line 1.2 and an area at right angles. As a result, for the bit s1.4 which is orthogonal to the word line 1.2, the active region has a region parallel to the region intersecting at 45 degrees. By the way, as the portion of the active region parallel to the bit line 1.4 becomes longer, the portion where the storage capacitor lower electrode (for example, 1.6 in FIG. 1 or 5.9 in FIG. 5) contacts the substrate becomes larger. This is preferable from the perspective of improving the conduction characteristics between the two, but in order to ensure the isolation characteristics between the adjacent active regions, it is necessary to secure more space than is allowed by the layout rules. However, the layout pattern The vertices of are rounded due to the limitations of the known photolithography method, so in actual layouts, where vertices or vertices or straight lines face each other, the space can be made smaller than in the layout rules. In the active region of FIG. 6, the distance between parallel patterns is 0.
Although the space is 7 μm or more, the narrowest space where the vertex and the straight line face each other is 0.5 μm. However, any space on the resist pattern is 0.
．． 7 μm or more has been secured.

Furthermore, if layout rules must be strictly followed, sufficient space can be secured by making a notch at the apex without impairing the conduction characteristics described above.

The shape of the channel region of the memory transistor where the active region and the word line overlap is determined by the setting of the gate length, that is, the width of the word line. If the gate length can be short, the 0 point on the active region 1.1 in FIG. 6 is outside the word line 1.2, so the channel region becomes a pentagon, and the interior angles of each vertex are: 0245 degrees, E=135 degrees, F290 degrees, A=
135 degrees, B=135 degrees. On the other hand, when the gate length is increased, the channel region becomes hexagonal, and the interior angle of the apex is 0.
245 degrees, D=225 degrees, E=90 degrees, F290 degrees, A
= 135 degrees, B = 135 degrees. In the embodiment shown in FIG. 6, the width of the active region is 0.7 μm between parallel linear regions, and the space between the active regions is also 0.7 μm.
It was set as μm. The widest part of the word line is also 0.7μm
It is. If the center of the bit line contact hole is the 0 point, and the space between the word lines facing each other around this point is the minimum processing dimension of 0.5 μm, then the gate length is 0.
．． In the case of 7 μm, the channel region becomes hexagonal. Furthermore, when the gate length is less than 0.6 μm, the channel region becomes pentagonal.

Note that the above discussion concerns the layout of the memory cell, and the pattern actually transferred onto the substrate has rounded corners due to the limitations of the known photolithography method, and has the shape shown in Figure 6. Needless to say, it will be different.

Second Embodiment In the memory array shown in FIG. 1, the shape of the active region is 1.
It has an 80 degree point symmetry. However, a memory array with exactly the same word line pitch and bit line pitch can also be realized using different active areas. FIG. 7 shows an example of this.

The active region 1.1 in FIG. 7 is located along the center line of the bit line contact hole 1.3 and at the hood $1.
It has mirror symmetry with respect to a line parallel to 2. In this arrangement, if the center of the bit line contact hole in one active area is set as the origin, the centers of the bit line contact holes in the four active areas closest to it are (-W
p, -Dp), (-Wp.

-Dp), (Wp*Dp), (Wp*
D p ), and each shape is obtained by translating the central active region. A memory array can be constructed by repeatedly arranging these as one unit.

Even with the above active region shape, it is possible to form a storage capacitor portion after forming the bit line 1.4, which is a feature of the present invention, while realizing a channel region tilted with respect to the word line. As long as the same layout rules are used, a memory cell with the same word line pitch and bit line pitch as the memory cell shown in FIG. 1 can be obtained, and of course the size of the storage capacitance section remains the same. Further, if the active region is arranged as shown in FIG. 7, it becomes a two-intersection type memory cell, similar to that shown in FIG. The method for creating a memory cell is also the same as shown in Figure 1.
This is exactly the same as the example.

Third Embodiment In order to prevent the SN ratio from decreasing due to bit line noise, 64
After the bit, the two-intersection method is adopted. In this method, the word line always passes under the two bare bit lines, so coupling noise is generated in the same phase on the two bit lines and cancels out during sensing. In the one-intersection method, variations in the parasitic capacitance of bare bit lines directly become noise, so there is a drawback that it is susceptible to noise.

FIG. 8 shows a part of a one-intersection type memory array using the semiconductor memory device of the present invention. Note that the plate electrode is excluded here for the sake of simplicity.

However, as in the previous embodiments, the plate electrode is a conductive layer that simply covers the memory array, and has a structure that does not have holes, at least on the memory array. In this embodiment, bit line contact hole 1
．． An example of an active area having a point symmetry of 180 degrees with respect to the center of 5 is shown.

A one-intersection memory array has one active area 1
．． Considering the coordinates with the center of the bit line contact hole 1.5 of No. 1 as the origin, the centers of the bit line contact holes of the four active regions closest to it are set as (-W p
t −D p ), (−Wp, O), (Wp.

0), (Wp, Dp). Here, Wp and -DP are the distances between the bit line contact holes, respectively, Wp is a component parallel to the bit line 1.4, and Dp is a component parallel to the word line 1.2. If we focus on one bit line, we can see that all the word lines that intersect with it have storage capacitances, which is different from the two-intersection method in which storage capacitances are alternately attached to bare bit lines.

The method for manufacturing the memory cell of the above embodiment essentially consists of the first
However, in the memory cells shown in FIGS. 1 and 7, the storage capacitor contact holes 1, 5 are the same as those shown in the figures, but the storage capacitor contact holes 1, 5 are connected to two word lines 1.2 and two bit lines 1.2. 4
, the storage capacitor lower electrode could be processed above the word line and bit line. In contrast,
In the memory cell shown in FIG. 8, since the pitch of the bit lines is increased, no bit line is placed in one side of the storage capacitor contact hole 1.5. Therefore, when compared on the actual memory level difference, Although there is some difference in the shape of the storage capacitor lower electrode 1.6 between the two, this does not pose a major problem during processing.

Fourth Embodiment In the fourth embodiment shown in FIG. 9, a one-intersection type memory array is realized using active regions having mirror symmetry in shape. Focusing on one active region 1.1 and considering a coordinate system with the center of its bit line contact hole 1.3 as the origin, the centers of the bit line contact holes of the four active regions closest to it are as follows.
Re, (wp.

O), (-Wρ+ -D p), (Wpy O), (W
p+Dp), and its orientation is the central active area rotated or inverted by 180 degrees.

Even by using this active region, a memory cell having exactly the same word line pitch and bit line pitch as shown in FIG. 8 can be realized.

Fifth Embodiment In the memory cell of the present invention, the word line and the bit line intersect and the storage capacitor section is formed thereon, so that the lower electrode of the storage capacitor must be processed on a high step. For example, the word line thickness is 200 nm, the bit line thickness is 200 nm.
m, assuming that the thickness of the oxide film for insulating each line in a self-aligned manner is 250nm, there is a distance of 900nm from the substrate surface where the word line and bit line intersect.
A step of m is created. When processing the storage capacitor lower electrode, it is necessary to remove the electrode layer (polycrystalline silicon) attached to the side wall of the 900 nm step.
In a memory cell, the area surrounded by two word lines and two bit lines becomes like a deep trench, so the polycrystalline silicon in this area is completely removed and the lower electrodes of each storage capacitor are separated. It's not easy to do. For this reason, the first
The layout of the storage capacitor lower electrode 1.6 as shown in the figure has the above-mentioned problem, and in the worst case, the lower electrode 1.6 will be connected.

A layout for improving the above drawbacks is shown in FIG. 1θ. In this memory cell layout, the only difference is the arrangement of the storage capacitor lower electrode 1.6 from that shown in FIG. 1, and the other button shapes and arrangements are exactly the same.

In the above embodiment, the arrangement of the lower electrodes 1.6 in each column is shifted in opposite directions, and two word lines 1.6 are formed on the element isolation oxide film.
The deep trench formed by the bit lines 2 and 1.4 is filled with the lower electrode.

As a result, at least in the memory array, processing of the lower electrode on the step formed at the intersection of the word line and the bit line is eliminated, and the problem of the lower electrode short circuit is eliminated. By the way, in the periphery of the memory array, it is essential to process the lower electrode on this high level difference, and if this process is not completed, polycrystalline silicon will remain along the level difference in the periphery of the array. However, in the peripheral areas,
Since deep trenches are not formed, removal of polycrystalline silicon is easier than in a memory array. Further, even if polycrystalline silicon remains in the periphery, as long as it is separated from the lower electrode in the memory array, it will not pose a problem in memory operation.

〔Effect of the invention〕

As described above, in the semiconductor memory device according to the present invention, in which the minimum unit is one switch transistor and one charge storage capacitor, the channel region and source/drain region of the switch transistor are formed. The main part of the active region is arranged so that it is not parallel to either the main part of the word line forming the switching transistor or the main part of the bit line for writing and reading information. This allows 16 Mbit level DRA
The minute memory cells required by M can be easily manufactured using conventional photolithography and dry etching methods. Moreover, compared to STCs with conventional structures, the storage capacity is not affected by the processing of the plate electrodes.
The storage capacitor sections can be arranged most densely. As a result, sufficient capacity can be ensured even with a small cell area. This capacitance value has a sufficient margin even if soft errors caused by α rays, circuit noise, etc. are taken into consideration.

A second feature of the present invention is that since the storage capacitor section is formed on the bit line, the storage capacitor and the plate electrode also serve as a shield line.

Therefore, the line-to-line capacitance of the bit lines is reduced, and memory array noise is significantly reduced. Another major feature is that the number of masks required to realize this structure is almost the same as that of conventional structures.

By using the present invention as described above, it becomes possible to realize a memory cell that satisfies the area and capacitance values required for DRAMs at the megabit level to several tens of megabits.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a first embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a plan view showing a first example of a conventional STC cell, and FIG. 3 is a plan view showing a second example of a conventional STC cell. 4 is a cross-sectional view of the STC cell shown in FIG. 2, FIG. 5 is a cross-sectional view of the memory cell shown in the first embodiment, and FIG. 6 shows the shape of the active region and the channel region. FIG. 7 is a plan view of a memory cell showing a second embodiment of the present invention, and FIG. 8 is a plan view of a memory cell showing a third embodiment of the present invention. This figure is a plan view of a memory cell showing a fourth embodiment of the invention, and FIG. 10 is a plan view of a memory cell showing a fifth embodiment of the invention. 1.1... Active area 1.2.5.4... Word line 1.3... Bit line contact hole 1.4.5.7
...Bit line 1.5...Storage capacitor contact hole 1.6.5.
9...Charge storage capacitor lower electrode representative patent attorney
Junnosuke NakamuraFigure Figure Figure T, b Figure Figure

Claims (1)

[Claims] 1. In a semiconductor memory device whose minimum unit is one switching transistor and one charge storage capacitor, an active region in which a channel region and a source/drain region of the switching transistor are formed; The main part is arranged so as not to be parallel to either the main part of the word line forming the switching transistor or the main part of the bit line for writing and reading information. A semiconductor storage device. 2. The active region is composed of a region that is tilted and a region that is perpendicular to the word line, and at the same time, a region that is parallel to the tilted region with respect to the bit line, and , the channel region of the transistor formed by overlapping the word line and the active region is hexagonal, and the internal angles of the corner vertices are 90 degrees and 90 degrees, respectively.
The semiconductor memory device according to claim 1, wherein the angle is 135 degrees, 135 degrees, 45 degrees, and 225 degrees. 3. The channel region of the transistor where the word line and the active region overlap is pentagonal, and the internal angles of each vertex are 90 degrees, 135 degrees, 135 degrees, 45 degrees, and 1, respectively.
The semiconductor memory device according to claim 2, wherein the angle is 35 degrees. 4. The active region has an area of 180 mm with respect to the center of the contact hole opened in order for the beat line to contact one of the diffusion layers of the switch transistor.
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a shape that is symmetrical in degrees. 5. Claim 1, wherein the active area is mirror symmetrical with respect to a line passing through the center of the beat line contact hole and parallel to the word line.
The semiconductor storage device described in . 6. The active region is in contact with the lower electrode of the charge storage capacitor at one diffusion layer, and the diffusion layer is always arranged in a region surrounded by two word lines and two bit lines. A semiconductor memory device according to claim 1. 7. The active region, which has a point-symmetrical shape, has its origin at the center of the bit line contact hole, and has a distance between the bit line contact holes with a component parallel to the word line Dp and a component parallel to the bit line. When Wp is
The centers of the bit line contact holes on the four active regions closest to the above active region are (-Wp, D
p), (-Wp, -Dp), (Wp, Dp), (Wp,
-Dp), each of which is a two-intersection type memory array in which the active area at the center is inverted and translated in parallel. Device. 8. The mirror-symmetrical active area has the centers of the bit line contact holes on the four active areas closest to the active area, respectively (-Wp, Dp
), (-Wp, -Dp), (Wp, Dp), (Wp, -
6. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is a two-intersection type memory array, each of which has an arrangement in which the active region at the center is moved in parallel. 9. The active area having the point-symmetrical shape has its origin at the center of the bit line contact hole in the active area, and the centers of the bit line contact holes on the four active areas closest to the active area are respectively ( −
Wp, O), (-Wp, -Dp), (Wp, O), (W
5. The semiconductor memory device according to claim 4, wherein each of the semiconductor memory arrays is a one-intersection type memory array arranged in such a way that the active region at the center is moved in parallel. 10. The mirror-symmetric active area has the center of the bit line contact hole in the active area as its origin, and the centers of the bit line contact holes on the four active areas closest to the active area are as follows:
respectively (-Wp, O), (-Wp, -Dp), (Wp, O
), (Wp, Dp), each of which is a one-intersection type memory array in which the active area at the center is rotated by 180 degrees and further translated in parallel. The semiconductor memory device described in Section 5. 11. The lower electrode of the charge storage section in contact with one of the diffusion layers is arranged so as to extend over the element isolation oxide film that is not covered by either the word line or the bit line. A semiconductor memory device according to claim 6. 12. The charge storage capacitor has at least one plate electrode on the memory array that does not come into contact with the lower and upper conductive layers of the plate electrode, and also has holes necessary for electrical connection. The semiconductor memory device according to claim 1, characterized in that there is no such.