JPH02226363A - Address generation circuit - Google Patents

Abstract

PURPOSE:To reduce circuit scale in an address generation circuit and to reduce the size of a chip when an integrated circuit is formed by providing an adder and subtracter in a cell by one bit of address and generating the read address and write address of a memory cell array from one pointer. CONSTITUTION:At the time of up-counting operation, the output of an adder 74 is inputted through a switch 76 to a flip-flop (FF) 73 and the output of the FF 73 is inputted to the adder 74. In this case, the output of the FF 73 and the output of a subtracter 75 are alternatively outputted by a switch 78. At the time of down-counting operation, the output of the subtracter 75 is inputted through the switch 76 to the FF 73 and the output of the FF 73 is inputted to the subtracter 75. At such a time, the output of the adder is supplied to switch 77 to a switch 78 and the output of the FF 73 and the output of the adder 74 are outputted by the switch 78. Thus, the read address and write address are alternatively outputted by one pointer and the circuit scale is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is directed to a digital signal processing circuit configured with an integrated circuit (IC, LSI, VLSI, etc.).
The present invention relates to an address generation circuit provided in a semiconductor memory such as a random access memory (random access memory).

(Prior Art) Generally, in digital signal processing, sum-of-products operations are often performed, and an example of such a circuit is shown in FIG.

FIG. 2 is a functional block diagram of the product-sum calculation circuit. In this circuit, for example, input data Di is stored in N shift registers 1-1 to 1-H at every fixed sampling period, and each shift register output and coefficient α are stored at each sampling period.
1 to αN are multiplied by multipliers 2-1 to 2-N, and the multiplication results are added by adder 3 to output operation result data DO.

FIG. 3 shows an example of a configuration in which this type of product-sum operation circuit is configured using a RAM.

FIG. 3 is a schematic configuration diagram of a conventional RAM.

This RAM is the shift register 1-1 to 1-N in FIG.
a data storage memory cell array 10 having the functions of
The memory cell array 10 includes an address generation circuit 11 that generates an address for the memory cell array 10. The address generation circuit 11 is composed of a first pointer 12 that generates a read address Aρ, a second pointer 13 that generates a write address Aw, and a selector 14 that selects an address Aρ or Aw. An output is connected to the memory cell array 10. An arithmetic circuit 20 having multiplication and addition functions is connected to this RAM.

In the above configuration, in order to perform the product-sum operation, the read data AI output from the first pointer 12 is sent to the selector 1.
4 to the memory cell array 10, and the (N1)th stored data DA is read from the memory cell array 10 and inputted to the arithmetic circuit 20. Further, this data DA is written to the 100Nth address of the memory cell array using the write data Aw output from the second pointer 13. In such an operation, the read addresses A, l! are read from the first pointer 12 in the order of N, N-1, N2, . . . , 1! is output, and the second
From the pointer 13, N+1°N, N-1, N-2, .
. . , write data Aw is output in the order of 2. In order to generate this address at high speed and with easy control, the conventional address generation circuit 11 is provided with two independent pointers 12 and 13.

FIG. 4 is a diagram showing an example of the configuration of the pointer in FIG. 3.

This pointer is composed of an up/down counter and includes a control circuit 30 that operates on a program ROM or the like, and a clock signal CK output from the control circuit 30,
The K-bit cells 31-1 to 31-K are controlled by the load signal LD, up/down switching signal U/D, and the like. Preset data PD is stored in cells 31-1 to 31-K.
I to PDK are respectively input, and the cells 31-1 to 31-3
Addresses QAI to QAK are output from 1-K, respectively.

FIG. 5 is a circuit diagram showing an example of the configuration of a cell for one bit in FIG. 4.

This cell includes a switch 40 that is switched by a load signal LD, switches 41 and 42 that are switched by an up/down switching signal U/D, and an inverter 43 for signal inversion.
, 44, an adder 45 that adds the carry signal (carry signal) CI of the previous stage and the output from the switch 42 and outputs a sum signal and a carry signal CO to the next stage, and a flip-flop function, hereinafter referred to as FF. ) 46.

In this cell, in the case of up-count operation, the up/down switching signal U/D is set to a high level (hereinafter referred to as I
I HII), the switch 40,
41 and 42 are switched as shown by the solid line. Then,
The address QA output from the output terminal Q of FF46 is
The signal is output to the outside, and is also fed back to the input terminal of the FF 46 via the switch 42, adder 45, and switch 41. Therefore, the address (QA+1) is input to the input terminal of the FF 46 in accordance with the input of the clock signal CK, so that the up-count operation continues.

In the case of down-count operation, by setting the cup/down switching signal U/D to a low level (hereinafter referred to as LI+), the switches 41 and 42 are switched as shown by broken lines. Then, the address QA output from the output terminal Q of the FF 46 is transmitted to the FF 4 through the inverter 44, the switch 42, the adder 45, the inverter 43, and the switch 40.
It is fed back to the input terminal of 6. Therefore, clock signal C
Since the address (QA-1) is input to the input terminal of the FF 46 in accordance with the input of K, the down-count operation continues.

(Problems to be Solved by the Invention) However, the above address generation port #111 requires first and second pointers 12.13 and a selector 14 that selects the outputs of these two pointers 12.13. Therefore, if a digital signal processing circuit or the like is constructed using the address generation circuit 11, memory cell array 10, etc., there is a problem that the circuit scale becomes large and is not suitable for integrated circuit implementation.

The present invention provides an address generation circuit that solves the problems of the prior art, such as the increase in circuit scale and the resulting incompatibility with integrated circuits.

(Means for Solving the Problems) In order to solve the above problems, the present invention includes an address storage pointer composed of a plurality of bits of up/down counters, and generates read addresses and write addresses for a memory cell array. In the address generation circuit, at least a FF receives input of cells corresponding to 1 bit of the address of the up/down counter in synchronization with a clock signal, and a sum signal and a carry by adding the output of the FF and a first input signal. an adder that generates a signal, a subtracter that subtracts the output of the FF and a second input signal to generate a difference signal and a borrow signal, and selects the sum signal and the difference signal and inputs the FF. a first switch that selects the sum signal and the difference signal in a phase opposite to that of the first switch; and an output of the second switch and the F
The third switch selects the output of F and outputs the signal as an output signal.

(Function) According to the present invention, since the address generation circuit is configured as described above, during up-count operation, the output of the adder is input to the FF via the first switch, and the output of the FF is Input to adder.

At this time, the output of the subtracter is supplied to the third switch via the second switch, and the third switch supplies the FF
The output of the subtracter and the output of the subtracter are output alternately. During a down-count operation, the output of the subtracter is input to the FF via the first switch, and the output of the FF is input to the subtracter. At this time, the output of the adder is supplied to the third switch via the second switch, and the third switch outputs the output of the FF and the output of the adder. As a result, one pointer outputs a read address and a write address alternately. Therefore, the above problem can be solved.

(Embodiment) FIGS. 1(a) and 1(b) are configuration diagrams of an address generation circuit showing an embodiment of the present invention, in which FIG. 1(a) is an overall configuration diagram, and FIG. FIG. 4 is a circuit diagram of a cell for one bit in FIG.

As shown in FIG. 1(a), this address generation circuit 50
consists of a one-bit pointer 51 that generates a read address Aρ and a write address Aw for the memory cell array 10 for storing data. This bit pointer 51 is composed of an up/down counter, and is equipped with a control circuit 52 that operates on a program ROM or the like, and a clock signal C output from the control circuit 52.
K-bit cells 53-1 to 53K are controlled by K, load signal LD, read address/write address switching signal R/W, and up/down switching signal U/D. Cells 53-1 to 53-K contain preset data PDI.
The PDK inputs that cell 53-1 to 53.
-K outputs addresses QAI to QAK, that is, read address A, llman or write address Aw.

Each cell 53-1 to 53-K (=53> is shown in FIG. 1(b)
As shown in the figure, a terminal 60 for inputting preset data PD
, a terminal for inputting the clock signal CK, a terminal 62 for inputting the carry signal (carry signal) CIP from the previous stage, a terminal 6 for inputting the borrow signal (carry down signal) CIN from the previous stage
3. Terminal 64 for outputting address QA, terminal 65 for outputting borrow signal CON to the next stage, carry signal c to the next stage
Terminal 66 for outputting OP, terminal 67 for inputting load signal LD, terminal 68 for inputting read/write switching signal R/W
, and input terminal 69 for up/down switching signal U/D.
have. Each terminal 67, 68, 69 has a signal LD
, R/W, and U/D, respectively, are connected to inverters 70, 71, and 72 that generate reverse phase signals LD, R/W, and U/D.

This cell 53 has an FF 73 that takes in the signal on the input terminal at the rising edge of the clock signal CK input to the clock terminal C and outputs it from the output terminal Q, and a carry signal CIP on the carry terminal CI. Add the signal on terminal A and output the sum signal and carry signal to terminals S and CO.
and a subtracter 7 that adds the borrow signal CIN on the borrow terminal CI and the signal on the input terminal A and outputs a difference signal and a borrow signal from the output terminals S and CO.
5. The input terminal of the FF 73 is connected to the terminal 60 via the switch 76, and also connected to the terminal 60 via the switch 76.
6.77 to the respective output terminals S and S of the adder 74 and the subtracter 75, respectively. Each output terminal S, S of the adder 74 and subtracter 75 is connected to a switch 78.7.
9 to a terminal 64, and the terminal 64 is connected to the output terminal Q of the FF 73 via a switch 79, and to the input terminals A and A of an adder 74 and a subtracter 75, respectively. . The output terminals C○ and CO of the adder 74 and the subtracter 75 are connected to terminals 66 and 65, respectively.

The switches 76, 77, 78, and 79 have a signal switching function, and are, for example, N-channel field effect transistors (hereinafter referred to as FETs) 76a, 77a, 78b, 79a and P-channel FETs 76b, 77b, 78b, 79b.
They are each composed of

In the above configuration, the operation shown in FIG. 1(b) will be explained first.

When initializing the cell 53, the load signal LD is set to, for example, II HII. Then, the FET in switch 76
76a is turned on, and the preset data PD on the terminal 60 is input to the input terminal of FF7B. Here, FF73
When the clock signal CK is input to the clock terminal C of the F
F73 activates the precertifier I at the rising edge of the clock signal CK.
It takes in data PD and outputs it from output terminal Q.

In the case of up-count operation, the load signal LD is
II, and set the up/down switching signal U/D to, for example, "Hll. Then, the FE in the switch 76
When T76a turns off, FET76b turns on, and when FET77a in switch 77 turns on, FE
T77b turns off. The adder 74 adds the output from the output terminal Q of the FF 73 and the carry signal CIP from the lower bit cell, and outputs the sum signal and the carry signal from the output terminals S and CO. The sum signal is FET77a, 76b
It is input to the input terminal of FF73 via.

In this state, the clock signal C to the clock terminal C of FF73
When K is input, the FF 73 takes in the sum signal at the rising edge of the clock signal CK and outputs it from the output terminal Q. Thereafter, every time the clock signal CK is inputted sequentially, the alarm count operation is continued using the carry signal CIP from the lower bit cell and the output of FF7B.

In case of down count operation, up/down switching signal U
/D becomes 11 L II, FETs 77b and 78b in switches 77 and 78 are turned on, and FFs 77a and 78b are turned on.
78b turns off. The subtracter 75 outputs the output of the FF 73 and
Find the difference from the borrow signal CIN from the lower bit cell,
The difference signal and the borrow signal to the upper bit cell are output to the terminal S.
, output from CO. The difference signal is FET77b, 76b
It is input to the input terminal of FF73 via. In this state, when clock signal CK is input to lower F73, FF7
3 takes in the difference signal and outputs it from the output terminal Q.

Thereafter, each time the clock signal CK is inputted sequentially, the down-count operation is continued by the borrow signal CIN from the lower bit cell and the output of the FF 73.

Next, the overall operation of the address generation circuit 50 of FIG. 1(a) will be explained with reference to FIG. 6. In addition, the 6th
The figure is a timing chart of FIG. 1.

In FIG. 1(a), K-bit cells 531 to 53-
Preseller 1 to data PD1 to PDN loaded into K are, for example, N, and for the sake of simplicity, the outputs of each FF 73 and the output of each adder 74 in cells 53-1 to 53- of each stage are , and the output of each subtractor 75 are also represented by N.

First, a cell operation when a read address Aρ and a write address Aw are outputted from the pointer 51 constituting the address generation circuit 50 will be described.

Assuming that N is output from the output terminal Q of FF7B in each cell 53-1 to 53-, the adder 74 outputs (N+1>, and the subtracter 75 outputs (N-1>). Output.

When using pointer 51 as a down counter,
The load signal LD becomes II L II, the up/down switching signal U/D becomes PA L''', and FET76a 77a
, 78a are off, FET 76b.

77b and 78b are turned on. The output sum signal of each adder 74 is sent to the output selection switch 7 via a FET 78b.
The signal is input to the middle FET 79b side. This switch 79
When FETs 79a and 79b inside are switched at the midpoint of the clock signal CK by the read/write switching signal R/W, the terminal 64 outputs the output of FF7B for the read address Ag in the first half of the clock signal CK, and the write address A in the second half.
The output of the adder 74 for g is obtained. That is, first read from address N, write to address (N+ 1 >
-1>, read from address N, write to address N, and thereafter read addresses A, 11 and write address Aw are obtained alternately. Therefore, for example, in a product-sum operation as shown in FIG. 2, the memory cell array 10 is
Addresses can be easily generated when used as 1-N.

The above is an explanation when the pointer 51 is operated as a down counter, but when it is operated as an up counter, the output of the subtracter 75 is outputted to the terminal 64 via FETs 78b and 79b, which is almost the same as a down counter. The operation is as follows.

This embodiment has the following advantages.

Since the address generation pointer 51 is provided with an adder 74 and a subtracter 75, the read addresses A, 11 and the write address Aw for the memory cell array 10 can be alternately output from the pointer 51.

Therefore, instead of conventionally requiring two pointers 12 and 13, the address generation circuit 50 can be configured with one pointer 51, making it possible to eliminate a large amount of circuitry, and reducing the chip size when integrated circuits are implemented. can be reduced.

Note that the present invention is not limited to the illustrated embodiment; for example, the first embodiment
Various modifications are possible, such as configuring the switches 76 to 7 in the figure with other switching transistors such as analog switches, or using the present invention for address generation in other digital signal processing circuits.

(Effects of the Invention) As explained in detail above, according to the present invention, since an adder and a subtracter are provided in a cell for one address bit, a read address and a write address of a memory cell array can be accessed from one pointer. can be generated, thereby reducing the circuit scale of the address generation circuit, and can be expected to reduce the chip size when integrated circuits are integrated.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are block diagrams of an address generation circuit showing an embodiment of the present invention, FIG. 2 is a block diagram of a general product-sum operation circuit, and FIG. 3 is a block diagram of a conventional RAM. , FIG. 4 is a block diagram of the pointer in FIG. 3, FIG. 5 is a block diagram of the cell in FIG. 4, and FIG. 6 is a timing chart of FIG. 10... Memory cell array, 50...
Address generation circuit, 51... Pointer, 52.
...Control circuit, 53-1 to 53-K...
Cell, 73...FF, 74...Adder, 75...Subtractor, 76-79...Switch, A, fl...・Write address, Aw・
...Read address, CK...Clock signal, CIP. COP... Carry signal, CIN, CON...
...borrow signal, R/W...read/write switching signal, QA...address, U/D...
...Up/down switching signal.

Claims (1)

[Scope of Claims] In an address generation circuit that includes an address storage pointer constituted by a multi-bit up/down counter and generates a read address and a write address for a memory cell array, The cell includes: a flip-flop that receives input in synchronization with a clock signal; an adder that adds the output of the flip-flop and a first input signal to generate a sum signal and a carry signal; and an output of the flip-flop. a subtracter that subtracts a second input signal to generate a difference signal and a borrow signal; a first switch that selects the sum signal and the difference signal to input the flip-flop; a second switch that selects the difference signal with a phase opposite to that of the first switch; and a third switch that selects the output of the second switch and the output of the flip-flop as an output signal. , an address generation circuit characterized by comprising: