JPH02226294A - Display controller - Google Patents

Abstract

PURPOSE:To prevent a liquid crystal display plate from deteriorating owing to a program miss of software by providing the display controller with an FF for display on/off control which receives the same inputs as the 1st and final registers in a register group for timing setting. CONSTITUTION:The inputs WR1 and WRn to the 1st and final registers R1 and Rn in the register group registers R1 - Rn for timing setting are branched and inputted to the FF. Namely, a synchronizing signal generating circuit 4 outputs synchronizing signals S2 and S3, which are set with the data of the registers R1 - Rn, to drivers 7 and 8 to drive the liquid crystal display plate 6, and the system of the controller 1 is reset to stop the signals S2 and S3. Then the data in the registers R1 - Rn are rewritten by a CPU 3 through a system bus S1 so as to set the synchronizing signals, and the FF outputs an 'L' signal with the 1st write data WR1; and the output of an AND gate G1 is also held at 'L' to turn off the display plate 6 and then the FF outputs an 'H' signal to turn on the display plate 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a display control device having a function of preventing deterioration of a liquid crystal display panel of a liquid crystal display device.

[Conventional technology]

FIG. 4 is a block diagram showing the configuration of a conventional display control device. (1) is a display control device, (2) is a liquid crystal display device,
(3) indicates a central processing unit (hereinafter referred to as CPU).

(4) is a synchronization signal generation circuit, RO is a register that controls display on/off, and display control device (υ includes a synchronization signal generation circuit (4) and a register cat. (5) is a synchronization signal Generation internal circuit, R1, R2...h is a timing setting register, Rt is a timing reset register, and the synchronization signal generation circuit (4) is connected to the synchronization signal generation internal circuit (5) and registers R1, R2,... - Consists of Rn and Rt. (6) is a liquid crystal display board, (7) is a segment driver, (3) is a common driver, (
9) is an input terminal for forcibly controlling the on/off of the display, and the liquid crystal display device (2) connects the liquid crystal display board (6), drivers (7) and (8), and the input terminal (9). Contains. S1 system has, WRI, WR2,..., W
Rn, WRt, WR.

is write data, and the signal coming from the CPU (3) through the system bus S1 is written within the display control device (1).
Cheetah WRI, WR2, -, WRn, WRt, W
Ro and site registers R1, R2, ..., Rn,
Enter Rt and Ro. S2゜S3 is a synchronization signal, which is output from the synchronization signal generation circuit (4) and generates the synchronization signal S2.
is input to the segment driver (7), and the synchronization signal S3 is input to the common driver (8). & is a signal (hereinafter DISPOFF) that controls the on/off of the display on the liquid crystal display board (5).
signal), which is output from the register RO and enters the input terminal (9).

Next, the operation will be explained. The synchronization signal generation circuit (4) receives signals WR1, WR2, --, WRn, WRt input from the CPU (3) through the system bus S1.
The synchronization signals 32 and S3 are generated by the liquid crystal display device (
2) respectively to the drivers (7) and (8). Drivers (7) and (8) drive the liquid crystal display panel (6) according to synchronization signals S2 and S3. The liquid crystal display board (6) displays 1) ISP OFF according to the data written in register Ro.
, is displayed when DISPOFF=ゞL'/, and is not displayed when DISPOFF=ゞL'/.

Since the synchronization signal generation circuit (4) and the register Ro independently control the liquid crystal display device (2), the CPU (3) gives commands to each when resetting the synchronization timing. Data for timing setting is given to the synchronization signal generation circuit (4), and on the other hand, the synchronization signals S2 and S3, which were synchronized due to the change in timing, generate out-of-synchronization pulses and the liquid crystal display board (6). CPU (3) is set to DISPOF in register RO to prevent deterioration.
Provide data such that F=+L'/. A flowchart of the software that executes this is shown in FIG. In the state of "step αQ", a synchronized display is performed, the register RO is H'/, and the DISI T signal S4 is m
= 'H'/. In "step αη", the CPU (3
) rewrites register RO to L with write data WRo, and DISPOFF signal S4 becomes DISPOFF-KL.
is input into the drivers (7) and (8), and the display is turned off. Next, the CPU (3) controls the synchronization signal generation circuit (4) and starts resetting the timing. "Step"
The system will now be reset. For timing reset of "step 0", CPU (3) uses register Rt.
Rewrite and stop the synchronization signal. In "step (7)", CPU (3) writes write data WRs, WR2,...
・, registers R1, R2,..., R through WRn
Rewrite n and set the timing of the synchronization signal. In "step 01)", the register Rt is rewritten and a synchronization signal is generated. Finally, CPU (3) rewrites register RO to <'H〃 (step @) and IJISPCJ
The FF signal S4 is a driver (
7) and (8) are input, and the liquid crystal display board (6) recesses the display (step (2)).

[Problem to be solved by the invention]

In conventional display control devices, there is a risk that the liquid crystal display panel may deteriorate due to errors in the flow of software programming.

The present invention was made in order to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a display control device that reduces the burden on control software.

[Means to solve the problem]

The display control device according to the present invention includes a flip-flop that inputs the same input as the first and last register in the timing setting register group and controls the on/off of the display.

Another display control device according to the present invention includes a timing reset register that can control display on/off.

[For use]

According to the present invention, when the central processing unit executes processing that disturbs the synchronization signal, the signal from the central processing unit is branched and converted into a control signal, thereby automatically controlling the on/off of the liquid crystal display panel.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram showing an embodiment according to the present invention.

In the figures, the same or equivalent parts as in FIG. 4 are given the same reference numerals. FF is R-S flip-flop, G1 is A
This is an ND gate, and the display control device (1) includes a synchronizing signal generating circuit (4), a register Ro, a flip-flop voltage, and a gate G1. Flip-flop FF is CPU
Write data from (3) ■ Light is set input, write data WRn is reset input, and negative Q is output.

1 to the gate inputs the register Ro and the negative output page of the flip-flop and outputs the DISPOFF signal S4.

Next, the operation will be explained. FIG. 2 shows a software flowchart for resetting the synchronization timing. The state of "step αq" is a synchronized display line t) t'
L ” C Ot) DISPOFF signal S4 C DIS
POFF=ゞH'/. That is, the outputs Q of the register RO and flip-flop F are both H, and the gate G
The output of 1 is 蒀′. Furthermore, register groups R1, R2,
..., synchronization signal S2 set by the data of Rn
・S3 is from the synchronization signal generation circuit (4) to the driver (7)・
(3), and the liquid crystal display panel (6) is driven. In "step αυ", the system of the display control device (1) is reset. The synchronization signals S2 and S3 are stopped by the timing reset in "step (2)". In "step α4", the timing of the synchronization signal is set. C.P.
Register 8 from U (3) through system bus S1
The data of \R1, R2, . . . , Rn is rewritten, and the first rider data WRI becomes a flip-flop pressure set input and outputs an inverted output Q-<'L. Since the register fat remains <'H'/, AND gate G
The output of 1 becomes a tag, and ■Shukento signal & is DISPOF
F: As +L'/, the driver (7) in the liquid crystal display device (2) is input and the liquid crystal display board (6) is turned off. At the same time, the write data 'wRI begins to rewrite the register group, and continues. Write data WR2, WR3.

..., WRn is input and registers * R2, R3
, . . ., Rn is rewritten and the timing reset is completed. The last write data WRn is a flip-flop FF
becomes the reset input and outputs negative Q=ゞHe, AND
The output of the gate G1 becomes ゞH〃, and the DISPOFF signal S4 is inputted to the driver (7) as 1 = ゞH〃, and the liquid crystal display board (6) is turned on.
The timing reset is canceled when the signal is pressed, a synchronization signal is generated, and the liquid crystal display board (6) starts displaying (step <1).
.

In this way, in this embodiment, the timing setting register group R
1, R2, . . . , the first and last registers Rt in Rn.

By branching the inputs WRI and WRn to Rn and inputting the flip-flop pressure, the conventional flowchart shown in Fig. 5 can be simplified as shown in Fig. 2. Deterioration of the display board can be prevented.

Other embodiments of the present invention will be described below with reference to the drawings. Third
The figure is a configuration diagram showing another embodiment according to the present invention. In the figures, the same or equivalent parts as in Figure 1 are given the same reference numerals. The display control device/equipment (1) includes a synchronization signal generation circuit (
4), a register Ro, and an AND gate Gl.

The timing reset register Rt in the synchronization signal generation circuit (4) is active L'', and the AND gate G
1 uses register Ro and register Rt as input and DISPO
Outputs FF signal S4.

Next, the operation will be explained. The software flowchart for resetting the synchronization timing is shown in the above embodiment, ie, FIG. 2. "The state of step Cl0J is a synchronized display, and the mFF signal S4 is r f
u11=“H”. In other words, the data in registers kO and Rt are both HI (AND game).
=%H'/. Furthermore, register group R1, R
2, . . . The synchronization signal S2 is set by the data of 7.
S3 connects the synchronization signal generation circuit (4) to the driver (7) (
8), and the liquid crystal display panel (6) is driven.

In "step 0υ", the system of the display control device (1) is reset.

In "step (6)", the write data wRt-row is sent from the CPU (3), and the contents of the register Rt are ゞH'/
1 can be changed from ゞL〃. Register Rt resets the timing and stops the synchronization signal. AND at the same time
In order to output ゃL〃 to gate G1, DISPOFF signal S4 becomes DISPOFF-゜L'' and becomes dry (7
)・(In August, turn off the liquid crystal display board (6). At "Step α-men", write data VVR from CPU (3)
I, WR2,−, W'Rn is register group Kl,
Rewrite R2, . . . , Rn to set the timing of the synchronization signal. In step α4, when the write data WRt = <'H'/ from CPU (3) rewrites the register Rt from 'L' to 'H', the register Rt cancels the timing reset and returns to the newly set synchronization. Signal S2
・Generate S3. At the same time, AND gate G1 <'H
’, the DISPOFF signal S4 becomes DISP
OFF=H, and the liquid crystal display board (6) starts displaying ("Step 0").

As described above, in another embodiment of the present invention, the timing reset register Rt is used with the function of controlling the display on/off of the liquid crystal display board (6) in addition to the original timing reset function. The flowchart can be simplified as shown in FIG. 2, and deterioration of the liquid crystal display panel due to programming errors can be prevented by reducing software.

〔Effect of the invention〕

As described above, according to the present invention, the display off signal is output by the write signal from the central processing unit to the first register in the timing setting register group, and the display off signal is output by the write signal from the central processing unit to the last register in the register group. By providing a flip-flop that outputs a display-on signal, it is possible to prevent deterioration of the liquid crystal display board due to software programming errors.

Further, according to the present invention, by adding a display on/off control function to the timing reset register in addition to the original timing reset function, deterioration of the liquid crystal display board due to software programming errors can be prevented.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a flowchart of the present invention, Fig. 3 is a block diagram showing another embodiment of the present invention, and Fig. 4 is a conventional FIG. 5 is a flowchart of conventional processing. In the figure, (1) is a display control device, (2) liquid crystal display device, (3) is a central processing unit, (4) is a synchronization signal generation circuit, (5) is a synchronization signal generation internal circuit, and (6) is Liquid crystal display board, (7) is a segment driver, (8) is a common driver, (9) is an input terminal, R1, R2,..., Rn
is a timing setting register, ``A'' is a register that controls display on/off, Rt is a timing reset register, FF is an R-S flip-flop, G1 is an AND gate, Sl is a system bus, S2 and S3 are synchronization signals, S4
is the m child signal, WRI, WR2,...-, WRn, WR
o, WRt Harai) data. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) A register for controlling the display of a liquid crystal display device having an input terminal for forcibly controlling the on/off of the display, and a register for controlling the on/off of the display, and a segment driver and common register for the liquid crystal display device.
a synchronization signal generation circuit that generates a synchronization signal to the driver, and a display off signal outputted by a write signal from a central processing unit to a first register in a group of timing setting registers in the synchronization signal generation circuit; A display control device having a flip-flop that outputs a display-on signal in response to a write signal to the last register in a group, and a gate that receives as input the output of the flip-flop and the output of a register that controls on/off of the display. (2) A synchronization signal that controls the display of a liquid crystal display device having an input terminal for forcibly controlling display on/off and generates a synchronization signal to the segment driver and common driver in the liquid crystal display device. A display control device comprising: a generation circuit; a register that controls display on/off; and a gate that receives the register and a timing reset register in the synchronization signal generation circuit as inputs.