JPH02224043A - Cache memory - Google Patents

Abstract

PURPOSE:To improve the hit rate of a cache memory by enlarging a block size without deteriorating a throughput of a CPU and without adding a hardware of a buffer by using an address comparing circuit, a priority order control circuit and a dual port memory cell array. CONSTITUTION:EX-OR gates 71, 72 of an address comparing circuit 1 input CPU side block addresses 10, 11 and memory bus side block addresses 20, 21, respectively, and output a coincidence signal to an AND gate 73 when they coincide with each other. The AND gate 73 outputs a coincidence signal 51 only in the case when all the coincidence signals of the EX-OR gates 71, 72 are inputted. A priority order control circuit 2 outputs a word enable signal 52 to a decoder 4, unless the CPU side block addresses 10, 11 and the memory bus side block addresses 20, 21 coincide with each other. The decoder 4 activates a word line of a dual port memory cell array 3 only in the case when a word enable signal 52 is inputted. In such a way, the block size can be enlarged without allowing an access to wait.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory, and particularly to a cache memory that performs parallel processing of accesses on the CPU side and accesses on the memory bus side.

[Conventional technology]

Conventionally, cache memory using single-boat memory cells can only process access to one address, so it is necessary to simultaneously process accesses from the main memory to rewrite the cache memory due to cache misses and accesses from the CPU. Can not do it. Normally, when a CPU access misses the cache, the CPU retrieves the requested data from the main memory, rewrites the contents of the cache memory, and at the same time
Pass the data to u.

Here, as a method used to improve the cache hit rate, the unit of N replacement of cache memory due to cache miss (hereinafter referred to as block size) is
It may be about four times the bus width (16 bytes for a 32-bit CPU). At this time, if the block size is larger than the bus width between the cache memory and main memory, the bus width from the main memory to the cache memory may be Transfer (hereinafter referred to as block load) is performed in several steps. For example, if the block size is 16 bytes and the memory bus width is 32 bits, it will be transferred twice, but the cache memory is updated each time, so with conventional cache memory, the CPU is 6 Usually, the cache memory could not be accessed.
Main memory access cycles take longer than CPIJ access cycles, so the fact that the CPU cannot access during block loading means that the CPU
This reduces the throughput of U.

One cache memory solution to this problem is a buffer (between main memory and cache memory that holds data transferred by block load).
There is a method of providing a block load buffer (hereinafter referred to as a block load buffer), transferring blocks to the buffer T during block loading, and updating the cache memory when all blocks are completed. According to this method, the CPU can access the cache memory even during block loading, except when updating the cache memory at the end of block loading.

However, even with this method, when rewriting the cache memory from the buffer, CPU access is made to wait regardless of whether the address matches the CP tJ address, and the buffer also requires a large amount of hardware. For example, if the block size is 16 bytes, a buffer of ]28 bits is required.

[Problem to be solved by the invention]

The conventional cache memory mentioned above is a single baud I/
Since memory cells are used, there is a drawback that access to the cache memory from the CPU side and access for rewriting the cache memory from the main memory side cannot be processed simultaneously even if they are at different addresses. Furthermore, if the block size is increased in an attempt to improve the cache hit rate, the throughput of the CPU may drop or buffer hardware may be required.

An object of the present invention is to eliminate such problems, and when the address of the access on the CPLJ side and the address of the access on the memory bus side are different, it is possible to process both accesses without making them wait, and to save the block load buffer. An object of the present invention is to provide a cache memory in which the block size can be increased without having to wait for access even if the block size is not made to wait. A comparator circuit that compares the block address on the memory bus side with the block address on the memory bus side and outputs a match signal when they match, and a comparison circuit that outputs a match signal when the two addresses match. a priority control circuit that returns an enable signal to give priority and a busy signal to the other one indicating that the CP is in a waiting state;
first and second decoders connected to the block address on the U side and the block address on the memory bus side, respectively, and having the enable signal connected to one of them;
The CP tJ side data and the memory bus side data are connected to these first and second decoders, respectively.
- A dual-port memory cell array in which ports are connected via X and /O circuits, respectively.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, showing only parts related to the present invention.

Address comparison circuit 1 includes E) I-OR gate 7'', 72
, AND gate 73, and EX-OR gates 71 and 72 are CPU side block addresses j, 0 .
1.1 and memory bus side block address 20.21 respectively, and if they match, AND gate 73A,
Outputs a match signal. This AND gate 73 outputs a match signal 5] only when the match signals from all EX to OR gates 71 and 72 are input.

The priority control circuit 2 controls the CPU side block address /O
．． 11 and memory bus side block address 20.21
If they do not match, an 8-word enable signal 52 is output to the decoder 4. - If it is, output a busy signal 53 to the CPU. The decoder 4 deactivates the dual baud 1-only when the word enable signal 52 is input.
The word line of memory cell array 3 is activated. The decoder 5 inputs the memory bus side block address and activates the word line of the dual port memory cell array 3. I/
The O circuit 6 inputs and outputs CPU data to the dual port memory array 3 on the CPU side, and inputs data from the main memory on the memory bus side and writes it to the dual port I memory array 3.

Note that the block at 1 nos is an address indicating a block that is a unit of rewriting the contents of the cache memory due to a cache miss.

According to this embodiment, when the addresses of the CPU-side access (at 1/st) and the memory bus-side access (7') are different, both accesses can be processed without making the block wait. C even without a load buffer
The block size can be increased without having to wait for access to the PU's cache memory. Accesses on the CPU side are made to wait only when simultaneous accesses are made to addresses.

FIG. 2 is a block diagram of a second embodiment of the invention. E
The X-OR gates t-74 and t-75 are connected to the CPU side word address 30.31 and the memory bus side word address 40.31.
41 and output to the AND game door 3.

In this embodiment, the block address on the CPU side ]-o,
In order to make the access on the CPU side wait only when i1 matches the block address 20.21 on the memory bus side, and when the control address 3031 on the CP tJ side matches the word address 40.42 on the memory bus side. , this embodiment has the advantage of suppressing a decrease in CPIJ throughput I- compared to the first embodiment. Note that the word address is an address indicating a word unit of the CPU within a block of rewriting units of the cache memory indicated by the block address hi.

〔Effect of the invention〕

As explained above, the present invention uses an address comparison circuit, a priority control circuit, and a dual-port memory cell array to increase the block size without reducing the throughput of the C13U or adding buffer hardware. This has the effect of improving the fill rate of the cache memory.

1 and 2 are block diagrams of first and second embodiments of the present invention.

DESCRIPTION OF SYMBOLS 1... Address comparison circuit, 2... Priority control circuit, 3... Dual port memory cell array, 4゜5.
...Decoder, 6...I/O circuit, /O. 11...
CPU side block address, 20.21...Memory bus side block address, 30.31...CP IJ
Side control address 40.41...Memory bus side word address 1/...S, 51...Address comparison circuit output line,
52.53...Priority control circuit output line, 61...
CPU data, 62...Memory bus side data, 71,
72.74.75...EXOR game 1-573...
AND gate, 81, 82.84.85...EX-O
R gate output line.

Agent Patent Attorney Susumu Uchihara

[Brief explanation of the drawing]

sword flash yeah ? figure

Claims (1)

[Claims] A comparison circuit that compares the block address on the CPU side and a block address on the memory bus side and outputs a match signal when they match, and a comparison circuit that outputs a match signal when the two addresses match, and a comparison circuit that controls access to either address when the two addresses match. A priority control circuit that returns an enable signal to be prioritized and a busy signal indicating that it is waiting to the other one, and a block address on the CPU side and a block address on the memory bus side, each connected to one of the first and second decoders to which an enable signal is connected; and a dual port connected to the first and second decoders, respectively, and to the CPU side data and the memory bus side data via I/O circuits. - A cache memory characterized by comprising a memory cell array.